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690 lines
18 KiB
690 lines
18 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* tegra30_ahub.c - Tegra30 AHUB driver |
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* |
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* Copyright (c) 2011,2012, NVIDIA CORPORATION. All rights reserved. |
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*/ |
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|
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#include <linux/clk.h> |
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#include <linux/device.h> |
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#include <linux/io.h> |
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#include <linux/module.h> |
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#include <linux/of_platform.h> |
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#include <linux/platform_device.h> |
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#include <linux/pm_runtime.h> |
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#include <linux/regmap.h> |
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#include <linux/reset.h> |
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#include <linux/slab.h> |
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#include <sound/soc.h> |
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#include "tegra30_ahub.h" |
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#define DRV_NAME "tegra30-ahub" |
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static struct tegra30_ahub *ahub; |
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static inline void tegra30_apbif_write(u32 reg, u32 val) |
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{ |
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regmap_write(ahub->regmap_apbif, reg, val); |
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} |
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static inline u32 tegra30_apbif_read(u32 reg) |
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{ |
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u32 val; |
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regmap_read(ahub->regmap_apbif, reg, &val); |
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return val; |
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} |
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static inline void tegra30_audio_write(u32 reg, u32 val) |
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{ |
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regmap_write(ahub->regmap_ahub, reg, val); |
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} |
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static __maybe_unused int tegra30_ahub_runtime_suspend(struct device *dev) |
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{ |
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regcache_cache_only(ahub->regmap_apbif, true); |
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regcache_cache_only(ahub->regmap_ahub, true); |
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clk_bulk_disable_unprepare(ahub->nclocks, ahub->clocks); |
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return 0; |
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} |
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/* |
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* clk_apbif isn't required for an I2S<->I2S configuration where no PCM data |
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* is read from or sent to memory. However, that's not something the rest of |
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* the driver supports right now, so we'll just treat the two clocks as one |
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* for now. |
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* |
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* These functions should not be a plain ref-count. Instead, each active stream |
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* contributes some requirement to the minimum clock rate, so starting or |
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* stopping streams should dynamically adjust the clock as required. However, |
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* this is not yet implemented. |
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*/ |
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static __maybe_unused int tegra30_ahub_runtime_resume(struct device *dev) |
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{ |
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int ret; |
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ret = reset_control_bulk_assert(ahub->nresets, ahub->resets); |
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if (ret) |
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return ret; |
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ret = clk_bulk_prepare_enable(ahub->nclocks, ahub->clocks); |
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if (ret) |
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return ret; |
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usleep_range(10, 100); |
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ret = reset_control_bulk_deassert(ahub->nresets, ahub->resets); |
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if (ret) |
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goto disable_clocks; |
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regcache_cache_only(ahub->regmap_apbif, false); |
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regcache_cache_only(ahub->regmap_ahub, false); |
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regcache_mark_dirty(ahub->regmap_apbif); |
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regcache_mark_dirty(ahub->regmap_ahub); |
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ret = regcache_sync(ahub->regmap_apbif); |
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if (ret) |
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goto disable_clocks; |
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ret = regcache_sync(ahub->regmap_ahub); |
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if (ret) |
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goto disable_clocks; |
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return 0; |
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disable_clocks: |
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clk_bulk_disable_unprepare(ahub->nclocks, ahub->clocks); |
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return ret; |
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} |
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int tegra30_ahub_allocate_rx_fifo(enum tegra30_ahub_rxcif *rxcif, |
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char *dmachan, int dmachan_len, |
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dma_addr_t *fiforeg) |
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{ |
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int channel; |
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u32 reg, val; |
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struct tegra30_ahub_cif_conf cif_conf; |
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channel = find_first_zero_bit(ahub->rx_usage, |
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TEGRA30_AHUB_CHANNEL_CTRL_COUNT); |
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if (channel >= TEGRA30_AHUB_CHANNEL_CTRL_COUNT) |
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return -EBUSY; |
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__set_bit(channel, ahub->rx_usage); |
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*rxcif = TEGRA30_AHUB_RXCIF_APBIF_RX0 + channel; |
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snprintf(dmachan, dmachan_len, "rx%d", channel); |
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*fiforeg = ahub->apbif_addr + TEGRA30_AHUB_CHANNEL_RXFIFO + |
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(channel * TEGRA30_AHUB_CHANNEL_RXFIFO_STRIDE); |
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pm_runtime_get_sync(ahub->dev); |
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reg = TEGRA30_AHUB_CHANNEL_CTRL + |
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(channel * TEGRA30_AHUB_CHANNEL_CTRL_STRIDE); |
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val = tegra30_apbif_read(reg); |
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val &= ~(TEGRA30_AHUB_CHANNEL_CTRL_RX_THRESHOLD_MASK | |
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TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_MASK); |
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val |= (7 << TEGRA30_AHUB_CHANNEL_CTRL_RX_THRESHOLD_SHIFT) | |
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TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_EN | |
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TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_16; |
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tegra30_apbif_write(reg, val); |
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cif_conf.threshold = 0; |
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cif_conf.audio_channels = 2; |
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cif_conf.client_channels = 2; |
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cif_conf.audio_bits = TEGRA30_AUDIOCIF_BITS_16; |
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cif_conf.client_bits = TEGRA30_AUDIOCIF_BITS_16; |
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cif_conf.expand = 0; |
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cif_conf.stereo_conv = 0; |
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cif_conf.replicate = 0; |
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cif_conf.direction = TEGRA30_AUDIOCIF_DIRECTION_RX; |
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cif_conf.truncate = 0; |
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cif_conf.mono_conv = 0; |
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reg = TEGRA30_AHUB_CIF_RX_CTRL + |
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(channel * TEGRA30_AHUB_CIF_RX_CTRL_STRIDE); |
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ahub->soc_data->set_audio_cif(ahub->regmap_apbif, reg, &cif_conf); |
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pm_runtime_put(ahub->dev); |
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return 0; |
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} |
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EXPORT_SYMBOL_GPL(tegra30_ahub_allocate_rx_fifo); |
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int tegra30_ahub_enable_rx_fifo(enum tegra30_ahub_rxcif rxcif) |
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{ |
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int channel = rxcif - TEGRA30_AHUB_RXCIF_APBIF_RX0; |
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int reg, val; |
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pm_runtime_get_sync(ahub->dev); |
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reg = TEGRA30_AHUB_CHANNEL_CTRL + |
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(channel * TEGRA30_AHUB_CHANNEL_CTRL_STRIDE); |
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val = tegra30_apbif_read(reg); |
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val |= TEGRA30_AHUB_CHANNEL_CTRL_RX_EN; |
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tegra30_apbif_write(reg, val); |
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pm_runtime_put(ahub->dev); |
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return 0; |
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} |
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EXPORT_SYMBOL_GPL(tegra30_ahub_enable_rx_fifo); |
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int tegra30_ahub_disable_rx_fifo(enum tegra30_ahub_rxcif rxcif) |
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{ |
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int channel = rxcif - TEGRA30_AHUB_RXCIF_APBIF_RX0; |
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int reg, val; |
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pm_runtime_get_sync(ahub->dev); |
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reg = TEGRA30_AHUB_CHANNEL_CTRL + |
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(channel * TEGRA30_AHUB_CHANNEL_CTRL_STRIDE); |
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val = tegra30_apbif_read(reg); |
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val &= ~TEGRA30_AHUB_CHANNEL_CTRL_RX_EN; |
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tegra30_apbif_write(reg, val); |
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pm_runtime_put(ahub->dev); |
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return 0; |
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} |
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EXPORT_SYMBOL_GPL(tegra30_ahub_disable_rx_fifo); |
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int tegra30_ahub_free_rx_fifo(enum tegra30_ahub_rxcif rxcif) |
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{ |
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int channel = rxcif - TEGRA30_AHUB_RXCIF_APBIF_RX0; |
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__clear_bit(channel, ahub->rx_usage); |
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return 0; |
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} |
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EXPORT_SYMBOL_GPL(tegra30_ahub_free_rx_fifo); |
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int tegra30_ahub_allocate_tx_fifo(enum tegra30_ahub_txcif *txcif, |
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char *dmachan, int dmachan_len, |
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dma_addr_t *fiforeg) |
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{ |
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int channel; |
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u32 reg, val; |
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struct tegra30_ahub_cif_conf cif_conf; |
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channel = find_first_zero_bit(ahub->tx_usage, |
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TEGRA30_AHUB_CHANNEL_CTRL_COUNT); |
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if (channel >= TEGRA30_AHUB_CHANNEL_CTRL_COUNT) |
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return -EBUSY; |
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__set_bit(channel, ahub->tx_usage); |
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*txcif = TEGRA30_AHUB_TXCIF_APBIF_TX0 + channel; |
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snprintf(dmachan, dmachan_len, "tx%d", channel); |
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*fiforeg = ahub->apbif_addr + TEGRA30_AHUB_CHANNEL_TXFIFO + |
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(channel * TEGRA30_AHUB_CHANNEL_TXFIFO_STRIDE); |
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pm_runtime_get_sync(ahub->dev); |
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reg = TEGRA30_AHUB_CHANNEL_CTRL + |
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(channel * TEGRA30_AHUB_CHANNEL_CTRL_STRIDE); |
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val = tegra30_apbif_read(reg); |
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val &= ~(TEGRA30_AHUB_CHANNEL_CTRL_TX_THRESHOLD_MASK | |
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TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_MASK); |
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val |= (7 << TEGRA30_AHUB_CHANNEL_CTRL_TX_THRESHOLD_SHIFT) | |
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TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_EN | |
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TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_16; |
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tegra30_apbif_write(reg, val); |
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cif_conf.threshold = 0; |
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cif_conf.audio_channels = 2; |
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cif_conf.client_channels = 2; |
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cif_conf.audio_bits = TEGRA30_AUDIOCIF_BITS_16; |
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cif_conf.client_bits = TEGRA30_AUDIOCIF_BITS_16; |
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cif_conf.expand = 0; |
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cif_conf.stereo_conv = 0; |
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cif_conf.replicate = 0; |
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cif_conf.direction = TEGRA30_AUDIOCIF_DIRECTION_TX; |
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cif_conf.truncate = 0; |
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cif_conf.mono_conv = 0; |
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reg = TEGRA30_AHUB_CIF_TX_CTRL + |
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(channel * TEGRA30_AHUB_CIF_TX_CTRL_STRIDE); |
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ahub->soc_data->set_audio_cif(ahub->regmap_apbif, reg, &cif_conf); |
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pm_runtime_put(ahub->dev); |
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return 0; |
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} |
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EXPORT_SYMBOL_GPL(tegra30_ahub_allocate_tx_fifo); |
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int tegra30_ahub_enable_tx_fifo(enum tegra30_ahub_txcif txcif) |
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{ |
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int channel = txcif - TEGRA30_AHUB_TXCIF_APBIF_TX0; |
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int reg, val; |
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pm_runtime_get_sync(ahub->dev); |
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reg = TEGRA30_AHUB_CHANNEL_CTRL + |
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(channel * TEGRA30_AHUB_CHANNEL_CTRL_STRIDE); |
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val = tegra30_apbif_read(reg); |
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val |= TEGRA30_AHUB_CHANNEL_CTRL_TX_EN; |
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tegra30_apbif_write(reg, val); |
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pm_runtime_put(ahub->dev); |
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return 0; |
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} |
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EXPORT_SYMBOL_GPL(tegra30_ahub_enable_tx_fifo); |
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int tegra30_ahub_disable_tx_fifo(enum tegra30_ahub_txcif txcif) |
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{ |
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int channel = txcif - TEGRA30_AHUB_TXCIF_APBIF_TX0; |
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int reg, val; |
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pm_runtime_get_sync(ahub->dev); |
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reg = TEGRA30_AHUB_CHANNEL_CTRL + |
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(channel * TEGRA30_AHUB_CHANNEL_CTRL_STRIDE); |
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val = tegra30_apbif_read(reg); |
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val &= ~TEGRA30_AHUB_CHANNEL_CTRL_TX_EN; |
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tegra30_apbif_write(reg, val); |
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pm_runtime_put(ahub->dev); |
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return 0; |
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} |
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EXPORT_SYMBOL_GPL(tegra30_ahub_disable_tx_fifo); |
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int tegra30_ahub_free_tx_fifo(enum tegra30_ahub_txcif txcif) |
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{ |
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int channel = txcif - TEGRA30_AHUB_TXCIF_APBIF_TX0; |
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__clear_bit(channel, ahub->tx_usage); |
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return 0; |
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} |
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EXPORT_SYMBOL_GPL(tegra30_ahub_free_tx_fifo); |
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int tegra30_ahub_set_rx_cif_source(enum tegra30_ahub_rxcif rxcif, |
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enum tegra30_ahub_txcif txcif) |
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{ |
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int channel = rxcif - TEGRA30_AHUB_RXCIF_APBIF_RX0; |
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int reg; |
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pm_runtime_get_sync(ahub->dev); |
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reg = TEGRA30_AHUB_AUDIO_RX + |
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(channel * TEGRA30_AHUB_AUDIO_RX_STRIDE); |
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tegra30_audio_write(reg, 1 << txcif); |
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pm_runtime_put(ahub->dev); |
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return 0; |
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} |
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EXPORT_SYMBOL_GPL(tegra30_ahub_set_rx_cif_source); |
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int tegra30_ahub_unset_rx_cif_source(enum tegra30_ahub_rxcif rxcif) |
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{ |
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int channel = rxcif - TEGRA30_AHUB_RXCIF_APBIF_RX0; |
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int reg; |
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pm_runtime_get_sync(ahub->dev); |
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reg = TEGRA30_AHUB_AUDIO_RX + |
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(channel * TEGRA30_AHUB_AUDIO_RX_STRIDE); |
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tegra30_audio_write(reg, 0); |
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pm_runtime_put(ahub->dev); |
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return 0; |
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} |
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EXPORT_SYMBOL_GPL(tegra30_ahub_unset_rx_cif_source); |
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static const struct reset_control_bulk_data tegra30_ahub_resets_data[] = { |
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{ "d_audio" }, |
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{ "apbif" }, |
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{ "i2s0" }, |
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{ "i2s1" }, |
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{ "i2s2" }, |
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{ "i2s3" }, |
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{ "i2s4" }, |
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{ "dam0" }, |
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{ "dam1" }, |
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{ "dam2" }, |
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{ "spdif" }, |
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{ "amx" }, /* Tegra114+ */ |
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{ "adx" }, /* Tegra114+ */ |
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{ "amx1" }, /* Tegra124 */ |
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{ "adx1" }, /* Tegra124 */ |
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{ "afc0" }, /* Tegra124 */ |
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{ "afc1" }, /* Tegra124 */ |
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{ "afc2" }, /* Tegra124 */ |
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{ "afc3" }, /* Tegra124 */ |
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{ "afc4" }, /* Tegra124 */ |
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{ "afc5" }, /* Tegra124 */ |
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}; |
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#define LAST_REG(name) \ |
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(TEGRA30_AHUB_##name + \ |
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(TEGRA30_AHUB_##name##_STRIDE * TEGRA30_AHUB_##name##_COUNT) - 4) |
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#define REG_IN_ARRAY(reg, name) \ |
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((reg >= TEGRA30_AHUB_##name) && \ |
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(reg <= LAST_REG(name) && \ |
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(!((reg - TEGRA30_AHUB_##name) % TEGRA30_AHUB_##name##_STRIDE)))) |
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static bool tegra30_ahub_apbif_wr_rd_reg(struct device *dev, unsigned int reg) |
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{ |
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switch (reg) { |
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case TEGRA30_AHUB_CONFIG_LINK_CTRL: |
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case TEGRA30_AHUB_MISC_CTRL: |
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case TEGRA30_AHUB_APBDMA_LIVE_STATUS: |
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case TEGRA30_AHUB_I2S_LIVE_STATUS: |
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case TEGRA30_AHUB_SPDIF_LIVE_STATUS: |
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case TEGRA30_AHUB_I2S_INT_MASK: |
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case TEGRA30_AHUB_DAM_INT_MASK: |
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case TEGRA30_AHUB_SPDIF_INT_MASK: |
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case TEGRA30_AHUB_APBIF_INT_MASK: |
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case TEGRA30_AHUB_I2S_INT_STATUS: |
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case TEGRA30_AHUB_DAM_INT_STATUS: |
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case TEGRA30_AHUB_SPDIF_INT_STATUS: |
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case TEGRA30_AHUB_APBIF_INT_STATUS: |
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case TEGRA30_AHUB_I2S_INT_SOURCE: |
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case TEGRA30_AHUB_DAM_INT_SOURCE: |
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case TEGRA30_AHUB_SPDIF_INT_SOURCE: |
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case TEGRA30_AHUB_APBIF_INT_SOURCE: |
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case TEGRA30_AHUB_I2S_INT_SET: |
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case TEGRA30_AHUB_DAM_INT_SET: |
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case TEGRA30_AHUB_SPDIF_INT_SET: |
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case TEGRA30_AHUB_APBIF_INT_SET: |
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return true; |
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default: |
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break; |
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} |
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if (REG_IN_ARRAY(reg, CHANNEL_CTRL) || |
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REG_IN_ARRAY(reg, CHANNEL_CLEAR) || |
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REG_IN_ARRAY(reg, CHANNEL_STATUS) || |
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REG_IN_ARRAY(reg, CHANNEL_TXFIFO) || |
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REG_IN_ARRAY(reg, CHANNEL_RXFIFO) || |
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REG_IN_ARRAY(reg, CIF_TX_CTRL) || |
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REG_IN_ARRAY(reg, CIF_RX_CTRL) || |
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REG_IN_ARRAY(reg, DAM_LIVE_STATUS)) |
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return true; |
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return false; |
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} |
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static bool tegra30_ahub_apbif_volatile_reg(struct device *dev, |
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unsigned int reg) |
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{ |
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switch (reg) { |
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case TEGRA30_AHUB_CONFIG_LINK_CTRL: |
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case TEGRA30_AHUB_MISC_CTRL: |
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case TEGRA30_AHUB_APBDMA_LIVE_STATUS: |
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case TEGRA30_AHUB_I2S_LIVE_STATUS: |
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case TEGRA30_AHUB_SPDIF_LIVE_STATUS: |
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case TEGRA30_AHUB_I2S_INT_STATUS: |
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case TEGRA30_AHUB_DAM_INT_STATUS: |
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case TEGRA30_AHUB_SPDIF_INT_STATUS: |
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case TEGRA30_AHUB_APBIF_INT_STATUS: |
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case TEGRA30_AHUB_I2S_INT_SET: |
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case TEGRA30_AHUB_DAM_INT_SET: |
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case TEGRA30_AHUB_SPDIF_INT_SET: |
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case TEGRA30_AHUB_APBIF_INT_SET: |
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return true; |
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default: |
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break; |
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} |
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if (REG_IN_ARRAY(reg, CHANNEL_CLEAR) || |
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REG_IN_ARRAY(reg, CHANNEL_STATUS) || |
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REG_IN_ARRAY(reg, CHANNEL_TXFIFO) || |
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REG_IN_ARRAY(reg, CHANNEL_RXFIFO) || |
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REG_IN_ARRAY(reg, DAM_LIVE_STATUS)) |
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return true; |
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return false; |
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} |
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static bool tegra30_ahub_apbif_precious_reg(struct device *dev, |
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unsigned int reg) |
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{ |
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if (REG_IN_ARRAY(reg, CHANNEL_TXFIFO) || |
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REG_IN_ARRAY(reg, CHANNEL_RXFIFO)) |
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return true; |
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return false; |
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} |
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static const struct regmap_config tegra30_ahub_apbif_regmap_config = { |
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.name = "apbif", |
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.reg_bits = 32, |
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.val_bits = 32, |
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.reg_stride = 4, |
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.max_register = TEGRA30_AHUB_APBIF_INT_SET, |
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.writeable_reg = tegra30_ahub_apbif_wr_rd_reg, |
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.readable_reg = tegra30_ahub_apbif_wr_rd_reg, |
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.volatile_reg = tegra30_ahub_apbif_volatile_reg, |
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.precious_reg = tegra30_ahub_apbif_precious_reg, |
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.cache_type = REGCACHE_FLAT, |
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}; |
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static bool tegra30_ahub_ahub_wr_rd_reg(struct device *dev, unsigned int reg) |
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{ |
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if (REG_IN_ARRAY(reg, AUDIO_RX)) |
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return true; |
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return false; |
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} |
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static const struct regmap_config tegra30_ahub_ahub_regmap_config = { |
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.name = "ahub", |
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.reg_bits = 32, |
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.val_bits = 32, |
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.reg_stride = 4, |
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.max_register = LAST_REG(AUDIO_RX), |
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.writeable_reg = tegra30_ahub_ahub_wr_rd_reg, |
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.readable_reg = tegra30_ahub_ahub_wr_rd_reg, |
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.cache_type = REGCACHE_FLAT, |
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}; |
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static struct tegra30_ahub_soc_data soc_data_tegra30 = { |
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.num_resets = 11, |
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.set_audio_cif = tegra30_ahub_set_cif, |
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}; |
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static struct tegra30_ahub_soc_data soc_data_tegra114 = { |
|
.num_resets = 13, |
|
.set_audio_cif = tegra30_ahub_set_cif, |
|
}; |
|
|
|
static struct tegra30_ahub_soc_data soc_data_tegra124 = { |
|
.num_resets = 21, |
|
.set_audio_cif = tegra124_ahub_set_cif, |
|
}; |
|
|
|
static const struct of_device_id tegra30_ahub_of_match[] = { |
|
{ .compatible = "nvidia,tegra124-ahub", .data = &soc_data_tegra124 }, |
|
{ .compatible = "nvidia,tegra114-ahub", .data = &soc_data_tegra114 }, |
|
{ .compatible = "nvidia,tegra30-ahub", .data = &soc_data_tegra30 }, |
|
{}, |
|
}; |
|
|
|
static int tegra30_ahub_probe(struct platform_device *pdev) |
|
{ |
|
const struct tegra30_ahub_soc_data *soc_data; |
|
struct resource *res0; |
|
void __iomem *regs_apbif, *regs_ahub; |
|
int ret = 0; |
|
|
|
soc_data = of_device_get_match_data(&pdev->dev); |
|
if (!soc_data) |
|
return -EINVAL; |
|
|
|
ahub = devm_kzalloc(&pdev->dev, sizeof(struct tegra30_ahub), |
|
GFP_KERNEL); |
|
if (!ahub) |
|
return -ENOMEM; |
|
dev_set_drvdata(&pdev->dev, ahub); |
|
|
|
BUILD_BUG_ON(sizeof(ahub->resets) != sizeof(tegra30_ahub_resets_data)); |
|
memcpy(ahub->resets, tegra30_ahub_resets_data, sizeof(ahub->resets)); |
|
|
|
ahub->nresets = soc_data->num_resets; |
|
ahub->soc_data = soc_data; |
|
ahub->dev = &pdev->dev; |
|
|
|
ahub->clocks[ahub->nclocks++].id = "apbif"; |
|
ahub->clocks[ahub->nclocks++].id = "d_audio"; |
|
|
|
ret = devm_clk_bulk_get(&pdev->dev, ahub->nclocks, ahub->clocks); |
|
if (ret) |
|
goto err_unset_ahub; |
|
|
|
ret = devm_reset_control_bulk_get_exclusive(&pdev->dev, ahub->nresets, |
|
ahub->resets); |
|
if (ret) { |
|
dev_err(&pdev->dev, "Can't get resets: %d\n", ret); |
|
goto err_unset_ahub; |
|
} |
|
|
|
regs_apbif = devm_platform_get_and_ioremap_resource(pdev, 0, &res0); |
|
if (IS_ERR(regs_apbif)) { |
|
ret = PTR_ERR(regs_apbif); |
|
goto err_unset_ahub; |
|
} |
|
|
|
ahub->apbif_addr = res0->start; |
|
|
|
ahub->regmap_apbif = devm_regmap_init_mmio(&pdev->dev, regs_apbif, |
|
&tegra30_ahub_apbif_regmap_config); |
|
if (IS_ERR(ahub->regmap_apbif)) { |
|
dev_err(&pdev->dev, "apbif regmap init failed\n"); |
|
ret = PTR_ERR(ahub->regmap_apbif); |
|
goto err_unset_ahub; |
|
} |
|
regcache_cache_only(ahub->regmap_apbif, true); |
|
|
|
regs_ahub = devm_platform_ioremap_resource(pdev, 1); |
|
if (IS_ERR(regs_ahub)) { |
|
ret = PTR_ERR(regs_ahub); |
|
goto err_unset_ahub; |
|
} |
|
|
|
ahub->regmap_ahub = devm_regmap_init_mmio(&pdev->dev, regs_ahub, |
|
&tegra30_ahub_ahub_regmap_config); |
|
if (IS_ERR(ahub->regmap_ahub)) { |
|
dev_err(&pdev->dev, "ahub regmap init failed\n"); |
|
ret = PTR_ERR(ahub->regmap_ahub); |
|
goto err_unset_ahub; |
|
} |
|
regcache_cache_only(ahub->regmap_ahub, true); |
|
|
|
pm_runtime_enable(&pdev->dev); |
|
|
|
of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev); |
|
|
|
return 0; |
|
|
|
err_unset_ahub: |
|
ahub = NULL; |
|
|
|
return ret; |
|
} |
|
|
|
static int tegra30_ahub_remove(struct platform_device *pdev) |
|
{ |
|
pm_runtime_disable(&pdev->dev); |
|
|
|
ahub = NULL; |
|
|
|
return 0; |
|
} |
|
|
|
static const struct dev_pm_ops tegra30_ahub_pm_ops = { |
|
SET_RUNTIME_PM_OPS(tegra30_ahub_runtime_suspend, |
|
tegra30_ahub_runtime_resume, NULL) |
|
SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, |
|
pm_runtime_force_resume) |
|
}; |
|
|
|
static struct platform_driver tegra30_ahub_driver = { |
|
.probe = tegra30_ahub_probe, |
|
.remove = tegra30_ahub_remove, |
|
.driver = { |
|
.name = DRV_NAME, |
|
.of_match_table = tegra30_ahub_of_match, |
|
.pm = &tegra30_ahub_pm_ops, |
|
}, |
|
}; |
|
module_platform_driver(tegra30_ahub_driver); |
|
|
|
void tegra30_ahub_set_cif(struct regmap *regmap, unsigned int reg, |
|
struct tegra30_ahub_cif_conf *conf) |
|
{ |
|
unsigned int value; |
|
|
|
value = (conf->threshold << |
|
TEGRA30_AUDIOCIF_CTRL_FIFO_THRESHOLD_SHIFT) | |
|
((conf->audio_channels - 1) << |
|
TEGRA30_AUDIOCIF_CTRL_AUDIO_CHANNELS_SHIFT) | |
|
((conf->client_channels - 1) << |
|
TEGRA30_AUDIOCIF_CTRL_CLIENT_CHANNELS_SHIFT) | |
|
(conf->audio_bits << |
|
TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT) | |
|
(conf->client_bits << |
|
TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT) | |
|
(conf->expand << |
|
TEGRA30_AUDIOCIF_CTRL_EXPAND_SHIFT) | |
|
(conf->stereo_conv << |
|
TEGRA30_AUDIOCIF_CTRL_STEREO_CONV_SHIFT) | |
|
(conf->replicate << |
|
TEGRA30_AUDIOCIF_CTRL_REPLICATE_SHIFT) | |
|
(conf->direction << |
|
TEGRA30_AUDIOCIF_CTRL_DIRECTION_SHIFT) | |
|
(conf->truncate << |
|
TEGRA30_AUDIOCIF_CTRL_TRUNCATE_SHIFT) | |
|
(conf->mono_conv << |
|
TEGRA30_AUDIOCIF_CTRL_MONO_CONV_SHIFT); |
|
|
|
regmap_write(regmap, reg, value); |
|
} |
|
EXPORT_SYMBOL_GPL(tegra30_ahub_set_cif); |
|
|
|
void tegra124_ahub_set_cif(struct regmap *regmap, unsigned int reg, |
|
struct tegra30_ahub_cif_conf *conf) |
|
{ |
|
unsigned int value; |
|
|
|
value = (conf->threshold << |
|
TEGRA124_AUDIOCIF_CTRL_FIFO_THRESHOLD_SHIFT) | |
|
((conf->audio_channels - 1) << |
|
TEGRA124_AUDIOCIF_CTRL_AUDIO_CHANNELS_SHIFT) | |
|
((conf->client_channels - 1) << |
|
TEGRA124_AUDIOCIF_CTRL_CLIENT_CHANNELS_SHIFT) | |
|
(conf->audio_bits << |
|
TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT) | |
|
(conf->client_bits << |
|
TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT) | |
|
(conf->expand << |
|
TEGRA30_AUDIOCIF_CTRL_EXPAND_SHIFT) | |
|
(conf->stereo_conv << |
|
TEGRA30_AUDIOCIF_CTRL_STEREO_CONV_SHIFT) | |
|
(conf->replicate << |
|
TEGRA30_AUDIOCIF_CTRL_REPLICATE_SHIFT) | |
|
(conf->direction << |
|
TEGRA30_AUDIOCIF_CTRL_DIRECTION_SHIFT) | |
|
(conf->truncate << |
|
TEGRA30_AUDIOCIF_CTRL_TRUNCATE_SHIFT) | |
|
(conf->mono_conv << |
|
TEGRA30_AUDIOCIF_CTRL_MONO_CONV_SHIFT); |
|
|
|
regmap_write(regmap, reg, value); |
|
} |
|
EXPORT_SYMBOL_GPL(tegra124_ahub_set_cif); |
|
|
|
MODULE_AUTHOR("Stephen Warren <[email protected]>"); |
|
MODULE_DESCRIPTION("Tegra30 AHUB driver"); |
|
MODULE_LICENSE("GPL v2"); |
|
MODULE_ALIAS("platform:" DRV_NAME); |
|
MODULE_DEVICE_TABLE(of, tegra30_ahub_of_match);
|
|
|