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72 lines
2.5 KiB
72 lines
2.5 KiB
/* SPDX-License-Identifier: GPL-2.0-only */ |
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/* |
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* tegra210_adx.h - Definitions for Tegra210 ADX driver |
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* |
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* Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved. |
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* |
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*/ |
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#ifndef __TEGRA210_ADX_H__ |
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#define __TEGRA210_ADX_H__ |
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/* Register offsets from TEGRA210_ADX*_BASE */ |
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#define TEGRA210_ADX_RX_STATUS 0x0c |
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#define TEGRA210_ADX_RX_INT_STATUS 0x10 |
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#define TEGRA210_ADX_RX_INT_MASK 0x14 |
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#define TEGRA210_ADX_RX_INT_SET 0x18 |
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#define TEGRA210_ADX_RX_INT_CLEAR 0x1c |
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#define TEGRA210_ADX_RX_CIF_CTRL 0x20 |
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#define TEGRA210_ADX_TX_STATUS 0x4c |
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#define TEGRA210_ADX_TX_INT_STATUS 0x50 |
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#define TEGRA210_ADX_TX_INT_MASK 0x54 |
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#define TEGRA210_ADX_TX_INT_SET 0x58 |
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#define TEGRA210_ADX_TX_INT_CLEAR 0x5c |
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#define TEGRA210_ADX_TX1_CIF_CTRL 0x60 |
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#define TEGRA210_ADX_TX2_CIF_CTRL 0x64 |
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#define TEGRA210_ADX_TX3_CIF_CTRL 0x68 |
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#define TEGRA210_ADX_TX4_CIF_CTRL 0x6c |
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#define TEGRA210_ADX_ENABLE 0x80 |
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#define TEGRA210_ADX_SOFT_RESET 0x84 |
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#define TEGRA210_ADX_CG 0x88 |
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#define TEGRA210_ADX_STATUS 0x8c |
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#define TEGRA210_ADX_INT_STATUS 0x90 |
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#define TEGRA210_ADX_CTRL 0xa4 |
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#define TEGRA210_ADX_IN_BYTE_EN0 0xa8 |
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#define TEGRA210_ADX_IN_BYTE_EN1 0xac |
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#define TEGRA210_ADX_CFG_RAM_CTRL 0xb8 |
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#define TEGRA210_ADX_CFG_RAM_DATA 0xbc |
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/* Fields in TEGRA210_ADX_ENABLE */ |
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#define TEGRA210_ADX_ENABLE_SHIFT 0 |
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/* Fields in TEGRA210_ADX_CFG_RAM_CTRL */ |
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#define TEGRA210_ADX_CFG_RAM_CTRL_RAM_ADDR_SHIFT 0 |
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#define TEGRA210_ADX_CFG_RAM_CTRL_RW_SHIFT 14 |
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#define TEGRA210_ADX_CFG_RAM_CTRL_RW_WRITE (1 << TEGRA210_ADX_CFG_RAM_CTRL_RW_SHIFT) |
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#define TEGRA210_ADX_CFG_RAM_CTRL_ADDR_INIT_EN_SHIFT 13 |
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#define TEGRA210_ADX_CFG_RAM_CTRL_ADDR_INIT_EN (1 << TEGRA210_ADX_CFG_RAM_CTRL_ADDR_INIT_EN_SHIFT) |
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#define TEGRA210_ADX_CFG_RAM_CTRL_SEQ_ACCESS_EN_SHIFT 12 |
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#define TEGRA210_ADX_CFG_RAM_CTRL_SEQ_ACCESS_EN (1 << TEGRA210_ADX_CFG_RAM_CTRL_SEQ_ACCESS_EN_SHIFT) |
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/* Fields in TEGRA210_ADX_SOFT_RESET */ |
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#define TEGRA210_ADX_SOFT_RESET_SOFT_RESET_SHIFT 0 |
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#define TEGRA210_ADX_SOFT_RESET_SOFT_RESET_MASK (1 << TEGRA210_ADX_SOFT_RESET_SOFT_RESET_SHIFT) |
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#define TEGRA210_ADX_SOFT_RESET_SOFT_EN (1 << TEGRA210_ADX_SOFT_RESET_SOFT_RESET_SHIFT) |
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#define TEGRA210_ADX_SOFT_RESET_SOFT_DEFAULT (0 << TEGRA210_ADX_SOFT_RESET_SOFT_RESET_SHIFT) |
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#define TEGRA210_ADX_AUDIOCIF_CH_STRIDE 4 |
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#define TEGRA210_ADX_RAM_DEPTH 16 |
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#define TEGRA210_ADX_MAP_STREAM_NUMBER_SHIFT 6 |
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#define TEGRA210_ADX_MAP_WORD_NUMBER_SHIFT 2 |
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#define TEGRA210_ADX_MAP_BYTE_NUMBER_SHIFT 0 |
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struct tegra210_adx { |
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struct regmap *regmap; |
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unsigned int map[TEGRA210_ADX_RAM_DEPTH]; |
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unsigned int byte_mask[2]; |
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}; |
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#endif
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