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217 lines
5.8 KiB
217 lines
5.8 KiB
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) |
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// |
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// Copyright(c) 2020 Intel Corporation. All rights reserved. |
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// |
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// Author: Fred Oh <[email protected]> |
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// |
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/* |
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* Hardware interface for audio DSP on IceLake. |
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*/ |
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#include <linux/kernel.h> |
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#include <linux/kconfig.h> |
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#include <linux/export.h> |
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#include <linux/bits.h> |
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#include "../ops.h" |
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#include "hda.h" |
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#include "hda-ipc.h" |
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#include "../sof-audio.h" |
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#define ICL_DSP_HPRO_CORE_ID 3 |
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static const struct snd_sof_debugfs_map icl_dsp_debugfs[] = { |
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{"hda", HDA_DSP_HDA_BAR, 0, 0x4000, SOF_DEBUGFS_ACCESS_ALWAYS}, |
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{"pp", HDA_DSP_PP_BAR, 0, 0x1000, SOF_DEBUGFS_ACCESS_ALWAYS}, |
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{"dsp", HDA_DSP_BAR, 0, 0x10000, SOF_DEBUGFS_ACCESS_ALWAYS}, |
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}; |
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static int icl_dsp_core_stall(struct snd_sof_dev *sdev, unsigned int core_mask) |
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{ |
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struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata; |
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const struct sof_intel_dsp_desc *chip = hda->desc; |
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/* make sure core_mask in host managed cores */ |
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core_mask &= chip->host_managed_cores_mask; |
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if (!core_mask) { |
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dev_err(sdev->dev, "error: core_mask is not in host managed cores\n"); |
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return -EINVAL; |
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} |
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/* stall core */ |
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snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPCS, |
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HDA_DSP_ADSPCS_CSTALL_MASK(core_mask), |
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HDA_DSP_ADSPCS_CSTALL_MASK(core_mask)); |
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return 0; |
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} |
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/* |
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* post fw run operation for ICL. |
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* Core 3 will be powered up and in stall when HPRO is enabled |
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*/ |
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static int icl_dsp_post_fw_run(struct snd_sof_dev *sdev) |
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{ |
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struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata; |
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int ret; |
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if (sdev->first_boot) { |
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ret = hda_sdw_startup(sdev); |
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if (ret < 0) { |
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dev_err(sdev->dev, "error: could not startup SoundWire links\n"); |
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return ret; |
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} |
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} |
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hda_sdw_int_enable(sdev, true); |
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/* |
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* The recommended HW programming sequence for ICL is to |
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* power up core 3 and keep it in stall if HPRO is enabled. |
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*/ |
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if (!hda->clk_config_lpro) { |
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ret = hda_dsp_enable_core(sdev, BIT(ICL_DSP_HPRO_CORE_ID)); |
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if (ret < 0) { |
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dev_err(sdev->dev, "error: dsp core power up failed on core %d\n", |
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ICL_DSP_HPRO_CORE_ID); |
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return ret; |
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} |
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sdev->enabled_cores_mask |= BIT(ICL_DSP_HPRO_CORE_ID); |
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sdev->dsp_core_ref_count[ICL_DSP_HPRO_CORE_ID]++; |
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snd_sof_dsp_stall(sdev, BIT(ICL_DSP_HPRO_CORE_ID)); |
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} |
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/* re-enable clock gating and power gating */ |
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return hda_dsp_ctrl_clock_power_gating(sdev, true); |
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} |
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/* Icelake ops */ |
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const struct snd_sof_dsp_ops sof_icl_ops = { |
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/* probe/remove/shutdown */ |
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.probe = hda_dsp_probe, |
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.remove = hda_dsp_remove, |
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.shutdown = hda_dsp_shutdown, |
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/* Register IO */ |
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.write = sof_io_write, |
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.read = sof_io_read, |
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.write64 = sof_io_write64, |
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.read64 = sof_io_read64, |
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/* Block IO */ |
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.block_read = sof_block_read, |
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.block_write = sof_block_write, |
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/* Mailbox IO */ |
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.mailbox_read = sof_mailbox_read, |
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.mailbox_write = sof_mailbox_write, |
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/* doorbell */ |
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.irq_thread = cnl_ipc_irq_thread, |
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/* ipc */ |
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.send_msg = cnl_ipc_send_msg, |
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.fw_ready = sof_fw_ready, |
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.get_mailbox_offset = hda_dsp_ipc_get_mailbox_offset, |
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.get_window_offset = hda_dsp_ipc_get_window_offset, |
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.ipc_msg_data = hda_ipc_msg_data, |
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.ipc_pcm_params = hda_ipc_pcm_params, |
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/* machine driver */ |
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.machine_select = hda_machine_select, |
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.machine_register = sof_machine_register, |
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.machine_unregister = sof_machine_unregister, |
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.set_mach_params = hda_set_mach_params, |
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/* debug */ |
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.debug_map = icl_dsp_debugfs, |
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.debug_map_count = ARRAY_SIZE(icl_dsp_debugfs), |
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.dbg_dump = hda_dsp_dump, |
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.ipc_dump = cnl_ipc_dump, |
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.debugfs_add_region_item = snd_sof_debugfs_add_region_item_iomem, |
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/* stream callbacks */ |
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.pcm_open = hda_dsp_pcm_open, |
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.pcm_close = hda_dsp_pcm_close, |
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.pcm_hw_params = hda_dsp_pcm_hw_params, |
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.pcm_hw_free = hda_dsp_stream_hw_free, |
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.pcm_trigger = hda_dsp_pcm_trigger, |
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.pcm_pointer = hda_dsp_pcm_pointer, |
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.pcm_ack = hda_dsp_pcm_ack, |
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#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA_PROBES) |
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/* probe callbacks */ |
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.probe_assign = hda_probe_compr_assign, |
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.probe_free = hda_probe_compr_free, |
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.probe_set_params = hda_probe_compr_set_params, |
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.probe_trigger = hda_probe_compr_trigger, |
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.probe_pointer = hda_probe_compr_pointer, |
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#endif |
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/* firmware loading */ |
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.load_firmware = snd_sof_load_firmware_raw, |
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/* pre/post fw run */ |
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.pre_fw_run = hda_dsp_pre_fw_run, |
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.post_fw_run = icl_dsp_post_fw_run, |
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/* parse platform specific extended manifest */ |
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.parse_platform_ext_manifest = hda_dsp_ext_man_get_cavs_config_data, |
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/* dsp core get/put */ |
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.core_get = hda_dsp_core_get, |
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/* firmware run */ |
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.run = hda_dsp_cl_boot_firmware_iccmax, |
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.stall = icl_dsp_core_stall, |
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/* trace callback */ |
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.trace_init = hda_dsp_trace_init, |
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.trace_release = hda_dsp_trace_release, |
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.trace_trigger = hda_dsp_trace_trigger, |
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/* DAI drivers */ |
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.drv = skl_dai, |
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.num_drv = SOF_SKL_NUM_DAIS, |
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/* PM */ |
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.suspend = hda_dsp_suspend, |
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.resume = hda_dsp_resume, |
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.runtime_suspend = hda_dsp_runtime_suspend, |
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.runtime_resume = hda_dsp_runtime_resume, |
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.runtime_idle = hda_dsp_runtime_idle, |
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.set_hw_params_upon_resume = hda_dsp_set_hw_params_upon_resume, |
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.set_power_state = hda_dsp_set_power_state, |
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/* ALSA HW info flags */ |
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.hw_info = SNDRV_PCM_INFO_MMAP | |
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SNDRV_PCM_INFO_MMAP_VALID | |
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SNDRV_PCM_INFO_INTERLEAVED | |
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SNDRV_PCM_INFO_PAUSE | |
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SNDRV_PCM_INFO_NO_PERIOD_WAKEUP, |
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.dsp_arch_ops = &sof_xtensa_arch_ops, |
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}; |
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EXPORT_SYMBOL_NS(sof_icl_ops, SND_SOC_SOF_INTEL_HDA_COMMON); |
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const struct sof_intel_dsp_desc icl_chip_info = { |
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/* Icelake */ |
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.cores_num = 4, |
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.init_core_mask = 1, |
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.host_managed_cores_mask = GENMASK(3, 0), |
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.ipc_req = CNL_DSP_REG_HIPCIDR, |
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.ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY, |
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.ipc_ack = CNL_DSP_REG_HIPCIDA, |
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.ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE, |
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.ipc_ctl = CNL_DSP_REG_HIPCCTL, |
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.rom_init_timeout = 300, |
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.ssp_count = ICL_SSP_COUNT, |
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.ssp_base_offset = CNL_SSP_BASE_OFFSET, |
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.sdw_shim_base = SDW_SHIM_BASE, |
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.sdw_alh_base = SDW_ALH_BASE, |
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.check_sdw_irq = hda_common_check_sdw_irq, |
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}; |
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EXPORT_SYMBOL_NS(icl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
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