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892 lines
21 KiB
892 lines
21 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* pxa-ssp.c -- ALSA Soc Audio Layer |
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* |
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* Copyright 2005,2008 Wolfson Microelectronics PLC. |
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* Author: Liam Girdwood |
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* Mark Brown <[email protected]> |
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* |
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* TODO: |
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* o Test network mode for > 16bit sample size |
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*/ |
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|
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#include <linux/init.h> |
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#include <linux/module.h> |
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#include <linux/slab.h> |
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#include <linux/platform_device.h> |
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#include <linux/clk.h> |
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#include <linux/io.h> |
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#include <linux/pxa2xx_ssp.h> |
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#include <linux/of.h> |
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#include <linux/dmaengine.h> |
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|
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#include <asm/irq.h> |
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|
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#include <sound/core.h> |
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#include <sound/pcm.h> |
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#include <sound/initval.h> |
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#include <sound/pcm_params.h> |
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#include <sound/soc.h> |
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#include <sound/pxa2xx-lib.h> |
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#include <sound/dmaengine_pcm.h> |
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#include "pxa-ssp.h" |
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|
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/* |
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* SSP audio private data |
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*/ |
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struct ssp_priv { |
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struct ssp_device *ssp; |
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struct clk *extclk; |
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unsigned long ssp_clk; |
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unsigned int sysclk; |
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unsigned int dai_fmt; |
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unsigned int configured_dai_fmt; |
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#ifdef CONFIG_PM |
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uint32_t cr0; |
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uint32_t cr1; |
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uint32_t to; |
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uint32_t psp; |
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#endif |
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}; |
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|
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static void dump_registers(struct ssp_device *ssp) |
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{ |
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dev_dbg(ssp->dev, "SSCR0 0x%08x SSCR1 0x%08x SSTO 0x%08x\n", |
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pxa_ssp_read_reg(ssp, SSCR0), pxa_ssp_read_reg(ssp, SSCR1), |
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pxa_ssp_read_reg(ssp, SSTO)); |
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dev_dbg(ssp->dev, "SSPSP 0x%08x SSSR 0x%08x SSACD 0x%08x\n", |
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pxa_ssp_read_reg(ssp, SSPSP), pxa_ssp_read_reg(ssp, SSSR), |
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pxa_ssp_read_reg(ssp, SSACD)); |
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} |
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static void pxa_ssp_set_dma_params(struct ssp_device *ssp, int width4, |
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int out, struct snd_dmaengine_dai_dma_data *dma) |
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{ |
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dma->addr_width = width4 ? DMA_SLAVE_BUSWIDTH_4_BYTES : |
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DMA_SLAVE_BUSWIDTH_2_BYTES; |
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dma->maxburst = 16; |
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dma->addr = ssp->phys_base + SSDR; |
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} |
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static int pxa_ssp_startup(struct snd_pcm_substream *substream, |
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struct snd_soc_dai *cpu_dai) |
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{ |
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struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai); |
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struct ssp_device *ssp = priv->ssp; |
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struct snd_dmaengine_dai_dma_data *dma; |
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int ret = 0; |
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if (!snd_soc_dai_active(cpu_dai)) { |
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clk_prepare_enable(ssp->clk); |
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pxa_ssp_disable(ssp); |
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} |
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clk_prepare_enable(priv->extclk); |
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dma = kzalloc(sizeof(struct snd_dmaengine_dai_dma_data), GFP_KERNEL); |
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if (!dma) |
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return -ENOMEM; |
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dma->chan_name = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? |
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"tx" : "rx"; |
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snd_soc_dai_set_dma_data(cpu_dai, substream, dma); |
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return ret; |
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} |
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static void pxa_ssp_shutdown(struct snd_pcm_substream *substream, |
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struct snd_soc_dai *cpu_dai) |
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{ |
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struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai); |
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struct ssp_device *ssp = priv->ssp; |
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if (!snd_soc_dai_active(cpu_dai)) { |
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pxa_ssp_disable(ssp); |
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clk_disable_unprepare(ssp->clk); |
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} |
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clk_disable_unprepare(priv->extclk); |
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kfree(snd_soc_dai_get_dma_data(cpu_dai, substream)); |
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snd_soc_dai_set_dma_data(cpu_dai, substream, NULL); |
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} |
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#ifdef CONFIG_PM |
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static int pxa_ssp_suspend(struct snd_soc_component *component) |
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{ |
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struct ssp_priv *priv = snd_soc_component_get_drvdata(component); |
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struct ssp_device *ssp = priv->ssp; |
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if (!snd_soc_component_active(component)) |
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clk_prepare_enable(ssp->clk); |
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priv->cr0 = __raw_readl(ssp->mmio_base + SSCR0); |
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priv->cr1 = __raw_readl(ssp->mmio_base + SSCR1); |
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priv->to = __raw_readl(ssp->mmio_base + SSTO); |
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priv->psp = __raw_readl(ssp->mmio_base + SSPSP); |
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pxa_ssp_disable(ssp); |
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clk_disable_unprepare(ssp->clk); |
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return 0; |
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} |
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static int pxa_ssp_resume(struct snd_soc_component *component) |
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{ |
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struct ssp_priv *priv = snd_soc_component_get_drvdata(component); |
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struct ssp_device *ssp = priv->ssp; |
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uint32_t sssr = SSSR_ROR | SSSR_TUR | SSSR_BCE; |
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clk_prepare_enable(ssp->clk); |
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__raw_writel(sssr, ssp->mmio_base + SSSR); |
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__raw_writel(priv->cr0 & ~SSCR0_SSE, ssp->mmio_base + SSCR0); |
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__raw_writel(priv->cr1, ssp->mmio_base + SSCR1); |
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__raw_writel(priv->to, ssp->mmio_base + SSTO); |
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__raw_writel(priv->psp, ssp->mmio_base + SSPSP); |
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if (snd_soc_component_active(component)) |
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pxa_ssp_enable(ssp); |
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else |
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clk_disable_unprepare(ssp->clk); |
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return 0; |
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} |
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#else |
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#define pxa_ssp_suspend NULL |
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#define pxa_ssp_resume NULL |
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#endif |
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|
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/* |
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* ssp_set_clkdiv - set SSP clock divider |
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* @div: serial clock rate divider |
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*/ |
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static void pxa_ssp_set_scr(struct ssp_device *ssp, u32 div) |
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{ |
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u32 sscr0 = pxa_ssp_read_reg(ssp, SSCR0); |
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if (ssp->type == PXA25x_SSP) { |
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sscr0 &= ~0x0000ff00; |
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sscr0 |= ((div - 2)/2) << 8; /* 2..512 */ |
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} else { |
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sscr0 &= ~0x000fff00; |
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sscr0 |= (div - 1) << 8; /* 1..4096 */ |
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} |
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pxa_ssp_write_reg(ssp, SSCR0, sscr0); |
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} |
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|
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/* |
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* Set the SSP ports SYSCLK. |
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*/ |
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static int pxa_ssp_set_dai_sysclk(struct snd_soc_dai *cpu_dai, |
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int clk_id, unsigned int freq, int dir) |
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{ |
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struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai); |
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struct ssp_device *ssp = priv->ssp; |
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u32 sscr0 = pxa_ssp_read_reg(ssp, SSCR0) & |
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~(SSCR0_ECS | SSCR0_NCS | SSCR0_MOD | SSCR0_ACS); |
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if (priv->extclk) { |
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int ret; |
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/* |
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* For DT based boards, if an extclk is given, use it |
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* here and configure PXA_SSP_CLK_EXT. |
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*/ |
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ret = clk_set_rate(priv->extclk, freq); |
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if (ret < 0) |
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return ret; |
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clk_id = PXA_SSP_CLK_EXT; |
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} |
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dev_dbg(ssp->dev, |
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"pxa_ssp_set_dai_sysclk id: %d, clk_id %d, freq %u\n", |
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cpu_dai->id, clk_id, freq); |
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switch (clk_id) { |
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case PXA_SSP_CLK_NET_PLL: |
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sscr0 |= SSCR0_MOD; |
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break; |
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case PXA_SSP_CLK_PLL: |
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/* Internal PLL is fixed */ |
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if (ssp->type == PXA25x_SSP) |
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priv->sysclk = 1843200; |
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else |
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priv->sysclk = 13000000; |
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break; |
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case PXA_SSP_CLK_EXT: |
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priv->sysclk = freq; |
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sscr0 |= SSCR0_ECS; |
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break; |
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case PXA_SSP_CLK_NET: |
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priv->sysclk = freq; |
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sscr0 |= SSCR0_NCS | SSCR0_MOD; |
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break; |
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case PXA_SSP_CLK_AUDIO: |
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priv->sysclk = 0; |
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pxa_ssp_set_scr(ssp, 1); |
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sscr0 |= SSCR0_ACS; |
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break; |
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default: |
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return -ENODEV; |
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} |
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/* The SSP clock must be disabled when changing SSP clock mode |
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* on PXA2xx. On PXA3xx it must be enabled when doing so. */ |
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if (ssp->type != PXA3xx_SSP) |
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clk_disable_unprepare(ssp->clk); |
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pxa_ssp_write_reg(ssp, SSCR0, sscr0); |
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if (ssp->type != PXA3xx_SSP) |
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clk_prepare_enable(ssp->clk); |
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return 0; |
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} |
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/* |
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* Configure the PLL frequency pxa27x and (afaik - pxa320 only) |
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*/ |
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static int pxa_ssp_set_pll(struct ssp_priv *priv, unsigned int freq) |
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{ |
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struct ssp_device *ssp = priv->ssp; |
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u32 ssacd = pxa_ssp_read_reg(ssp, SSACD) & ~0x70; |
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if (ssp->type == PXA3xx_SSP) |
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pxa_ssp_write_reg(ssp, SSACDD, 0); |
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switch (freq) { |
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case 5622000: |
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break; |
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case 11345000: |
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ssacd |= (0x1 << 4); |
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break; |
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case 12235000: |
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ssacd |= (0x2 << 4); |
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break; |
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case 14857000: |
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ssacd |= (0x3 << 4); |
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break; |
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case 32842000: |
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ssacd |= (0x4 << 4); |
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break; |
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case 48000000: |
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ssacd |= (0x5 << 4); |
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break; |
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case 0: |
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/* Disable */ |
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break; |
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default: |
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/* PXA3xx has a clock ditherer which can be used to generate |
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* a wider range of frequencies - calculate a value for it. |
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*/ |
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if (ssp->type == PXA3xx_SSP) { |
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u32 val; |
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u64 tmp = 19968; |
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tmp *= 1000000; |
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do_div(tmp, freq); |
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val = tmp; |
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val = (val << 16) | 64; |
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pxa_ssp_write_reg(ssp, SSACDD, val); |
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ssacd |= (0x6 << 4); |
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dev_dbg(ssp->dev, |
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"Using SSACDD %x to supply %uHz\n", |
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val, freq); |
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break; |
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} |
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return -EINVAL; |
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} |
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pxa_ssp_write_reg(ssp, SSACD, ssacd); |
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return 0; |
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} |
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/* |
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* Set the active slots in TDM/Network mode |
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*/ |
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static int pxa_ssp_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, |
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unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width) |
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{ |
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struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai); |
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struct ssp_device *ssp = priv->ssp; |
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u32 sscr0; |
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sscr0 = pxa_ssp_read_reg(ssp, SSCR0); |
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sscr0 &= ~(SSCR0_MOD | SSCR0_SlotsPerFrm(8) | SSCR0_EDSS | SSCR0_DSS); |
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/* set slot width */ |
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if (slot_width > 16) |
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sscr0 |= SSCR0_EDSS | SSCR0_DataSize(slot_width - 16); |
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else |
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sscr0 |= SSCR0_DataSize(slot_width); |
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if (slots > 1) { |
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/* enable network mode */ |
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sscr0 |= SSCR0_MOD; |
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/* set number of active slots */ |
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sscr0 |= SSCR0_SlotsPerFrm(slots); |
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/* set active slot mask */ |
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pxa_ssp_write_reg(ssp, SSTSA, tx_mask); |
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pxa_ssp_write_reg(ssp, SSRSA, rx_mask); |
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} |
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pxa_ssp_write_reg(ssp, SSCR0, sscr0); |
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return 0; |
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} |
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/* |
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* Tristate the SSP DAI lines |
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*/ |
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static int pxa_ssp_set_dai_tristate(struct snd_soc_dai *cpu_dai, |
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int tristate) |
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{ |
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struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai); |
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struct ssp_device *ssp = priv->ssp; |
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u32 sscr1; |
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sscr1 = pxa_ssp_read_reg(ssp, SSCR1); |
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if (tristate) |
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sscr1 &= ~SSCR1_TTE; |
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else |
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sscr1 |= SSCR1_TTE; |
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pxa_ssp_write_reg(ssp, SSCR1, sscr1); |
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return 0; |
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} |
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static int pxa_ssp_set_dai_fmt(struct snd_soc_dai *cpu_dai, |
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unsigned int fmt) |
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{ |
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struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai); |
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switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { |
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case SND_SOC_DAIFMT_CBM_CFM: |
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case SND_SOC_DAIFMT_CBM_CFS: |
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case SND_SOC_DAIFMT_CBS_CFS: |
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break; |
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default: |
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return -EINVAL; |
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} |
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switch (fmt & SND_SOC_DAIFMT_INV_MASK) { |
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case SND_SOC_DAIFMT_NB_NF: |
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case SND_SOC_DAIFMT_NB_IF: |
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case SND_SOC_DAIFMT_IB_IF: |
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case SND_SOC_DAIFMT_IB_NF: |
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break; |
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default: |
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return -EINVAL; |
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} |
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switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { |
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case SND_SOC_DAIFMT_I2S: |
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case SND_SOC_DAIFMT_DSP_A: |
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case SND_SOC_DAIFMT_DSP_B: |
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break; |
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default: |
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return -EINVAL; |
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} |
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/* Settings will be applied in hw_params() */ |
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priv->dai_fmt = fmt; |
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return 0; |
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} |
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/* |
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* Set up the SSP DAI format. |
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* The SSP Port must be inactive before calling this function as the |
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* physical interface format is changed. |
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*/ |
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static int pxa_ssp_configure_dai_fmt(struct ssp_priv *priv) |
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{ |
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struct ssp_device *ssp = priv->ssp; |
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u32 sscr0, sscr1, sspsp, scfr; |
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|
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/* check if we need to change anything at all */ |
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if (priv->configured_dai_fmt == priv->dai_fmt) |
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return 0; |
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|
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/* reset port settings */ |
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sscr0 = pxa_ssp_read_reg(ssp, SSCR0) & |
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~(SSCR0_PSP | SSCR0_MOD); |
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sscr1 = pxa_ssp_read_reg(ssp, SSCR1) & |
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~(SSCR1_SCLKDIR | SSCR1_SFRMDIR | SSCR1_SCFR | |
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SSCR1_RWOT | SSCR1_TRAIL | SSCR1_TFT | SSCR1_RFT); |
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sspsp = pxa_ssp_read_reg(ssp, SSPSP) & |
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~(SSPSP_SFRMP | SSPSP_SCMODE(3)); |
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sscr1 |= SSCR1_RxTresh(8) | SSCR1_TxTresh(7); |
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switch (priv->dai_fmt & SND_SOC_DAIFMT_MASTER_MASK) { |
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case SND_SOC_DAIFMT_CBM_CFM: |
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sscr1 |= SSCR1_SCLKDIR | SSCR1_SFRMDIR | SSCR1_SCFR; |
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break; |
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case SND_SOC_DAIFMT_CBM_CFS: |
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sscr1 |= SSCR1_SCLKDIR | SSCR1_SCFR; |
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break; |
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case SND_SOC_DAIFMT_CBS_CFS: |
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break; |
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default: |
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return -EINVAL; |
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} |
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switch (priv->dai_fmt & SND_SOC_DAIFMT_INV_MASK) { |
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case SND_SOC_DAIFMT_NB_NF: |
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sspsp |= SSPSP_SFRMP; |
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break; |
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case SND_SOC_DAIFMT_NB_IF: |
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break; |
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case SND_SOC_DAIFMT_IB_IF: |
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sspsp |= SSPSP_SCMODE(2); |
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break; |
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case SND_SOC_DAIFMT_IB_NF: |
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sspsp |= SSPSP_SCMODE(2) | SSPSP_SFRMP; |
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break; |
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default: |
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return -EINVAL; |
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} |
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|
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switch (priv->dai_fmt & SND_SOC_DAIFMT_FORMAT_MASK) { |
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case SND_SOC_DAIFMT_I2S: |
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sscr0 |= SSCR0_PSP; |
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sscr1 |= SSCR1_RWOT | SSCR1_TRAIL; |
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/* See hw_params() */ |
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break; |
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|
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case SND_SOC_DAIFMT_DSP_A: |
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sspsp |= SSPSP_FSRT; |
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fallthrough; |
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case SND_SOC_DAIFMT_DSP_B: |
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sscr0 |= SSCR0_MOD | SSCR0_PSP; |
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sscr1 |= SSCR1_TRAIL | SSCR1_RWOT; |
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break; |
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|
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default: |
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return -EINVAL; |
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} |
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|
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pxa_ssp_write_reg(ssp, SSCR0, sscr0); |
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pxa_ssp_write_reg(ssp, SSCR1, sscr1); |
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pxa_ssp_write_reg(ssp, SSPSP, sspsp); |
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|
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switch (priv->dai_fmt & SND_SOC_DAIFMT_MASTER_MASK) { |
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case SND_SOC_DAIFMT_CBM_CFM: |
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case SND_SOC_DAIFMT_CBM_CFS: |
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scfr = pxa_ssp_read_reg(ssp, SSCR1) | SSCR1_SCFR; |
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pxa_ssp_write_reg(ssp, SSCR1, scfr); |
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|
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while (pxa_ssp_read_reg(ssp, SSSR) & SSSR_BSY) |
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cpu_relax(); |
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break; |
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} |
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|
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dump_registers(ssp); |
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|
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/* Since we are configuring the timings for the format by hand |
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* we have to defer some things until hw_params() where we |
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* know parameters like the sample size. |
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*/ |
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priv->configured_dai_fmt = priv->dai_fmt; |
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|
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return 0; |
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} |
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|
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struct pxa_ssp_clock_mode { |
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int rate; |
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int pll; |
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u8 acds; |
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u8 scdb; |
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}; |
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|
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static const struct pxa_ssp_clock_mode pxa_ssp_clock_modes[] = { |
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{ .rate = 8000, .pll = 32842000, .acds = SSACD_ACDS_32, .scdb = SSACD_SCDB_4X }, |
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{ .rate = 11025, .pll = 5622000, .acds = SSACD_ACDS_4, .scdb = SSACD_SCDB_4X }, |
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{ .rate = 16000, .pll = 32842000, .acds = SSACD_ACDS_16, .scdb = SSACD_SCDB_4X }, |
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{ .rate = 22050, .pll = 5622000, .acds = SSACD_ACDS_2, .scdb = SSACD_SCDB_4X }, |
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{ .rate = 44100, .pll = 11345000, .acds = SSACD_ACDS_2, .scdb = SSACD_SCDB_4X }, |
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{ .rate = 48000, .pll = 12235000, .acds = SSACD_ACDS_2, .scdb = SSACD_SCDB_4X }, |
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{ .rate = 96000, .pll = 12235000, .acds = SSACD_ACDS_4, .scdb = SSACD_SCDB_1X }, |
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{} |
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}; |
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|
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/* |
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* Set the SSP audio DMA parameters and sample size. |
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* Can be called multiple times by oss emulation. |
|
*/ |
|
static int pxa_ssp_hw_params(struct snd_pcm_substream *substream, |
|
struct snd_pcm_hw_params *params, |
|
struct snd_soc_dai *cpu_dai) |
|
{ |
|
struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai); |
|
struct ssp_device *ssp = priv->ssp; |
|
int chn = params_channels(params); |
|
u32 sscr0, sspsp; |
|
int width = snd_pcm_format_physical_width(params_format(params)); |
|
int ttsa = pxa_ssp_read_reg(ssp, SSTSA) & 0xf; |
|
struct snd_dmaengine_dai_dma_data *dma_data; |
|
int rate = params_rate(params); |
|
int bclk = rate * chn * (width / 8); |
|
int ret; |
|
|
|
dma_data = snd_soc_dai_get_dma_data(cpu_dai, substream); |
|
|
|
/* Network mode with one active slot (ttsa == 1) can be used |
|
* to force 16-bit frame width on the wire (for S16_LE), even |
|
* with two channels. Use 16-bit DMA transfers for this case. |
|
*/ |
|
pxa_ssp_set_dma_params(ssp, |
|
((chn == 2) && (ttsa != 1)) || (width == 32), |
|
substream->stream == SNDRV_PCM_STREAM_PLAYBACK, dma_data); |
|
|
|
/* we can only change the settings if the port is not in use */ |
|
if (pxa_ssp_read_reg(ssp, SSCR0) & SSCR0_SSE) |
|
return 0; |
|
|
|
ret = pxa_ssp_configure_dai_fmt(priv); |
|
if (ret < 0) |
|
return ret; |
|
|
|
/* clear selected SSP bits */ |
|
sscr0 = pxa_ssp_read_reg(ssp, SSCR0) & ~(SSCR0_DSS | SSCR0_EDSS); |
|
|
|
/* bit size */ |
|
switch (params_format(params)) { |
|
case SNDRV_PCM_FORMAT_S16_LE: |
|
if (ssp->type == PXA3xx_SSP) |
|
sscr0 |= SSCR0_FPCKE; |
|
sscr0 |= SSCR0_DataSize(16); |
|
break; |
|
case SNDRV_PCM_FORMAT_S24_LE: |
|
sscr0 |= (SSCR0_EDSS | SSCR0_DataSize(8)); |
|
break; |
|
case SNDRV_PCM_FORMAT_S32_LE: |
|
sscr0 |= (SSCR0_EDSS | SSCR0_DataSize(16)); |
|
break; |
|
} |
|
pxa_ssp_write_reg(ssp, SSCR0, sscr0); |
|
|
|
if (sscr0 & SSCR0_ACS) { |
|
ret = pxa_ssp_set_pll(priv, bclk); |
|
|
|
/* |
|
* If we were able to generate the bclk directly, |
|
* all is fine. Otherwise, look up the closest rate |
|
* from the table and also set the dividers. |
|
*/ |
|
|
|
if (ret < 0) { |
|
const struct pxa_ssp_clock_mode *m; |
|
int ssacd, acds; |
|
|
|
for (m = pxa_ssp_clock_modes; m->rate; m++) { |
|
if (m->rate == rate) |
|
break; |
|
} |
|
|
|
if (!m->rate) |
|
return -EINVAL; |
|
|
|
acds = m->acds; |
|
|
|
/* The values in the table are for 16 bits */ |
|
if (width == 32) |
|
acds--; |
|
|
|
ret = pxa_ssp_set_pll(priv, bclk); |
|
if (ret < 0) |
|
return ret; |
|
|
|
ssacd = pxa_ssp_read_reg(ssp, SSACD); |
|
ssacd &= ~(SSACD_ACDS(7) | SSACD_SCDB_1X); |
|
ssacd |= SSACD_ACDS(m->acds); |
|
ssacd |= m->scdb; |
|
pxa_ssp_write_reg(ssp, SSACD, ssacd); |
|
} |
|
} else if (sscr0 & SSCR0_ECS) { |
|
/* |
|
* For setups with external clocking, the PLL and its diviers |
|
* are not active. Instead, the SCR bits in SSCR0 can be used |
|
* to divide the clock. |
|
*/ |
|
pxa_ssp_set_scr(ssp, bclk / rate); |
|
} |
|
|
|
switch (priv->dai_fmt & SND_SOC_DAIFMT_FORMAT_MASK) { |
|
case SND_SOC_DAIFMT_I2S: |
|
sspsp = pxa_ssp_read_reg(ssp, SSPSP); |
|
|
|
if (((priv->sysclk / bclk) == 64) && (width == 16)) { |
|
/* This is a special case where the bitclk is 64fs |
|
* and we're not dealing with 2*32 bits of audio |
|
* samples. |
|
* |
|
* The SSP values used for that are all found out by |
|
* trying and failing a lot; some of the registers |
|
* needed for that mode are only available on PXA3xx. |
|
*/ |
|
if (ssp->type != PXA3xx_SSP) |
|
return -EINVAL; |
|
|
|
sspsp |= SSPSP_SFRMWDTH(width * 2); |
|
sspsp |= SSPSP_SFRMDLY(width * 4); |
|
sspsp |= SSPSP_EDMYSTOP(3); |
|
sspsp |= SSPSP_DMYSTOP(3); |
|
sspsp |= SSPSP_DMYSTRT(1); |
|
} else { |
|
/* The frame width is the width the LRCLK is |
|
* asserted for; the delay is expressed in |
|
* half cycle units. We need the extra cycle |
|
* because the data starts clocking out one BCLK |
|
* after LRCLK changes polarity. |
|
*/ |
|
sspsp |= SSPSP_SFRMWDTH(width + 1); |
|
sspsp |= SSPSP_SFRMDLY((width + 1) * 2); |
|
sspsp |= SSPSP_DMYSTRT(1); |
|
} |
|
|
|
pxa_ssp_write_reg(ssp, SSPSP, sspsp); |
|
break; |
|
default: |
|
break; |
|
} |
|
|
|
/* When we use a network mode, we always require TDM slots |
|
* - complain loudly and fail if they've not been set up yet. |
|
*/ |
|
if ((sscr0 & SSCR0_MOD) && !ttsa) { |
|
dev_err(ssp->dev, "No TDM timeslot configured\n"); |
|
return -EINVAL; |
|
} |
|
|
|
dump_registers(ssp); |
|
|
|
return 0; |
|
} |
|
|
|
static void pxa_ssp_set_running_bit(struct snd_pcm_substream *substream, |
|
struct ssp_device *ssp, int value) |
|
{ |
|
uint32_t sscr0 = pxa_ssp_read_reg(ssp, SSCR0); |
|
uint32_t sscr1 = pxa_ssp_read_reg(ssp, SSCR1); |
|
uint32_t sspsp = pxa_ssp_read_reg(ssp, SSPSP); |
|
uint32_t sssr = pxa_ssp_read_reg(ssp, SSSR); |
|
|
|
if (value && (sscr0 & SSCR0_SSE)) |
|
pxa_ssp_write_reg(ssp, SSCR0, sscr0 & ~SSCR0_SSE); |
|
|
|
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { |
|
if (value) |
|
sscr1 |= SSCR1_TSRE; |
|
else |
|
sscr1 &= ~SSCR1_TSRE; |
|
} else { |
|
if (value) |
|
sscr1 |= SSCR1_RSRE; |
|
else |
|
sscr1 &= ~SSCR1_RSRE; |
|
} |
|
|
|
pxa_ssp_write_reg(ssp, SSCR1, sscr1); |
|
|
|
if (value) { |
|
pxa_ssp_write_reg(ssp, SSSR, sssr); |
|
pxa_ssp_write_reg(ssp, SSPSP, sspsp); |
|
pxa_ssp_write_reg(ssp, SSCR0, sscr0 | SSCR0_SSE); |
|
} |
|
} |
|
|
|
static int pxa_ssp_trigger(struct snd_pcm_substream *substream, int cmd, |
|
struct snd_soc_dai *cpu_dai) |
|
{ |
|
int ret = 0; |
|
struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai); |
|
struct ssp_device *ssp = priv->ssp; |
|
int val; |
|
|
|
switch (cmd) { |
|
case SNDRV_PCM_TRIGGER_RESUME: |
|
pxa_ssp_enable(ssp); |
|
break; |
|
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: |
|
pxa_ssp_set_running_bit(substream, ssp, 1); |
|
val = pxa_ssp_read_reg(ssp, SSSR); |
|
pxa_ssp_write_reg(ssp, SSSR, val); |
|
break; |
|
case SNDRV_PCM_TRIGGER_START: |
|
pxa_ssp_set_running_bit(substream, ssp, 1); |
|
break; |
|
case SNDRV_PCM_TRIGGER_STOP: |
|
pxa_ssp_set_running_bit(substream, ssp, 0); |
|
break; |
|
case SNDRV_PCM_TRIGGER_SUSPEND: |
|
pxa_ssp_disable(ssp); |
|
break; |
|
case SNDRV_PCM_TRIGGER_PAUSE_PUSH: |
|
pxa_ssp_set_running_bit(substream, ssp, 0); |
|
break; |
|
|
|
default: |
|
ret = -EINVAL; |
|
} |
|
|
|
dump_registers(ssp); |
|
|
|
return ret; |
|
} |
|
|
|
static int pxa_ssp_probe(struct snd_soc_dai *dai) |
|
{ |
|
struct device *dev = dai->dev; |
|
struct ssp_priv *priv; |
|
int ret; |
|
|
|
priv = kzalloc(sizeof(struct ssp_priv), GFP_KERNEL); |
|
if (!priv) |
|
return -ENOMEM; |
|
|
|
if (dev->of_node) { |
|
struct device_node *ssp_handle; |
|
|
|
ssp_handle = of_parse_phandle(dev->of_node, "port", 0); |
|
if (!ssp_handle) { |
|
dev_err(dev, "unable to get 'port' phandle\n"); |
|
ret = -ENODEV; |
|
goto err_priv; |
|
} |
|
|
|
priv->ssp = pxa_ssp_request_of(ssp_handle, "SoC audio"); |
|
if (priv->ssp == NULL) { |
|
ret = -ENODEV; |
|
goto err_priv; |
|
} |
|
|
|
priv->extclk = devm_clk_get(dev, "extclk"); |
|
if (IS_ERR(priv->extclk)) { |
|
ret = PTR_ERR(priv->extclk); |
|
if (ret == -EPROBE_DEFER) |
|
return ret; |
|
|
|
priv->extclk = NULL; |
|
} |
|
} else { |
|
priv->ssp = pxa_ssp_request(dai->id + 1, "SoC audio"); |
|
if (priv->ssp == NULL) { |
|
ret = -ENODEV; |
|
goto err_priv; |
|
} |
|
} |
|
|
|
priv->dai_fmt = (unsigned int) -1; |
|
snd_soc_dai_set_drvdata(dai, priv); |
|
|
|
return 0; |
|
|
|
err_priv: |
|
kfree(priv); |
|
return ret; |
|
} |
|
|
|
static int pxa_ssp_remove(struct snd_soc_dai *dai) |
|
{ |
|
struct ssp_priv *priv = snd_soc_dai_get_drvdata(dai); |
|
|
|
pxa_ssp_free(priv->ssp); |
|
kfree(priv); |
|
return 0; |
|
} |
|
|
|
#define PXA_SSP_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\ |
|
SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | \ |
|
SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \ |
|
SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_64000 | \ |
|
SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000) |
|
|
|
#define PXA_SSP_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE) |
|
|
|
static const struct snd_soc_dai_ops pxa_ssp_dai_ops = { |
|
.startup = pxa_ssp_startup, |
|
.shutdown = pxa_ssp_shutdown, |
|
.trigger = pxa_ssp_trigger, |
|
.hw_params = pxa_ssp_hw_params, |
|
.set_sysclk = pxa_ssp_set_dai_sysclk, |
|
.set_fmt = pxa_ssp_set_dai_fmt, |
|
.set_tdm_slot = pxa_ssp_set_dai_tdm_slot, |
|
.set_tristate = pxa_ssp_set_dai_tristate, |
|
}; |
|
|
|
static struct snd_soc_dai_driver pxa_ssp_dai = { |
|
.probe = pxa_ssp_probe, |
|
.remove = pxa_ssp_remove, |
|
.playback = { |
|
.channels_min = 1, |
|
.channels_max = 8, |
|
.rates = PXA_SSP_RATES, |
|
.formats = PXA_SSP_FORMATS, |
|
}, |
|
.capture = { |
|
.channels_min = 1, |
|
.channels_max = 8, |
|
.rates = PXA_SSP_RATES, |
|
.formats = PXA_SSP_FORMATS, |
|
}, |
|
.ops = &pxa_ssp_dai_ops, |
|
}; |
|
|
|
static const struct snd_soc_component_driver pxa_ssp_component = { |
|
.name = "pxa-ssp", |
|
.pcm_construct = pxa2xx_soc_pcm_new, |
|
.open = pxa2xx_soc_pcm_open, |
|
.close = pxa2xx_soc_pcm_close, |
|
.hw_params = pxa2xx_soc_pcm_hw_params, |
|
.prepare = pxa2xx_soc_pcm_prepare, |
|
.trigger = pxa2xx_soc_pcm_trigger, |
|
.pointer = pxa2xx_soc_pcm_pointer, |
|
.suspend = pxa_ssp_suspend, |
|
.resume = pxa_ssp_resume, |
|
}; |
|
|
|
#ifdef CONFIG_OF |
|
static const struct of_device_id pxa_ssp_of_ids[] = { |
|
{ .compatible = "mrvl,pxa-ssp-dai" }, |
|
{} |
|
}; |
|
MODULE_DEVICE_TABLE(of, pxa_ssp_of_ids); |
|
#endif |
|
|
|
static int asoc_ssp_probe(struct platform_device *pdev) |
|
{ |
|
return devm_snd_soc_register_component(&pdev->dev, &pxa_ssp_component, |
|
&pxa_ssp_dai, 1); |
|
} |
|
|
|
static struct platform_driver asoc_ssp_driver = { |
|
.driver = { |
|
.name = "pxa-ssp-dai", |
|
.of_match_table = of_match_ptr(pxa_ssp_of_ids), |
|
}, |
|
|
|
.probe = asoc_ssp_probe, |
|
}; |
|
|
|
module_platform_driver(asoc_ssp_driver); |
|
|
|
/* Module information */ |
|
MODULE_AUTHOR("Mark Brown <[email protected]>"); |
|
MODULE_DESCRIPTION("PXA SSP/PCM SoC Interface"); |
|
MODULE_LICENSE("GPL"); |
|
MODULE_ALIAS("platform:pxa-ssp-dai");
|
|
|