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103 lines
4.1 KiB
103 lines
4.1 KiB
/* SPDX-License-Identifier: GPL-2.0 */ |
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/* |
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* NXP AUDMIX ALSA SoC Digital Audio Interface (DAI) driver |
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* |
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* Copyright 2017 NXP |
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*/ |
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#ifndef __FSL_AUDMIX_H |
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#define __FSL_AUDMIX_H |
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#define FSL_AUDMIX_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ |
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SNDRV_PCM_FMTBIT_S24_LE |\ |
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SNDRV_PCM_FMTBIT_S32_LE) |
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/* AUDMIX Registers */ |
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#define FSL_AUDMIX_CTR 0x200 /* Control */ |
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#define FSL_AUDMIX_STR 0x204 /* Status */ |
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#define FSL_AUDMIX_ATCR0 0x208 /* Attenuation Control */ |
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#define FSL_AUDMIX_ATIVAL0 0x20c /* Attenuation Initial Value */ |
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#define FSL_AUDMIX_ATSTPUP0 0x210 /* Attenuation step up factor */ |
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#define FSL_AUDMIX_ATSTPDN0 0x214 /* Attenuation step down factor */ |
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#define FSL_AUDMIX_ATSTPTGT0 0x218 /* Attenuation step target */ |
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#define FSL_AUDMIX_ATTNVAL0 0x21c /* Attenuation Value */ |
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#define FSL_AUDMIX_ATSTP0 0x220 /* Attenuation step number */ |
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#define FSL_AUDMIX_ATCR1 0x228 /* Attenuation Control */ |
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#define FSL_AUDMIX_ATIVAL1 0x22c /* Attenuation Initial Value */ |
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#define FSL_AUDMIX_ATSTPUP1 0x230 /* Attenuation step up factor */ |
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#define FSL_AUDMIX_ATSTPDN1 0x234 /* Attenuation step down factor */ |
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#define FSL_AUDMIX_ATSTPTGT1 0x238 /* Attenuation step target */ |
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#define FSL_AUDMIX_ATTNVAL1 0x23c /* Attenuation Value */ |
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#define FSL_AUDMIX_ATSTP1 0x240 /* Attenuation step number */ |
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/* AUDMIX Control Register */ |
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#define FSL_AUDMIX_CTR_MIXCLK_SHIFT 0 |
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#define FSL_AUDMIX_CTR_MIXCLK_MASK BIT(FSL_AUDMIX_CTR_MIXCLK_SHIFT) |
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#define FSL_AUDMIX_CTR_MIXCLK(i) ((i) << FSL_AUDMIX_CTR_MIXCLK_SHIFT) |
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#define FSL_AUDMIX_CTR_OUTSRC_SHIFT 1 |
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#define FSL_AUDMIX_CTR_OUTSRC_MASK (0x3 << FSL_AUDMIX_CTR_OUTSRC_SHIFT) |
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#define FSL_AUDMIX_CTR_OUTSRC(i) (((i) << FSL_AUDMIX_CTR_OUTSRC_SHIFT)\ |
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& FSL_AUDMIX_CTR_OUTSRC_MASK) |
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#define FSL_AUDMIX_CTR_OUTWIDTH_SHIFT 3 |
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#define FSL_AUDMIX_CTR_OUTWIDTH_MASK (0x7 << FSL_AUDMIX_CTR_OUTWIDTH_SHIFT) |
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#define FSL_AUDMIX_CTR_OUTWIDTH(i) (((i) << FSL_AUDMIX_CTR_OUTWIDTH_SHIFT)\ |
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& FSL_AUDMIX_CTR_OUTWIDTH_MASK) |
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#define FSL_AUDMIX_CTR_OUTCKPOL_SHIFT 6 |
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#define FSL_AUDMIX_CTR_OUTCKPOL_MASK BIT(FSL_AUDMIX_CTR_OUTCKPOL_SHIFT) |
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#define FSL_AUDMIX_CTR_OUTCKPOL(i) ((i) << FSL_AUDMIX_CTR_OUTCKPOL_SHIFT) |
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#define FSL_AUDMIX_CTR_MASKRTDF_SHIFT 7 |
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#define FSL_AUDMIX_CTR_MASKRTDF_MASK BIT(FSL_AUDMIX_CTR_MASKRTDF_SHIFT) |
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#define FSL_AUDMIX_CTR_MASKRTDF(i) ((i) << FSL_AUDMIX_CTR_MASKRTDF_SHIFT) |
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#define FSL_AUDMIX_CTR_MASKCKDF_SHIFT 8 |
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#define FSL_AUDMIX_CTR_MASKCKDF_MASK BIT(FSL_AUDMIX_CTR_MASKCKDF_SHIFT) |
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#define FSL_AUDMIX_CTR_MASKCKDF(i) ((i) << FSL_AUDMIX_CTR_MASKCKDF_SHIFT) |
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#define FSL_AUDMIX_CTR_SYNCMODE_SHIFT 9 |
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#define FSL_AUDMIX_CTR_SYNCMODE_MASK BIT(FSL_AUDMIX_CTR_SYNCMODE_SHIFT) |
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#define FSL_AUDMIX_CTR_SYNCMODE(i) ((i) << FSL_AUDMIX_CTR_SYNCMODE_SHIFT) |
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#define FSL_AUDMIX_CTR_SYNCSRC_SHIFT 10 |
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#define FSL_AUDMIX_CTR_SYNCSRC_MASK BIT(FSL_AUDMIX_CTR_SYNCSRC_SHIFT) |
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#define FSL_AUDMIX_CTR_SYNCSRC(i) ((i) << FSL_AUDMIX_CTR_SYNCSRC_SHIFT) |
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/* AUDMIX Status Register */ |
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#define FSL_AUDMIX_STR_RATEDIFF BIT(0) |
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#define FSL_AUDMIX_STR_CLKDIFF BIT(1) |
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#define FSL_AUDMIX_STR_MIXSTAT_SHIFT 2 |
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#define FSL_AUDMIX_STR_MIXSTAT_MASK (0x3 << FSL_AUDMIX_STR_MIXSTAT_SHIFT) |
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#define FSL_AUDMIX_STR_MIXSTAT(i) (((i) & FSL_AUDMIX_STR_MIXSTAT_MASK) \ |
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>> FSL_AUDMIX_STR_MIXSTAT_SHIFT) |
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/* AUDMIX Attenuation Control Register */ |
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#define FSL_AUDMIX_ATCR_AT_EN BIT(0) |
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#define FSL_AUDMIX_ATCR_AT_UPDN BIT(1) |
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#define FSL_AUDMIX_ATCR_ATSTPDIF_SHIFT 2 |
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#define FSL_AUDMIX_ATCR_ATSTPDFI_MASK \ |
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(0xfff << FSL_AUDMIX_ATCR_ATSTPDIF_SHIFT) |
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/* AUDMIX Attenuation Initial Value Register */ |
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#define FSL_AUDMIX_ATIVAL_ATINVAL_MASK 0x3FFFF |
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/* AUDMIX Attenuation Step Up Factor Register */ |
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#define FSL_AUDMIX_ATSTPUP_ATSTEPUP_MASK 0x3FFFF |
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/* AUDMIX Attenuation Step Down Factor Register */ |
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#define FSL_AUDMIX_ATSTPDN_ATSTEPDN_MASK 0x3FFFF |
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/* AUDMIX Attenuation Step Target Register */ |
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#define FSL_AUDMIX_ATSTPTGT_ATSTPTG_MASK 0x3FFFF |
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/* AUDMIX Attenuation Value Register */ |
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#define FSL_AUDMIX_ATTNVAL_ATCURVAL_MASK 0x3FFFF |
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/* AUDMIX Attenuation Step Number Register */ |
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#define FSL_AUDMIX_ATSTP_STPCTR_MASK 0x3FFFF |
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#define FSL_AUDMIX_MAX_DAIS 2 |
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struct fsl_audmix { |
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struct platform_device *pdev; |
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struct regmap *regmap; |
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struct clk *ipg_clk; |
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spinlock_t lock; /* Protect tdms */ |
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u8 tdms; |
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}; |
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#endif /* __FSL_AUDMIX_H */
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