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924 lines
23 KiB
924 lines
23 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* atmel_ssc_dai.c -- ALSA SoC ATMEL SSC Audio Layer Platform driver |
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* |
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* Copyright (C) 2005 SAN People |
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* Copyright (C) 2008 Atmel |
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* |
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* Author: Sedji Gaouaou <[email protected]> |
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* ATMEL CORP. |
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* |
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* Based on at91-ssc.c by |
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* Frank Mandarino <[email protected]> |
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* Based on pxa2xx Platform drivers by |
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* Liam Girdwood <[email protected]> |
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*/ |
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|
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#include <linux/init.h> |
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#include <linux/module.h> |
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#include <linux/interrupt.h> |
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#include <linux/device.h> |
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#include <linux/delay.h> |
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#include <linux/clk.h> |
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#include <linux/atmel_pdc.h> |
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#include <linux/atmel-ssc.h> |
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#include <sound/core.h> |
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#include <sound/pcm.h> |
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#include <sound/pcm_params.h> |
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#include <sound/initval.h> |
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#include <sound/soc.h> |
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#include "atmel-pcm.h" |
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#include "atmel_ssc_dai.h" |
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#define NUM_SSC_DEVICES 3 |
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|
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/* |
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* SSC PDC registers required by the PCM DMA engine. |
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*/ |
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static struct atmel_pdc_regs pdc_tx_reg = { |
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.xpr = ATMEL_PDC_TPR, |
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.xcr = ATMEL_PDC_TCR, |
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.xnpr = ATMEL_PDC_TNPR, |
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.xncr = ATMEL_PDC_TNCR, |
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}; |
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static struct atmel_pdc_regs pdc_rx_reg = { |
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.xpr = ATMEL_PDC_RPR, |
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.xcr = ATMEL_PDC_RCR, |
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.xnpr = ATMEL_PDC_RNPR, |
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.xncr = ATMEL_PDC_RNCR, |
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}; |
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|
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/* |
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* SSC & PDC status bits for transmit and receive. |
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*/ |
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static struct atmel_ssc_mask ssc_tx_mask = { |
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.ssc_enable = SSC_BIT(CR_TXEN), |
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.ssc_disable = SSC_BIT(CR_TXDIS), |
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.ssc_endx = SSC_BIT(SR_ENDTX), |
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.ssc_endbuf = SSC_BIT(SR_TXBUFE), |
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.ssc_error = SSC_BIT(SR_OVRUN), |
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.pdc_enable = ATMEL_PDC_TXTEN, |
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.pdc_disable = ATMEL_PDC_TXTDIS, |
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}; |
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static struct atmel_ssc_mask ssc_rx_mask = { |
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.ssc_enable = SSC_BIT(CR_RXEN), |
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.ssc_disable = SSC_BIT(CR_RXDIS), |
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.ssc_endx = SSC_BIT(SR_ENDRX), |
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.ssc_endbuf = SSC_BIT(SR_RXBUFF), |
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.ssc_error = SSC_BIT(SR_OVRUN), |
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.pdc_enable = ATMEL_PDC_RXTEN, |
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.pdc_disable = ATMEL_PDC_RXTDIS, |
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}; |
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/* |
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* DMA parameters. |
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*/ |
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static struct atmel_pcm_dma_params ssc_dma_params[NUM_SSC_DEVICES][2] = { |
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{{ |
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.name = "SSC0 PCM out", |
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.pdc = &pdc_tx_reg, |
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.mask = &ssc_tx_mask, |
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}, |
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{ |
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.name = "SSC0 PCM in", |
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.pdc = &pdc_rx_reg, |
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.mask = &ssc_rx_mask, |
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} }, |
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{{ |
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.name = "SSC1 PCM out", |
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.pdc = &pdc_tx_reg, |
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.mask = &ssc_tx_mask, |
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}, |
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{ |
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.name = "SSC1 PCM in", |
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.pdc = &pdc_rx_reg, |
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.mask = &ssc_rx_mask, |
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} }, |
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{{ |
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.name = "SSC2 PCM out", |
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.pdc = &pdc_tx_reg, |
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.mask = &ssc_tx_mask, |
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}, |
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{ |
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.name = "SSC2 PCM in", |
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.pdc = &pdc_rx_reg, |
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.mask = &ssc_rx_mask, |
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} }, |
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}; |
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static struct atmel_ssc_info ssc_info[NUM_SSC_DEVICES] = { |
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{ |
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.name = "ssc0", |
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.dir_mask = SSC_DIR_MASK_UNUSED, |
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.initialized = 0, |
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}, |
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{ |
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.name = "ssc1", |
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.dir_mask = SSC_DIR_MASK_UNUSED, |
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.initialized = 0, |
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}, |
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{ |
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.name = "ssc2", |
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.dir_mask = SSC_DIR_MASK_UNUSED, |
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.initialized = 0, |
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}, |
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}; |
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/* |
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* SSC interrupt handler. Passes PDC interrupts to the DMA |
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* interrupt handler in the PCM driver. |
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*/ |
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static irqreturn_t atmel_ssc_interrupt(int irq, void *dev_id) |
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{ |
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struct atmel_ssc_info *ssc_p = dev_id; |
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struct atmel_pcm_dma_params *dma_params; |
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u32 ssc_sr; |
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u32 ssc_substream_mask; |
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int i; |
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ssc_sr = (unsigned long)ssc_readl(ssc_p->ssc->regs, SR) |
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& (unsigned long)ssc_readl(ssc_p->ssc->regs, IMR); |
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/* |
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* Loop through the substreams attached to this SSC. If |
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* a DMA-related interrupt occurred on that substream, call |
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* the DMA interrupt handler function, if one has been |
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* registered in the dma_params structure by the PCM driver. |
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*/ |
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for (i = 0; i < ARRAY_SIZE(ssc_p->dma_params); i++) { |
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dma_params = ssc_p->dma_params[i]; |
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if ((dma_params != NULL) && |
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(dma_params->dma_intr_handler != NULL)) { |
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ssc_substream_mask = (dma_params->mask->ssc_endx | |
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dma_params->mask->ssc_endbuf); |
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if (ssc_sr & ssc_substream_mask) { |
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dma_params->dma_intr_handler(ssc_sr, |
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dma_params-> |
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substream); |
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} |
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} |
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} |
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return IRQ_HANDLED; |
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} |
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/* |
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* When the bit clock is input, limit the maximum rate according to the |
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* Serial Clock Ratio Considerations section from the SSC documentation: |
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* |
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* The Transmitter and the Receiver can be programmed to operate |
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* with the clock signals provided on either the TK or RK pins. |
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* This allows the SSC to support many slave-mode data transfers. |
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* In this case, the maximum clock speed allowed on the RK pin is: |
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* - Peripheral clock divided by 2 if Receiver Frame Synchro is input |
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* - Peripheral clock divided by 3 if Receiver Frame Synchro is output |
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* In addition, the maximum clock speed allowed on the TK pin is: |
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* - Peripheral clock divided by 6 if Transmit Frame Synchro is input |
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* - Peripheral clock divided by 2 if Transmit Frame Synchro is output |
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* |
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* When the bit clock is output, limit the rate according to the |
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* SSC divider restrictions. |
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*/ |
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static int atmel_ssc_hw_rule_rate(struct snd_pcm_hw_params *params, |
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struct snd_pcm_hw_rule *rule) |
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{ |
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struct atmel_ssc_info *ssc_p = rule->private; |
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struct ssc_device *ssc = ssc_p->ssc; |
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struct snd_interval *i = hw_param_interval(params, rule->var); |
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struct snd_interval t; |
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struct snd_ratnum r = { |
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.den_min = 1, |
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.den_max = 4095, |
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.den_step = 1, |
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}; |
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unsigned int num = 0, den = 0; |
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int frame_size; |
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int mck_div = 2; |
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int ret; |
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frame_size = snd_soc_params_to_frame_size(params); |
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if (frame_size < 0) |
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return frame_size; |
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switch (ssc_p->daifmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { |
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case SND_SOC_DAIFMT_CBP_CFC: |
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if ((ssc_p->dir_mask & SSC_DIR_MASK_CAPTURE) |
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&& ssc->clk_from_rk_pin) |
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/* Receiver Frame Synchro (i.e. capture) |
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* is output (format is _CFS) and the RK pin |
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* is used for input (format is _CBM_). |
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*/ |
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mck_div = 3; |
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break; |
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case SND_SOC_DAIFMT_CBP_CFP: |
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if ((ssc_p->dir_mask & SSC_DIR_MASK_PLAYBACK) |
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&& !ssc->clk_from_rk_pin) |
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/* Transmit Frame Synchro (i.e. playback) |
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* is input (format is _CFM) and the TK pin |
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* is used for input (format _CBM_ but not |
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* using the RK pin). |
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*/ |
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mck_div = 6; |
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break; |
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} |
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switch (ssc_p->daifmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { |
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case SND_SOC_DAIFMT_CBC_CFC: |
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r.num = ssc_p->mck_rate / mck_div / frame_size; |
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ret = snd_interval_ratnum(i, 1, &r, &num, &den); |
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if (ret >= 0 && den && rule->var == SNDRV_PCM_HW_PARAM_RATE) { |
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params->rate_num = num; |
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params->rate_den = den; |
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} |
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break; |
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case SND_SOC_DAIFMT_CBP_CFC: |
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case SND_SOC_DAIFMT_CBP_CFP: |
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t.min = 8000; |
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t.max = ssc_p->mck_rate / mck_div / frame_size; |
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t.openmin = t.openmax = 0; |
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t.integer = 0; |
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ret = snd_interval_refine(i, &t); |
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break; |
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default: |
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ret = -EINVAL; |
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break; |
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} |
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return ret; |
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} |
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|
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/*-------------------------------------------------------------------------*\ |
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* DAI functions |
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\*-------------------------------------------------------------------------*/ |
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/* |
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* Startup. Only that one substream allowed in each direction. |
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*/ |
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static int atmel_ssc_startup(struct snd_pcm_substream *substream, |
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struct snd_soc_dai *dai) |
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{ |
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struct platform_device *pdev = to_platform_device(dai->dev); |
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struct atmel_ssc_info *ssc_p = &ssc_info[pdev->id]; |
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struct atmel_pcm_dma_params *dma_params; |
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int dir, dir_mask; |
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int ret; |
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pr_debug("atmel_ssc_startup: SSC_SR=0x%x\n", |
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ssc_readl(ssc_p->ssc->regs, SR)); |
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/* Enable PMC peripheral clock for this SSC */ |
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pr_debug("atmel_ssc_dai: Starting clock\n"); |
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clk_enable(ssc_p->ssc->clk); |
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ssc_p->mck_rate = clk_get_rate(ssc_p->ssc->clk); |
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/* Reset the SSC unless initialized to keep it in a clean state */ |
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if (!ssc_p->initialized) |
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ssc_writel(ssc_p->ssc->regs, CR, SSC_BIT(CR_SWRST)); |
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { |
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dir = 0; |
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dir_mask = SSC_DIR_MASK_PLAYBACK; |
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} else { |
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dir = 1; |
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dir_mask = SSC_DIR_MASK_CAPTURE; |
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} |
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ret = snd_pcm_hw_rule_add(substream->runtime, 0, |
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SNDRV_PCM_HW_PARAM_RATE, |
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atmel_ssc_hw_rule_rate, |
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ssc_p, |
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SNDRV_PCM_HW_PARAM_FRAME_BITS, |
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SNDRV_PCM_HW_PARAM_CHANNELS, -1); |
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if (ret < 0) { |
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dev_err(dai->dev, "Failed to specify rate rule: %d\n", ret); |
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return ret; |
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} |
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dma_params = &ssc_dma_params[pdev->id][dir]; |
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dma_params->ssc = ssc_p->ssc; |
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dma_params->substream = substream; |
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ssc_p->dma_params[dir] = dma_params; |
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snd_soc_dai_set_dma_data(dai, substream, dma_params); |
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if (ssc_p->dir_mask & dir_mask) |
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return -EBUSY; |
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ssc_p->dir_mask |= dir_mask; |
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return 0; |
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} |
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/* |
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* Shutdown. Clear DMA parameters and shutdown the SSC if there |
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* are no other substreams open. |
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*/ |
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static void atmel_ssc_shutdown(struct snd_pcm_substream *substream, |
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struct snd_soc_dai *dai) |
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{ |
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struct platform_device *pdev = to_platform_device(dai->dev); |
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struct atmel_ssc_info *ssc_p = &ssc_info[pdev->id]; |
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struct atmel_pcm_dma_params *dma_params; |
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int dir, dir_mask; |
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) |
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dir = 0; |
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else |
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dir = 1; |
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dma_params = ssc_p->dma_params[dir]; |
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if (dma_params != NULL) { |
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dma_params->ssc = NULL; |
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dma_params->substream = NULL; |
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ssc_p->dma_params[dir] = NULL; |
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} |
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dir_mask = 1 << dir; |
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ssc_p->dir_mask &= ~dir_mask; |
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if (!ssc_p->dir_mask) { |
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if (ssc_p->initialized) { |
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free_irq(ssc_p->ssc->irq, ssc_p); |
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ssc_p->initialized = 0; |
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} |
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/* Reset the SSC */ |
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ssc_writel(ssc_p->ssc->regs, CR, SSC_BIT(CR_SWRST)); |
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/* Clear the SSC dividers */ |
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ssc_p->cmr_div = ssc_p->tcmr_period = ssc_p->rcmr_period = 0; |
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ssc_p->forced_divider = 0; |
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} |
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|
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/* Shutdown the SSC clock. */ |
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pr_debug("atmel_ssc_dai: Stopping clock\n"); |
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clk_disable(ssc_p->ssc->clk); |
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} |
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/* |
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* Record the DAI format for use in hw_params(). |
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*/ |
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static int atmel_ssc_set_dai_fmt(struct snd_soc_dai *cpu_dai, |
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unsigned int fmt) |
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{ |
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struct platform_device *pdev = to_platform_device(cpu_dai->dev); |
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struct atmel_ssc_info *ssc_p = &ssc_info[pdev->id]; |
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ssc_p->daifmt = fmt; |
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return 0; |
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} |
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/* |
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* Record SSC clock dividers for use in hw_params(). |
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*/ |
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static int atmel_ssc_set_dai_clkdiv(struct snd_soc_dai *cpu_dai, |
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int div_id, int div) |
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{ |
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struct platform_device *pdev = to_platform_device(cpu_dai->dev); |
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struct atmel_ssc_info *ssc_p = &ssc_info[pdev->id]; |
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switch (div_id) { |
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case ATMEL_SSC_CMR_DIV: |
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/* |
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* The same master clock divider is used for both |
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* transmit and receive, so if a value has already |
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* been set, it must match this value. |
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*/ |
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if (ssc_p->dir_mask != |
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(SSC_DIR_MASK_PLAYBACK | SSC_DIR_MASK_CAPTURE)) |
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ssc_p->cmr_div = div; |
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else if (ssc_p->cmr_div == 0) |
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ssc_p->cmr_div = div; |
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else |
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if (div != ssc_p->cmr_div) |
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return -EBUSY; |
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ssc_p->forced_divider |= BIT(ATMEL_SSC_CMR_DIV); |
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break; |
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case ATMEL_SSC_TCMR_PERIOD: |
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ssc_p->tcmr_period = div; |
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ssc_p->forced_divider |= BIT(ATMEL_SSC_TCMR_PERIOD); |
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break; |
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case ATMEL_SSC_RCMR_PERIOD: |
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ssc_p->rcmr_period = div; |
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ssc_p->forced_divider |= BIT(ATMEL_SSC_RCMR_PERIOD); |
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break; |
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default: |
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return -EINVAL; |
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} |
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return 0; |
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} |
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|
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/* Is the cpu-dai master of the frame clock? */ |
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static int atmel_ssc_cfs(struct atmel_ssc_info *ssc_p) |
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{ |
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switch (ssc_p->daifmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { |
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case SND_SOC_DAIFMT_CBP_CFC: |
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case SND_SOC_DAIFMT_CBC_CFC: |
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return 1; |
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} |
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return 0; |
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} |
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|
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/* Is the cpu-dai master of the bit clock? */ |
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static int atmel_ssc_cbs(struct atmel_ssc_info *ssc_p) |
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{ |
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switch (ssc_p->daifmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { |
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case SND_SOC_DAIFMT_CBC_CFP: |
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case SND_SOC_DAIFMT_CBC_CFC: |
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return 1; |
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} |
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return 0; |
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} |
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|
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/* |
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* Configure the SSC. |
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*/ |
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static int atmel_ssc_hw_params(struct snd_pcm_substream *substream, |
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struct snd_pcm_hw_params *params, |
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struct snd_soc_dai *dai) |
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{ |
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struct platform_device *pdev = to_platform_device(dai->dev); |
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int id = pdev->id; |
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struct atmel_ssc_info *ssc_p = &ssc_info[id]; |
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struct ssc_device *ssc = ssc_p->ssc; |
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struct atmel_pcm_dma_params *dma_params; |
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int dir, channels, bits; |
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u32 tfmr, rfmr, tcmr, rcmr; |
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int ret; |
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int fslen, fslen_ext, fs_osync, fs_edge; |
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u32 cmr_div; |
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u32 tcmr_period; |
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u32 rcmr_period; |
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|
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/* |
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* Currently, there is only one set of dma params for |
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* each direction. If more are added, this code will |
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* have to be changed to select the proper set. |
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*/ |
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) |
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dir = 0; |
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else |
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dir = 1; |
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|
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/* |
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* If the cpu dai should provide BCLK, but noone has provided the |
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* divider needed for that to work, fall back to something sensible. |
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*/ |
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cmr_div = ssc_p->cmr_div; |
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if (!(ssc_p->forced_divider & BIT(ATMEL_SSC_CMR_DIV)) && |
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atmel_ssc_cbs(ssc_p)) { |
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int bclk_rate = snd_soc_params_to_bclk(params); |
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|
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if (bclk_rate < 0) { |
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dev_err(dai->dev, "unable to calculate cmr_div: %d\n", |
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bclk_rate); |
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return bclk_rate; |
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} |
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|
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cmr_div = DIV_ROUND_CLOSEST(ssc_p->mck_rate, 2 * bclk_rate); |
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} |
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|
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/* |
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* If the cpu dai should provide LRCLK, but noone has provided the |
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* dividers needed for that to work, fall back to something sensible. |
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*/ |
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tcmr_period = ssc_p->tcmr_period; |
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rcmr_period = ssc_p->rcmr_period; |
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if (atmel_ssc_cfs(ssc_p)) { |
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int frame_size = snd_soc_params_to_frame_size(params); |
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|
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if (frame_size < 0) { |
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dev_err(dai->dev, |
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"unable to calculate tx/rx cmr_period: %d\n", |
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frame_size); |
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return frame_size; |
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} |
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|
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if (!(ssc_p->forced_divider & BIT(ATMEL_SSC_TCMR_PERIOD))) |
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tcmr_period = frame_size / 2 - 1; |
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if (!(ssc_p->forced_divider & BIT(ATMEL_SSC_RCMR_PERIOD))) |
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rcmr_period = frame_size / 2 - 1; |
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} |
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|
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dma_params = ssc_p->dma_params[dir]; |
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|
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channels = params_channels(params); |
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|
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/* |
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* Determine sample size in bits and the PDC increment. |
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*/ |
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switch (params_format(params)) { |
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case SNDRV_PCM_FORMAT_S8: |
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bits = 8; |
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dma_params->pdc_xfer_size = 1; |
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break; |
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case SNDRV_PCM_FORMAT_S16_LE: |
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bits = 16; |
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dma_params->pdc_xfer_size = 2; |
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break; |
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case SNDRV_PCM_FORMAT_S24_LE: |
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bits = 24; |
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dma_params->pdc_xfer_size = 4; |
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break; |
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case SNDRV_PCM_FORMAT_S32_LE: |
|
bits = 32; |
|
dma_params->pdc_xfer_size = 4; |
|
break; |
|
default: |
|
printk(KERN_WARNING "atmel_ssc_dai: unsupported PCM format"); |
|
return -EINVAL; |
|
} |
|
|
|
/* |
|
* Compute SSC register settings. |
|
*/ |
|
|
|
fslen_ext = (bits - 1) / 16; |
|
fslen = (bits - 1) % 16; |
|
|
|
switch (ssc_p->daifmt & SND_SOC_DAIFMT_FORMAT_MASK) { |
|
|
|
case SND_SOC_DAIFMT_LEFT_J: |
|
fs_osync = SSC_FSOS_POSITIVE; |
|
fs_edge = SSC_START_RISING_RF; |
|
|
|
rcmr = SSC_BF(RCMR_STTDLY, 0); |
|
tcmr = SSC_BF(TCMR_STTDLY, 0); |
|
|
|
break; |
|
|
|
case SND_SOC_DAIFMT_I2S: |
|
fs_osync = SSC_FSOS_NEGATIVE; |
|
fs_edge = SSC_START_FALLING_RF; |
|
|
|
rcmr = SSC_BF(RCMR_STTDLY, 1); |
|
tcmr = SSC_BF(TCMR_STTDLY, 1); |
|
|
|
break; |
|
|
|
case SND_SOC_DAIFMT_DSP_A: |
|
/* |
|
* DSP/PCM Mode A format |
|
* |
|
* Data is transferred on first BCLK after LRC pulse rising |
|
* edge.If stereo, the right channel data is contiguous with |
|
* the left channel data. |
|
*/ |
|
fs_osync = SSC_FSOS_POSITIVE; |
|
fs_edge = SSC_START_RISING_RF; |
|
fslen = fslen_ext = 0; |
|
|
|
rcmr = SSC_BF(RCMR_STTDLY, 1); |
|
tcmr = SSC_BF(TCMR_STTDLY, 1); |
|
|
|
break; |
|
|
|
default: |
|
printk(KERN_WARNING "atmel_ssc_dai: unsupported DAI format 0x%x\n", |
|
ssc_p->daifmt); |
|
return -EINVAL; |
|
} |
|
|
|
if (!atmel_ssc_cfs(ssc_p)) { |
|
fslen = fslen_ext = 0; |
|
rcmr_period = tcmr_period = 0; |
|
fs_osync = SSC_FSOS_NONE; |
|
} |
|
|
|
rcmr |= SSC_BF(RCMR_START, fs_edge); |
|
tcmr |= SSC_BF(TCMR_START, fs_edge); |
|
|
|
if (atmel_ssc_cbs(ssc_p)) { |
|
/* |
|
* SSC provides BCLK |
|
* |
|
* The SSC transmit and receive clocks are generated from the |
|
* MCK divider, and the BCLK signal is output |
|
* on the SSC TK line. |
|
*/ |
|
rcmr |= SSC_BF(RCMR_CKS, SSC_CKS_DIV) |
|
| SSC_BF(RCMR_CKO, SSC_CKO_NONE); |
|
|
|
tcmr |= SSC_BF(TCMR_CKS, SSC_CKS_DIV) |
|
| SSC_BF(TCMR_CKO, SSC_CKO_CONTINUOUS); |
|
} else { |
|
rcmr |= SSC_BF(RCMR_CKS, ssc->clk_from_rk_pin ? |
|
SSC_CKS_PIN : SSC_CKS_CLOCK) |
|
| SSC_BF(RCMR_CKO, SSC_CKO_NONE); |
|
|
|
tcmr |= SSC_BF(TCMR_CKS, ssc->clk_from_rk_pin ? |
|
SSC_CKS_CLOCK : SSC_CKS_PIN) |
|
| SSC_BF(TCMR_CKO, SSC_CKO_NONE); |
|
} |
|
|
|
rcmr |= SSC_BF(RCMR_PERIOD, rcmr_period) |
|
| SSC_BF(RCMR_CKI, SSC_CKI_RISING); |
|
|
|
tcmr |= SSC_BF(TCMR_PERIOD, tcmr_period) |
|
| SSC_BF(TCMR_CKI, SSC_CKI_FALLING); |
|
|
|
rfmr = SSC_BF(RFMR_FSLEN_EXT, fslen_ext) |
|
| SSC_BF(RFMR_FSEDGE, SSC_FSEDGE_POSITIVE) |
|
| SSC_BF(RFMR_FSOS, fs_osync) |
|
| SSC_BF(RFMR_FSLEN, fslen) |
|
| SSC_BF(RFMR_DATNB, (channels - 1)) |
|
| SSC_BIT(RFMR_MSBF) |
|
| SSC_BF(RFMR_LOOP, 0) |
|
| SSC_BF(RFMR_DATLEN, (bits - 1)); |
|
|
|
tfmr = SSC_BF(TFMR_FSLEN_EXT, fslen_ext) |
|
| SSC_BF(TFMR_FSEDGE, SSC_FSEDGE_POSITIVE) |
|
| SSC_BF(TFMR_FSDEN, 0) |
|
| SSC_BF(TFMR_FSOS, fs_osync) |
|
| SSC_BF(TFMR_FSLEN, fslen) |
|
| SSC_BF(TFMR_DATNB, (channels - 1)) |
|
| SSC_BIT(TFMR_MSBF) |
|
| SSC_BF(TFMR_DATDEF, 0) |
|
| SSC_BF(TFMR_DATLEN, (bits - 1)); |
|
|
|
if (fslen_ext && !ssc->pdata->has_fslen_ext) { |
|
dev_err(dai->dev, "sample size %d is too large for SSC device\n", |
|
bits); |
|
return -EINVAL; |
|
} |
|
|
|
pr_debug("atmel_ssc_hw_params: " |
|
"RCMR=%08x RFMR=%08x TCMR=%08x TFMR=%08x\n", |
|
rcmr, rfmr, tcmr, tfmr); |
|
|
|
if (!ssc_p->initialized) { |
|
if (!ssc_p->ssc->pdata->use_dma) { |
|
ssc_writel(ssc_p->ssc->regs, PDC_RPR, 0); |
|
ssc_writel(ssc_p->ssc->regs, PDC_RCR, 0); |
|
ssc_writel(ssc_p->ssc->regs, PDC_RNPR, 0); |
|
ssc_writel(ssc_p->ssc->regs, PDC_RNCR, 0); |
|
|
|
ssc_writel(ssc_p->ssc->regs, PDC_TPR, 0); |
|
ssc_writel(ssc_p->ssc->regs, PDC_TCR, 0); |
|
ssc_writel(ssc_p->ssc->regs, PDC_TNPR, 0); |
|
ssc_writel(ssc_p->ssc->regs, PDC_TNCR, 0); |
|
} |
|
|
|
ret = request_irq(ssc_p->ssc->irq, atmel_ssc_interrupt, 0, |
|
ssc_p->name, ssc_p); |
|
if (ret < 0) { |
|
printk(KERN_WARNING |
|
"atmel_ssc_dai: request_irq failure\n"); |
|
pr_debug("Atmel_ssc_dai: Stopping clock\n"); |
|
clk_disable(ssc_p->ssc->clk); |
|
return ret; |
|
} |
|
|
|
ssc_p->initialized = 1; |
|
} |
|
|
|
/* set SSC clock mode register */ |
|
ssc_writel(ssc_p->ssc->regs, CMR, cmr_div); |
|
|
|
/* set receive clock mode and format */ |
|
ssc_writel(ssc_p->ssc->regs, RCMR, rcmr); |
|
ssc_writel(ssc_p->ssc->regs, RFMR, rfmr); |
|
|
|
/* set transmit clock mode and format */ |
|
ssc_writel(ssc_p->ssc->regs, TCMR, tcmr); |
|
ssc_writel(ssc_p->ssc->regs, TFMR, tfmr); |
|
|
|
pr_debug("atmel_ssc_dai,hw_params: SSC initialized\n"); |
|
return 0; |
|
} |
|
|
|
|
|
static int atmel_ssc_prepare(struct snd_pcm_substream *substream, |
|
struct snd_soc_dai *dai) |
|
{ |
|
struct platform_device *pdev = to_platform_device(dai->dev); |
|
struct atmel_ssc_info *ssc_p = &ssc_info[pdev->id]; |
|
struct atmel_pcm_dma_params *dma_params; |
|
int dir; |
|
|
|
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) |
|
dir = 0; |
|
else |
|
dir = 1; |
|
|
|
dma_params = ssc_p->dma_params[dir]; |
|
|
|
ssc_writel(ssc_p->ssc->regs, CR, dma_params->mask->ssc_disable); |
|
ssc_writel(ssc_p->ssc->regs, IDR, dma_params->mask->ssc_error); |
|
|
|
pr_debug("%s enabled SSC_SR=0x%08x\n", |
|
dir ? "receive" : "transmit", |
|
ssc_readl(ssc_p->ssc->regs, SR)); |
|
return 0; |
|
} |
|
|
|
static int atmel_ssc_trigger(struct snd_pcm_substream *substream, |
|
int cmd, struct snd_soc_dai *dai) |
|
{ |
|
struct platform_device *pdev = to_platform_device(dai->dev); |
|
struct atmel_ssc_info *ssc_p = &ssc_info[pdev->id]; |
|
struct atmel_pcm_dma_params *dma_params; |
|
int dir; |
|
|
|
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) |
|
dir = 0; |
|
else |
|
dir = 1; |
|
|
|
dma_params = ssc_p->dma_params[dir]; |
|
|
|
switch (cmd) { |
|
case SNDRV_PCM_TRIGGER_START: |
|
case SNDRV_PCM_TRIGGER_RESUME: |
|
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: |
|
ssc_writel(ssc_p->ssc->regs, CR, dma_params->mask->ssc_enable); |
|
break; |
|
default: |
|
ssc_writel(ssc_p->ssc->regs, CR, dma_params->mask->ssc_disable); |
|
break; |
|
} |
|
|
|
return 0; |
|
} |
|
|
|
#ifdef CONFIG_PM |
|
static int atmel_ssc_suspend(struct snd_soc_component *component) |
|
{ |
|
struct atmel_ssc_info *ssc_p; |
|
struct platform_device *pdev = to_platform_device(component->dev); |
|
|
|
if (!snd_soc_component_active(component)) |
|
return 0; |
|
|
|
ssc_p = &ssc_info[pdev->id]; |
|
|
|
/* Save the status register before disabling transmit and receive */ |
|
ssc_p->ssc_state.ssc_sr = ssc_readl(ssc_p->ssc->regs, SR); |
|
ssc_writel(ssc_p->ssc->regs, CR, SSC_BIT(CR_TXDIS) | SSC_BIT(CR_RXDIS)); |
|
|
|
/* Save the current interrupt mask, then disable unmasked interrupts */ |
|
ssc_p->ssc_state.ssc_imr = ssc_readl(ssc_p->ssc->regs, IMR); |
|
ssc_writel(ssc_p->ssc->regs, IDR, ssc_p->ssc_state.ssc_imr); |
|
|
|
ssc_p->ssc_state.ssc_cmr = ssc_readl(ssc_p->ssc->regs, CMR); |
|
ssc_p->ssc_state.ssc_rcmr = ssc_readl(ssc_p->ssc->regs, RCMR); |
|
ssc_p->ssc_state.ssc_rfmr = ssc_readl(ssc_p->ssc->regs, RFMR); |
|
ssc_p->ssc_state.ssc_tcmr = ssc_readl(ssc_p->ssc->regs, TCMR); |
|
ssc_p->ssc_state.ssc_tfmr = ssc_readl(ssc_p->ssc->regs, TFMR); |
|
|
|
return 0; |
|
} |
|
|
|
static int atmel_ssc_resume(struct snd_soc_component *component) |
|
{ |
|
struct atmel_ssc_info *ssc_p; |
|
struct platform_device *pdev = to_platform_device(component->dev); |
|
u32 cr; |
|
|
|
if (!snd_soc_component_active(component)) |
|
return 0; |
|
|
|
ssc_p = &ssc_info[pdev->id]; |
|
|
|
/* restore SSC register settings */ |
|
ssc_writel(ssc_p->ssc->regs, TFMR, ssc_p->ssc_state.ssc_tfmr); |
|
ssc_writel(ssc_p->ssc->regs, TCMR, ssc_p->ssc_state.ssc_tcmr); |
|
ssc_writel(ssc_p->ssc->regs, RFMR, ssc_p->ssc_state.ssc_rfmr); |
|
ssc_writel(ssc_p->ssc->regs, RCMR, ssc_p->ssc_state.ssc_rcmr); |
|
ssc_writel(ssc_p->ssc->regs, CMR, ssc_p->ssc_state.ssc_cmr); |
|
|
|
/* re-enable interrupts */ |
|
ssc_writel(ssc_p->ssc->regs, IER, ssc_p->ssc_state.ssc_imr); |
|
|
|
/* Re-enable receive and transmit as appropriate */ |
|
cr = 0; |
|
cr |= |
|
(ssc_p->ssc_state.ssc_sr & SSC_BIT(SR_RXEN)) ? SSC_BIT(CR_RXEN) : 0; |
|
cr |= |
|
(ssc_p->ssc_state.ssc_sr & SSC_BIT(SR_TXEN)) ? SSC_BIT(CR_TXEN) : 0; |
|
ssc_writel(ssc_p->ssc->regs, CR, cr); |
|
|
|
return 0; |
|
} |
|
#else /* CONFIG_PM */ |
|
# define atmel_ssc_suspend NULL |
|
# define atmel_ssc_resume NULL |
|
#endif /* CONFIG_PM */ |
|
|
|
#define ATMEL_SSC_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE |\ |
|
SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE) |
|
|
|
static const struct snd_soc_dai_ops atmel_ssc_dai_ops = { |
|
.startup = atmel_ssc_startup, |
|
.shutdown = atmel_ssc_shutdown, |
|
.prepare = atmel_ssc_prepare, |
|
.trigger = atmel_ssc_trigger, |
|
.hw_params = atmel_ssc_hw_params, |
|
.set_fmt = atmel_ssc_set_dai_fmt, |
|
.set_clkdiv = atmel_ssc_set_dai_clkdiv, |
|
}; |
|
|
|
static struct snd_soc_dai_driver atmel_ssc_dai = { |
|
.playback = { |
|
.channels_min = 1, |
|
.channels_max = 2, |
|
.rates = SNDRV_PCM_RATE_CONTINUOUS, |
|
.rate_min = 8000, |
|
.rate_max = 384000, |
|
.formats = ATMEL_SSC_FORMATS,}, |
|
.capture = { |
|
.channels_min = 1, |
|
.channels_max = 2, |
|
.rates = SNDRV_PCM_RATE_CONTINUOUS, |
|
.rate_min = 8000, |
|
.rate_max = 384000, |
|
.formats = ATMEL_SSC_FORMATS,}, |
|
.ops = &atmel_ssc_dai_ops, |
|
}; |
|
|
|
static const struct snd_soc_component_driver atmel_ssc_component = { |
|
.name = "atmel-ssc", |
|
.suspend = atmel_ssc_suspend, |
|
.resume = atmel_ssc_resume, |
|
}; |
|
|
|
static int asoc_ssc_init(struct device *dev) |
|
{ |
|
struct ssc_device *ssc = dev_get_drvdata(dev); |
|
int ret; |
|
|
|
ret = devm_snd_soc_register_component(dev, &atmel_ssc_component, |
|
&atmel_ssc_dai, 1); |
|
if (ret) { |
|
dev_err(dev, "Could not register DAI: %d\n", ret); |
|
return ret; |
|
} |
|
|
|
if (ssc->pdata->use_dma) |
|
ret = atmel_pcm_dma_platform_register(dev); |
|
else |
|
ret = atmel_pcm_pdc_platform_register(dev); |
|
|
|
if (ret) { |
|
dev_err(dev, "Could not register PCM: %d\n", ret); |
|
return ret; |
|
} |
|
|
|
return 0; |
|
} |
|
|
|
/** |
|
* atmel_ssc_set_audio - Allocate the specified SSC for audio use. |
|
* @ssc_id: SSD ID in [0, NUM_SSC_DEVICES[ |
|
*/ |
|
int atmel_ssc_set_audio(int ssc_id) |
|
{ |
|
struct ssc_device *ssc; |
|
int ret; |
|
|
|
/* If we can grab the SSC briefly to parent the DAI device off it */ |
|
ssc = ssc_request(ssc_id); |
|
if (IS_ERR(ssc)) { |
|
pr_err("Unable to parent ASoC SSC DAI on SSC: %ld\n", |
|
PTR_ERR(ssc)); |
|
return PTR_ERR(ssc); |
|
} else { |
|
ssc_info[ssc_id].ssc = ssc; |
|
} |
|
|
|
ret = asoc_ssc_init(&ssc->pdev->dev); |
|
|
|
return ret; |
|
} |
|
EXPORT_SYMBOL_GPL(atmel_ssc_set_audio); |
|
|
|
void atmel_ssc_put_audio(int ssc_id) |
|
{ |
|
struct ssc_device *ssc = ssc_info[ssc_id].ssc; |
|
|
|
ssc_free(ssc); |
|
} |
|
EXPORT_SYMBOL_GPL(atmel_ssc_put_audio); |
|
|
|
/* Module information */ |
|
MODULE_AUTHOR("Sedji Gaouaou, [email protected], www.atmel.com"); |
|
MODULE_DESCRIPTION("ATMEL SSC ASoC Interface"); |
|
MODULE_LICENSE("GPL");
|
|
|