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79 lines
2.8 KiB
79 lines
2.8 KiB
/* SPDX-License-Identifier: GPL-2.0 */ |
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/* |
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* Copyright (C) 2018-2019 SiFive, Inc. |
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* Wesley Terpstra |
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* Paul Walmsley |
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*/ |
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#ifndef __LINUX_CLK_ANALOGBITS_WRPLL_CLN28HPC_H |
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#define __LINUX_CLK_ANALOGBITS_WRPLL_CLN28HPC_H |
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#include <linux/types.h> |
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/* DIVQ_VALUES: number of valid DIVQ values */ |
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#define DIVQ_VALUES 6 |
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/* |
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* Bit definitions for struct wrpll_cfg.flags |
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* |
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* WRPLL_FLAGS_BYPASS_FLAG: if set, the PLL is either in bypass, or should be |
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* programmed to enter bypass |
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* WRPLL_FLAGS_RESET_FLAG: if set, the PLL is in reset |
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* WRPLL_FLAGS_INT_FEEDBACK_FLAG: if set, the PLL is configured for internal |
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* feedback mode |
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* WRPLL_FLAGS_EXT_FEEDBACK_FLAG: if set, the PLL is configured for external |
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* feedback mode (not yet supported by this driver) |
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*/ |
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#define WRPLL_FLAGS_BYPASS_SHIFT 0 |
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#define WRPLL_FLAGS_BYPASS_MASK BIT(WRPLL_FLAGS_BYPASS_SHIFT) |
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#define WRPLL_FLAGS_RESET_SHIFT 1 |
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#define WRPLL_FLAGS_RESET_MASK BIT(WRPLL_FLAGS_RESET_SHIFT) |
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#define WRPLL_FLAGS_INT_FEEDBACK_SHIFT 2 |
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#define WRPLL_FLAGS_INT_FEEDBACK_MASK BIT(WRPLL_FLAGS_INT_FEEDBACK_SHIFT) |
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#define WRPLL_FLAGS_EXT_FEEDBACK_SHIFT 3 |
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#define WRPLL_FLAGS_EXT_FEEDBACK_MASK BIT(WRPLL_FLAGS_EXT_FEEDBACK_SHIFT) |
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/** |
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* struct wrpll_cfg - WRPLL configuration values |
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* @divr: reference divider value (6 bits), as presented to the PLL signals |
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* @divf: feedback divider value (9 bits), as presented to the PLL signals |
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* @divq: output divider value (3 bits), as presented to the PLL signals |
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* @flags: PLL configuration flags. See above for more information |
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* @range: PLL loop filter range. See below for more information |
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* @output_rate_cache: cached output rates, swept across DIVQ |
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* @parent_rate: PLL refclk rate for which values are valid |
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* @max_r: maximum possible R divider value, given @parent_rate |
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* @init_r: initial R divider value to start the search from |
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* |
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* @divr, @divq, @divq, @range represent what the PLL expects to see |
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* on its input signals. Thus @divr and @divf are the actual divisors |
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* minus one. @divq is a power-of-two divider; for example, 1 = |
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* divide-by-2 and 6 = divide-by-64. 0 is an invalid @divq value. |
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* |
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* When initially passing a struct wrpll_cfg record, the |
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* record should be zero-initialized with the exception of the @flags |
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* field. The only flag bits that need to be set are either |
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* WRPLL_FLAGS_INT_FEEDBACK or WRPLL_FLAGS_EXT_FEEDBACK. |
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*/ |
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struct wrpll_cfg { |
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u8 divr; |
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u8 divq; |
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u8 range; |
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u8 flags; |
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u16 divf; |
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/* private: */ |
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u32 output_rate_cache[DIVQ_VALUES]; |
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unsigned long parent_rate; |
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u8 max_r; |
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u8 init_r; |
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}; |
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int wrpll_configure_for_rate(struct wrpll_cfg *c, u32 target_rate, |
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unsigned long parent_rate); |
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unsigned int wrpll_calc_max_lock_us(const struct wrpll_cfg *c); |
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unsigned long wrpll_calc_output_rate(const struct wrpll_cfg *c, |
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unsigned long parent_rate); |
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#endif /* __LINUX_CLK_ANALOGBITS_WRPLL_CLN28HPC_H */
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