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541 lines
12 KiB
541 lines
12 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* Copyright 2021 NXP |
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*/ |
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#include <linux/pcs/pcs-xpcs.h> |
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#include <linux/of_mdio.h> |
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#include "sja1105.h" |
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|
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#define SJA1110_PCS_BANK_REG SJA1110_SPI_ADDR(0x3fc) |
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|
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int sja1105_pcs_mdio_read(struct mii_bus *bus, int phy, int reg) |
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{ |
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struct sja1105_mdio_private *mdio_priv = bus->priv; |
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struct sja1105_private *priv = mdio_priv->priv; |
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u64 addr; |
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u32 tmp; |
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u16 mmd; |
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int rc; |
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|
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if (!(reg & MII_ADDR_C45)) |
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return -EINVAL; |
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|
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mmd = (reg >> MII_DEVADDR_C45_SHIFT) & 0x1f; |
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addr = (mmd << 16) | (reg & GENMASK(15, 0)); |
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|
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if (mmd != MDIO_MMD_VEND1 && mmd != MDIO_MMD_VEND2) |
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return 0xffff; |
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|
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if (mmd == MDIO_MMD_VEND2 && (reg & GENMASK(15, 0)) == MII_PHYSID1) |
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return NXP_SJA1105_XPCS_ID >> 16; |
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if (mmd == MDIO_MMD_VEND2 && (reg & GENMASK(15, 0)) == MII_PHYSID2) |
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return NXP_SJA1105_XPCS_ID & GENMASK(15, 0); |
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|
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rc = sja1105_xfer_u32(priv, SPI_READ, addr, &tmp, NULL); |
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if (rc < 0) |
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return rc; |
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|
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return tmp & 0xffff; |
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} |
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|
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int sja1105_pcs_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val) |
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{ |
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struct sja1105_mdio_private *mdio_priv = bus->priv; |
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struct sja1105_private *priv = mdio_priv->priv; |
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u64 addr; |
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u32 tmp; |
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u16 mmd; |
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|
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if (!(reg & MII_ADDR_C45)) |
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return -EINVAL; |
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|
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mmd = (reg >> MII_DEVADDR_C45_SHIFT) & 0x1f; |
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addr = (mmd << 16) | (reg & GENMASK(15, 0)); |
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tmp = val; |
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|
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if (mmd != MDIO_MMD_VEND1 && mmd != MDIO_MMD_VEND2) |
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return -EINVAL; |
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|
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return sja1105_xfer_u32(priv, SPI_WRITE, addr, &tmp, NULL); |
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} |
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|
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int sja1110_pcs_mdio_read(struct mii_bus *bus, int phy, int reg) |
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{ |
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struct sja1105_mdio_private *mdio_priv = bus->priv; |
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struct sja1105_private *priv = mdio_priv->priv; |
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const struct sja1105_regs *regs = priv->info->regs; |
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int offset, bank; |
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u64 addr; |
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u32 tmp; |
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u16 mmd; |
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int rc; |
|
|
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if (!(reg & MII_ADDR_C45)) |
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return -EINVAL; |
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|
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if (regs->pcs_base[phy] == SJA1105_RSV_ADDR) |
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return -ENODEV; |
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|
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mmd = (reg >> MII_DEVADDR_C45_SHIFT) & 0x1f; |
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addr = (mmd << 16) | (reg & GENMASK(15, 0)); |
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|
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if (mmd == MDIO_MMD_VEND2 && (reg & GENMASK(15, 0)) == MII_PHYSID1) |
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return NXP_SJA1110_XPCS_ID >> 16; |
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if (mmd == MDIO_MMD_VEND2 && (reg & GENMASK(15, 0)) == MII_PHYSID2) |
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return NXP_SJA1110_XPCS_ID & GENMASK(15, 0); |
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|
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bank = addr >> 8; |
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offset = addr & GENMASK(7, 0); |
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|
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/* This addressing scheme reserves register 0xff for the bank address |
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* register, so that can never be addressed. |
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*/ |
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if (WARN_ON(offset == 0xff)) |
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return -ENODEV; |
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|
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tmp = bank; |
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|
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rc = sja1105_xfer_u32(priv, SPI_WRITE, |
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regs->pcs_base[phy] + SJA1110_PCS_BANK_REG, |
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&tmp, NULL); |
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if (rc < 0) |
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return rc; |
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|
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rc = sja1105_xfer_u32(priv, SPI_READ, regs->pcs_base[phy] + offset, |
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&tmp, NULL); |
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if (rc < 0) |
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return rc; |
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|
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return tmp & 0xffff; |
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} |
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|
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int sja1110_pcs_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val) |
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{ |
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struct sja1105_mdio_private *mdio_priv = bus->priv; |
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struct sja1105_private *priv = mdio_priv->priv; |
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const struct sja1105_regs *regs = priv->info->regs; |
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int offset, bank; |
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u64 addr; |
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u32 tmp; |
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u16 mmd; |
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int rc; |
|
|
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if (!(reg & MII_ADDR_C45)) |
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return -EINVAL; |
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|
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if (regs->pcs_base[phy] == SJA1105_RSV_ADDR) |
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return -ENODEV; |
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|
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mmd = (reg >> MII_DEVADDR_C45_SHIFT) & 0x1f; |
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addr = (mmd << 16) | (reg & GENMASK(15, 0)); |
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|
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bank = addr >> 8; |
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offset = addr & GENMASK(7, 0); |
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|
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/* This addressing scheme reserves register 0xff for the bank address |
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* register, so that can never be addressed. |
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*/ |
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if (WARN_ON(offset == 0xff)) |
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return -ENODEV; |
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|
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tmp = bank; |
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|
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rc = sja1105_xfer_u32(priv, SPI_WRITE, |
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regs->pcs_base[phy] + SJA1110_PCS_BANK_REG, |
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&tmp, NULL); |
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if (rc < 0) |
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return rc; |
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|
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tmp = val; |
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|
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return sja1105_xfer_u32(priv, SPI_WRITE, regs->pcs_base[phy] + offset, |
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&tmp, NULL); |
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} |
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|
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enum sja1105_mdio_opcode { |
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SJA1105_C45_ADDR = 0, |
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SJA1105_C22 = 1, |
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SJA1105_C45_DATA = 2, |
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SJA1105_C45_DATA_AUTOINC = 3, |
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}; |
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|
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static u64 sja1105_base_t1_encode_addr(struct sja1105_private *priv, |
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int phy, enum sja1105_mdio_opcode op, |
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int xad) |
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{ |
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const struct sja1105_regs *regs = priv->info->regs; |
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|
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return regs->mdio_100base_t1 | (phy << 7) | (op << 5) | (xad << 0); |
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} |
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static int sja1105_base_t1_mdio_read(struct mii_bus *bus, int phy, int reg) |
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{ |
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struct sja1105_mdio_private *mdio_priv = bus->priv; |
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struct sja1105_private *priv = mdio_priv->priv; |
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u64 addr; |
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u32 tmp; |
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int rc; |
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|
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if (reg & MII_ADDR_C45) { |
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u16 mmd = (reg >> MII_DEVADDR_C45_SHIFT) & 0x1f; |
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addr = sja1105_base_t1_encode_addr(priv, phy, SJA1105_C45_ADDR, |
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mmd); |
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tmp = reg & MII_REGADDR_C45_MASK; |
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rc = sja1105_xfer_u32(priv, SPI_WRITE, addr, &tmp, NULL); |
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if (rc < 0) |
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return rc; |
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addr = sja1105_base_t1_encode_addr(priv, phy, SJA1105_C45_DATA, |
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mmd); |
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rc = sja1105_xfer_u32(priv, SPI_READ, addr, &tmp, NULL); |
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if (rc < 0) |
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return rc; |
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|
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return tmp & 0xffff; |
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} |
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|
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/* Clause 22 read */ |
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addr = sja1105_base_t1_encode_addr(priv, phy, SJA1105_C22, reg & 0x1f); |
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|
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rc = sja1105_xfer_u32(priv, SPI_READ, addr, &tmp, NULL); |
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if (rc < 0) |
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return rc; |
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|
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return tmp & 0xffff; |
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} |
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static int sja1105_base_t1_mdio_write(struct mii_bus *bus, int phy, int reg, |
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u16 val) |
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{ |
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struct sja1105_mdio_private *mdio_priv = bus->priv; |
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struct sja1105_private *priv = mdio_priv->priv; |
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u64 addr; |
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u32 tmp; |
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int rc; |
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|
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if (reg & MII_ADDR_C45) { |
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u16 mmd = (reg >> MII_DEVADDR_C45_SHIFT) & 0x1f; |
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addr = sja1105_base_t1_encode_addr(priv, phy, SJA1105_C45_ADDR, |
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mmd); |
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tmp = reg & MII_REGADDR_C45_MASK; |
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rc = sja1105_xfer_u32(priv, SPI_WRITE, addr, &tmp, NULL); |
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if (rc < 0) |
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return rc; |
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addr = sja1105_base_t1_encode_addr(priv, phy, SJA1105_C45_DATA, |
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mmd); |
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tmp = val & 0xffff; |
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rc = sja1105_xfer_u32(priv, SPI_WRITE, addr, &tmp, NULL); |
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if (rc < 0) |
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return rc; |
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return 0; |
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} |
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/* Clause 22 write */ |
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addr = sja1105_base_t1_encode_addr(priv, phy, SJA1105_C22, reg & 0x1f); |
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tmp = val & 0xffff; |
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return sja1105_xfer_u32(priv, SPI_WRITE, addr, &tmp, NULL); |
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} |
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static int sja1105_base_tx_mdio_read(struct mii_bus *bus, int phy, int reg) |
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{ |
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struct sja1105_mdio_private *mdio_priv = bus->priv; |
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struct sja1105_private *priv = mdio_priv->priv; |
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const struct sja1105_regs *regs = priv->info->regs; |
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u32 tmp; |
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int rc; |
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|
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rc = sja1105_xfer_u32(priv, SPI_READ, regs->mdio_100base_tx + reg, |
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&tmp, NULL); |
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if (rc < 0) |
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return rc; |
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|
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return tmp & 0xffff; |
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} |
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static int sja1105_base_tx_mdio_write(struct mii_bus *bus, int phy, int reg, |
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u16 val) |
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{ |
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struct sja1105_mdio_private *mdio_priv = bus->priv; |
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struct sja1105_private *priv = mdio_priv->priv; |
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const struct sja1105_regs *regs = priv->info->regs; |
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u32 tmp = val; |
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return sja1105_xfer_u32(priv, SPI_WRITE, regs->mdio_100base_tx + reg, |
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&tmp, NULL); |
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} |
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static int sja1105_mdiobus_base_tx_register(struct sja1105_private *priv, |
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struct device_node *mdio_node) |
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{ |
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struct sja1105_mdio_private *mdio_priv; |
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struct device_node *np; |
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struct mii_bus *bus; |
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int rc = 0; |
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np = of_get_compatible_child(mdio_node, "nxp,sja1110-base-tx-mdio"); |
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if (!np) |
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return 0; |
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|
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if (!of_device_is_available(np)) |
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goto out_put_np; |
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bus = mdiobus_alloc_size(sizeof(*mdio_priv)); |
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if (!bus) { |
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rc = -ENOMEM; |
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goto out_put_np; |
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} |
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bus->name = "SJA1110 100base-TX MDIO bus"; |
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snprintf(bus->id, MII_BUS_ID_SIZE, "%s-base-tx", |
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dev_name(priv->ds->dev)); |
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bus->read = sja1105_base_tx_mdio_read; |
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bus->write = sja1105_base_tx_mdio_write; |
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bus->parent = priv->ds->dev; |
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mdio_priv = bus->priv; |
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mdio_priv->priv = priv; |
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rc = of_mdiobus_register(bus, np); |
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if (rc) { |
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mdiobus_free(bus); |
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goto out_put_np; |
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} |
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priv->mdio_base_tx = bus; |
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out_put_np: |
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of_node_put(np); |
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return rc; |
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} |
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static void sja1105_mdiobus_base_tx_unregister(struct sja1105_private *priv) |
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{ |
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if (!priv->mdio_base_tx) |
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return; |
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mdiobus_unregister(priv->mdio_base_tx); |
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mdiobus_free(priv->mdio_base_tx); |
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priv->mdio_base_tx = NULL; |
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} |
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static int sja1105_mdiobus_base_t1_register(struct sja1105_private *priv, |
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struct device_node *mdio_node) |
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{ |
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struct sja1105_mdio_private *mdio_priv; |
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struct device_node *np; |
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struct mii_bus *bus; |
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int rc = 0; |
|
|
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np = of_get_compatible_child(mdio_node, "nxp,sja1110-base-t1-mdio"); |
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if (!np) |
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return 0; |
|
|
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if (!of_device_is_available(np)) |
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goto out_put_np; |
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|
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bus = mdiobus_alloc_size(sizeof(*mdio_priv)); |
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if (!bus) { |
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rc = -ENOMEM; |
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goto out_put_np; |
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} |
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|
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bus->name = "SJA1110 100base-T1 MDIO bus"; |
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snprintf(bus->id, MII_BUS_ID_SIZE, "%s-base-t1", |
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dev_name(priv->ds->dev)); |
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bus->read = sja1105_base_t1_mdio_read; |
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bus->write = sja1105_base_t1_mdio_write; |
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bus->parent = priv->ds->dev; |
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mdio_priv = bus->priv; |
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mdio_priv->priv = priv; |
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|
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rc = of_mdiobus_register(bus, np); |
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if (rc) { |
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mdiobus_free(bus); |
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goto out_put_np; |
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} |
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priv->mdio_base_t1 = bus; |
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|
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out_put_np: |
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of_node_put(np); |
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|
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return rc; |
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} |
|
|
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static void sja1105_mdiobus_base_t1_unregister(struct sja1105_private *priv) |
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{ |
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if (!priv->mdio_base_t1) |
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return; |
|
|
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mdiobus_unregister(priv->mdio_base_t1); |
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mdiobus_free(priv->mdio_base_t1); |
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priv->mdio_base_t1 = NULL; |
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} |
|
|
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static int sja1105_mdiobus_pcs_register(struct sja1105_private *priv) |
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{ |
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struct sja1105_mdio_private *mdio_priv; |
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struct dsa_switch *ds = priv->ds; |
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struct mii_bus *bus; |
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int rc = 0; |
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int port; |
|
|
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if (!priv->info->pcs_mdio_read || !priv->info->pcs_mdio_write) |
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return 0; |
|
|
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bus = mdiobus_alloc_size(sizeof(*mdio_priv)); |
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if (!bus) |
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return -ENOMEM; |
|
|
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bus->name = "SJA1105 PCS MDIO bus"; |
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snprintf(bus->id, MII_BUS_ID_SIZE, "%s-pcs", |
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dev_name(ds->dev)); |
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bus->read = priv->info->pcs_mdio_read; |
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bus->write = priv->info->pcs_mdio_write; |
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bus->parent = ds->dev; |
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/* There is no PHY on this MDIO bus => mask out all PHY addresses |
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* from auto probing. |
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*/ |
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bus->phy_mask = ~0; |
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mdio_priv = bus->priv; |
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mdio_priv->priv = priv; |
|
|
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rc = mdiobus_register(bus); |
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if (rc) { |
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mdiobus_free(bus); |
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return rc; |
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} |
|
|
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for (port = 0; port < ds->num_ports; port++) { |
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struct mdio_device *mdiodev; |
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struct dw_xpcs *xpcs; |
|
|
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if (dsa_is_unused_port(ds, port)) |
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continue; |
|
|
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if (priv->phy_mode[port] != PHY_INTERFACE_MODE_SGMII && |
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priv->phy_mode[port] != PHY_INTERFACE_MODE_2500BASEX) |
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continue; |
|
|
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mdiodev = mdio_device_create(bus, port); |
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if (IS_ERR(mdiodev)) { |
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rc = PTR_ERR(mdiodev); |
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goto out_pcs_free; |
|
} |
|
|
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xpcs = xpcs_create(mdiodev, priv->phy_mode[port]); |
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if (IS_ERR(xpcs)) { |
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rc = PTR_ERR(xpcs); |
|
goto out_pcs_free; |
|
} |
|
|
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priv->xpcs[port] = xpcs; |
|
} |
|
|
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priv->mdio_pcs = bus; |
|
|
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return 0; |
|
|
|
out_pcs_free: |
|
for (port = 0; port < ds->num_ports; port++) { |
|
if (!priv->xpcs[port]) |
|
continue; |
|
|
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mdio_device_free(priv->xpcs[port]->mdiodev); |
|
xpcs_destroy(priv->xpcs[port]); |
|
priv->xpcs[port] = NULL; |
|
} |
|
|
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mdiobus_unregister(bus); |
|
mdiobus_free(bus); |
|
|
|
return rc; |
|
} |
|
|
|
static void sja1105_mdiobus_pcs_unregister(struct sja1105_private *priv) |
|
{ |
|
struct dsa_switch *ds = priv->ds; |
|
int port; |
|
|
|
if (!priv->mdio_pcs) |
|
return; |
|
|
|
for (port = 0; port < ds->num_ports; port++) { |
|
if (!priv->xpcs[port]) |
|
continue; |
|
|
|
mdio_device_free(priv->xpcs[port]->mdiodev); |
|
xpcs_destroy(priv->xpcs[port]); |
|
priv->xpcs[port] = NULL; |
|
} |
|
|
|
mdiobus_unregister(priv->mdio_pcs); |
|
mdiobus_free(priv->mdio_pcs); |
|
priv->mdio_pcs = NULL; |
|
} |
|
|
|
int sja1105_mdiobus_register(struct dsa_switch *ds) |
|
{ |
|
struct sja1105_private *priv = ds->priv; |
|
const struct sja1105_regs *regs = priv->info->regs; |
|
struct device_node *switch_node = ds->dev->of_node; |
|
struct device_node *mdio_node; |
|
int rc; |
|
|
|
rc = sja1105_mdiobus_pcs_register(priv); |
|
if (rc) |
|
return rc; |
|
|
|
mdio_node = of_get_child_by_name(switch_node, "mdios"); |
|
if (!mdio_node) |
|
return 0; |
|
|
|
if (!of_device_is_available(mdio_node)) |
|
goto out_put_mdio_node; |
|
|
|
if (regs->mdio_100base_tx != SJA1105_RSV_ADDR) { |
|
rc = sja1105_mdiobus_base_tx_register(priv, mdio_node); |
|
if (rc) |
|
goto err_put_mdio_node; |
|
} |
|
|
|
if (regs->mdio_100base_t1 != SJA1105_RSV_ADDR) { |
|
rc = sja1105_mdiobus_base_t1_register(priv, mdio_node); |
|
if (rc) |
|
goto err_free_base_tx_mdiobus; |
|
} |
|
|
|
out_put_mdio_node: |
|
of_node_put(mdio_node); |
|
|
|
return 0; |
|
|
|
err_free_base_tx_mdiobus: |
|
sja1105_mdiobus_base_tx_unregister(priv); |
|
err_put_mdio_node: |
|
of_node_put(mdio_node); |
|
sja1105_mdiobus_pcs_unregister(priv); |
|
|
|
return rc; |
|
} |
|
|
|
void sja1105_mdiobus_unregister(struct dsa_switch *ds) |
|
{ |
|
struct sja1105_private *priv = ds->priv; |
|
|
|
sja1105_mdiobus_base_t1_unregister(priv); |
|
sja1105_mdiobus_base_tx_unregister(priv); |
|
sja1105_mdiobus_pcs_unregister(priv); |
|
}
|
|
|