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54 lines
1.5 KiB
54 lines
1.5 KiB
/* SPDX-License-Identifier: GPL-2.0-only */ |
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/* |
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* ADXL313 3-Axis Digital Accelerometer |
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* |
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* Copyright (c) 2021 Lucas Stankus <[email protected]> |
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*/ |
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#ifndef _ADXL313_H_ |
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#define _ADXL313_H_ |
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/* ADXL313 register definitions */ |
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#define ADXL313_REG_DEVID0 0x00 |
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#define ADXL313_REG_DEVID1 0x01 |
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#define ADXL313_REG_PARTID 0x02 |
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#define ADXL313_REG_XID 0x04 |
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#define ADXL313_REG_SOFT_RESET 0x18 |
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#define ADXL313_REG_OFS_AXIS(index) (0x1E + (index)) |
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#define ADXL313_REG_THRESH_ACT 0x24 |
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#define ADXL313_REG_ACT_INACT_CTL 0x27 |
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#define ADXL313_REG_BW_RATE 0x2C |
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#define ADXL313_REG_POWER_CTL 0x2D |
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#define ADXL313_REG_INT_MAP 0x2F |
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#define ADXL313_REG_DATA_FORMAT 0x31 |
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#define ADXL313_REG_DATA_AXIS(index) (0x32 + ((index) * 2)) |
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#define ADXL313_REG_FIFO_CTL 0x38 |
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#define ADXL313_REG_FIFO_STATUS 0x39 |
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#define ADXL313_DEVID0 0xAD |
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#define ADXL313_DEVID1 0x1D |
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#define ADXL313_PARTID 0xCB |
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#define ADXL313_SOFT_RESET 0x52 |
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#define ADXL313_RATE_MSK GENMASK(3, 0) |
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#define ADXL313_RATE_BASE 6 |
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#define ADXL313_POWER_CTL_MSK GENMASK(3, 2) |
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#define ADXL313_MEASUREMENT_MODE BIT(3) |
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#define ADXL313_RANGE_MSK GENMASK(1, 0) |
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#define ADXL313_RANGE_4G 3 |
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#define ADXL313_FULL_RES BIT(3) |
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#define ADXL313_SPI_3WIRE BIT(6) |
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#define ADXL313_I2C_DISABLE BIT(6) |
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extern const struct regmap_access_table adxl313_readable_regs_table; |
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extern const struct regmap_access_table adxl313_writable_regs_table; |
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int adxl313_core_probe(struct device *dev, |
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struct regmap *regmap, |
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const char *name, |
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int (*setup)(struct device *, struct regmap *)); |
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#endif /* _ADXL313_H_ */
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