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198 lines
5.6 KiB
198 lines
5.6 KiB
/* SPDX-License-Identifier: GPL-2.0 */ |
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/* |
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* sh7760fb.h -- platform data for SH7760/SH7763 LCDC framebuffer driver. |
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* |
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* (c) 2006-2008 MSC Vertriebsges.m.b.H., |
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* Manuel Lauss <[email protected]> |
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* (c) 2008 Nobuhiro Iwamatsu <[email protected]> |
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*/ |
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#ifndef _ASM_SH_SH7760FB_H |
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#define _ASM_SH_SH7760FB_H |
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/* |
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* some bits of the colormap registers should be written as zero. |
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* create a mask for that. |
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*/ |
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#define SH7760FB_PALETTE_MASK 0x00f8fcf8 |
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/* The LCDC dma engine always sets bits 27-26 to 1: this is Area3 */ |
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#define SH7760FB_DMA_MASK 0x0C000000 |
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/* palette */ |
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#define LDPR(x) (((x) << 2)) |
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/* framebuffer registers and bits */ |
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#define LDICKR 0x400 |
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#define LDMTR 0x402 |
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/* see sh7760fb.h for LDMTR bits */ |
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#define LDDFR 0x404 |
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#define LDDFR_PABD (1 << 8) |
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#define LDDFR_COLOR_MASK 0x7F |
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#define LDSMR 0x406 |
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#define LDSMR_ROT (1 << 13) |
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#define LDSARU 0x408 |
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#define LDSARL 0x40c |
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#define LDLAOR 0x410 |
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#define LDPALCR 0x412 |
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#define LDPALCR_PALS (1 << 4) |
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#define LDPALCR_PALEN (1 << 0) |
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#define LDHCNR 0x414 |
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#define LDHSYNR 0x416 |
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#define LDVDLNR 0x418 |
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#define LDVTLNR 0x41a |
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#define LDVSYNR 0x41c |
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#define LDACLNR 0x41e |
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#define LDINTR 0x420 |
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#define LDPMMR 0x424 |
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#define LDPSPR 0x426 |
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#define LDCNTR 0x428 |
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#define LDCNTR_DON (1 << 0) |
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#define LDCNTR_DON2 (1 << 4) |
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#ifdef CONFIG_CPU_SUBTYPE_SH7763 |
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# define LDLIRNR 0x440 |
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/* LDINTR bit */ |
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# define LDINTR_MINTEN (1 << 15) |
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# define LDINTR_FINTEN (1 << 14) |
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# define LDINTR_VSINTEN (1 << 13) |
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# define LDINTR_VEINTEN (1 << 12) |
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# define LDINTR_MINTS (1 << 11) |
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# define LDINTR_FINTS (1 << 10) |
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# define LDINTR_VSINTS (1 << 9) |
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# define LDINTR_VEINTS (1 << 8) |
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# define VINT_START (LDINTR_VSINTEN) |
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# define VINT_CHECK (LDINTR_VSINTS) |
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#else |
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/* LDINTR bit */ |
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# define LDINTR_VINTSEL (1 << 12) |
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# define LDINTR_VINTE (1 << 8) |
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# define LDINTR_VINTS (1 << 0) |
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# define VINT_START (LDINTR_VINTSEL) |
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# define VINT_CHECK (LDINTR_VINTS) |
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#endif |
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/* HSYNC polarity inversion */ |
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#define LDMTR_FLMPOL (1 << 15) |
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/* VSYNC polarity inversion */ |
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#define LDMTR_CL1POL (1 << 14) |
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/* DISPLAY-ENABLE polarity inversion */ |
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#define LDMTR_DISPEN_LOWACT (1 << 13) |
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/* DISPLAY DATA BUS polarity inversion */ |
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#define LDMTR_DPOL_LOWACT (1 << 12) |
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/* AC modulation signal enable */ |
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#define LDMTR_MCNT (1 << 10) |
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/* Disable output of HSYNC during VSYNC period */ |
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#define LDMTR_CL1CNT (1 << 9) |
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/* Disable output of VSYNC during VSYNC period */ |
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#define LDMTR_CL2CNT (1 << 8) |
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/* Display types supported by the LCDC */ |
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#define LDMTR_STN_MONO_4 0x00 |
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#define LDMTR_STN_MONO_8 0x01 |
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#define LDMTR_STN_COLOR_4 0x08 |
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#define LDMTR_STN_COLOR_8 0x09 |
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#define LDMTR_STN_COLOR_12 0x0A |
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#define LDMTR_STN_COLOR_16 0x0B |
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#define LDMTR_DSTN_MONO_8 0x11 |
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#define LDMTR_DSTN_MONO_16 0x13 |
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#define LDMTR_DSTN_COLOR_8 0x19 |
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#define LDMTR_DSTN_COLOR_12 0x1A |
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#define LDMTR_DSTN_COLOR_16 0x1B |
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#define LDMTR_TFT_COLOR_16 0x2B |
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/* framebuffer color layout */ |
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#define LDDFR_1BPP_MONO 0x00 |
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#define LDDFR_2BPP_MONO 0x01 |
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#define LDDFR_4BPP_MONO 0x02 |
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#define LDDFR_6BPP_MONO 0x04 |
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#define LDDFR_4BPP 0x0A |
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#define LDDFR_8BPP 0x0C |
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#define LDDFR_16BPP_RGB555 0x1D |
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#define LDDFR_16BPP_RGB565 0x2D |
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/* LCDC Pixclock sources */ |
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#define LCDC_CLKSRC_BUSCLOCK 0 |
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#define LCDC_CLKSRC_PERIPHERAL 1 |
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#define LCDC_CLKSRC_EXTERNAL 2 |
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#define LDICKR_CLKSRC(x) \ |
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(((x) & 3) << 12) |
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/* LCDC pixclock input divider. Set to 1 at a minimum! */ |
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#define LDICKR_CLKDIV(x) \ |
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((x) & 0x1f) |
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struct sh7760fb_platdata { |
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/* Set this member to a valid fb_videmode for the display you |
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* wish to use. The following members must be initialized: |
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* xres, yres, hsync_len, vsync_len, sync, |
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* {left,right,upper,lower}_margin. |
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* The driver uses the above members to calculate register values |
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* and memory requirements. Other members are ignored but may |
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* be used by other framebuffer layer components. |
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*/ |
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struct fb_videomode *def_mode; |
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/* LDMTR includes display type and signal polarity. The |
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* HSYNC/VSYNC polarities are derived from the fb_var_screeninfo |
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* data above; however the polarities of the following signals |
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* must be encoded in the ldmtr member: |
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* Display Enable signal (default high-active) DISPEN_LOWACT |
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* Display Data signals (default high-active) DPOL_LOWACT |
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* AC Modulation signal (default off) MCNT |
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* Hsync-During-Vsync suppression (default off) CL1CNT |
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* Vsync-during-vsync suppression (default off) CL2CNT |
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* NOTE: also set a display type! |
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* (one of LDMTR_{STN,DSTN,TFT}_{MONO,COLOR}_{4,8,12,16}) |
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*/ |
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u16 ldmtr; |
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/* LDDFR controls framebuffer image format (depth, organization) |
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* Use ONE of the LDDFR_?BPP_* macros! |
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*/ |
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u16 lddfr; |
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/* LDPMMR and LDPSPR control the timing of the power signals |
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* for the display. Please read the SH7760 Hardware Manual, |
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* Chapters 30.3.17, 30.3.18 and 30.4.6! |
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*/ |
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u16 ldpmmr; |
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u16 ldpspr; |
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/* LDACLNR contains the line numbers after which the AC modulation |
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* signal is to toggle. Set to ZERO for TFTs or displays which |
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* do not need it. (Chapter 30.3.15 in SH7760 Hardware Manual). |
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*/ |
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u16 ldaclnr; |
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/* LDICKR contains information on pixelclock source and config. |
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* Please use the LDICKR_CLKSRC() and LDICKR_CLKDIV() macros. |
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* minimal value for CLKDIV() must be 1!. |
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*/ |
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u16 ldickr; |
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/* set this member to 1 if you wish to use the LCDC's hardware |
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* rotation function. This is limited to displays <= 320x200 |
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* pixels resolution! |
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*/ |
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int rotate; /* set to 1 to rotate 90 CCW */ |
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/* set this to 1 to suppress vsync irq use. */ |
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int novsync; |
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/* blanking hook for platform. Set this if your platform can do |
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* more than the LCDC in terms of blanking (e.g. disable clock |
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* generator / backlight power supply / etc. |
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*/ |
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void (*blank) (int); |
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}; |
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#endif /* _ASM_SH_SH7760FB_H */
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