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81 lines
1.8 KiB
81 lines
1.8 KiB
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) |
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%YAML 1.2 |
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--- |
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$id: "http://devicetree.org/schemas/mailbox/st,stm32-ipcc.yaml#" |
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$schema: "http://devicetree.org/meta-schemas/core.yaml#" |
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title: STMicroelectronics STM32 IPC controller bindings |
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description: |
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The IPCC block provides a non blocking signaling mechanism to post and |
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retrieve messages in an atomic way between two processors. |
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It provides the signaling for N bidirectionnal channels. The number of |
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channels (N) can be read from a dedicated register. |
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maintainers: |
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- Fabien Dessenne <[email protected]> |
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- Arnaud Pouliquen <[email protected]> |
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properties: |
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compatible: |
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const: st,stm32mp1-ipcc |
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reg: |
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maxItems: 1 |
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clocks: |
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maxItems: 1 |
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interrupts: |
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items: |
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- description: rx channel occupied |
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- description: tx channel free |
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- description: wakeup source |
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minItems: 2 |
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interrupt-names: |
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items: |
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- const: rx |
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- const: tx |
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- const: wakeup |
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minItems: 2 |
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wakeup-source: true |
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"#mbox-cells": |
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const: 1 |
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st,proc-id: |
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description: Processor id using the mailbox (0 or 1) |
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$ref: /schemas/types.yaml#/definitions/uint32 |
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enum: [0, 1] |
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required: |
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- compatible |
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- reg |
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- st,proc-id |
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- clocks |
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- interrupt-names |
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- "#mbox-cells" |
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- interrupts |
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additionalProperties: false |
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examples: |
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- | |
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#include <dt-bindings/interrupt-controller/arm-gic.h> |
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#include <dt-bindings/clock/stm32mp1-clks.h> |
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ipcc: mailbox@4c001000 { |
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compatible = "st,stm32mp1-ipcc"; |
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#mbox-cells = <1>; |
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reg = <0x4c001000 0x400>; |
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st,proc-id = <0>; |
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interrupts-extended = <&intc GIC_SPI 100 IRQ_TYPE_NONE>, |
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<&intc GIC_SPI 101 IRQ_TYPE_NONE>, |
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<&aiec 62 1>; |
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interrupt-names = "rx", "tx", "wakeup"; |
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clocks = <&rcc_clk IPCC>; |
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wakeup-source; |
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}; |
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...
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