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59 lines
2.2 KiB
59 lines
2.2 KiB
Broadcom FlexRM Ring Manager |
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============================ |
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The Broadcom FlexRM ring manager provides a set of rings which can be |
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used to submit work to offload engines. An SoC may have multiple FlexRM |
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hardware blocks. There is one device tree entry per FlexRM block. The |
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FlexRM driver will create a mailbox-controller instance for given FlexRM |
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hardware block where each mailbox channel is a separate FlexRM ring. |
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Required properties: |
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-------------------- |
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- compatible: Should be "brcm,iproc-flexrm-mbox" |
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- reg: Specifies base physical address and size of the FlexRM |
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ring registers |
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- msi-parent: Phandles (and potential Device IDs) to MSI controllers |
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The FlexRM engine will send MSIs (instead of wired |
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interrupts) to CPU. There is one MSI for each FlexRM ring. |
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Refer devicetree/bindings/interrupt-controller/msi.txt |
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- #mbox-cells: Specifies the number of cells needed to encode a mailbox |
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channel. This should be 3. |
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The 1st cell is the mailbox channel number. |
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The 2nd cell contains MSI completion threshold. This is the |
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number of completion messages for which FlexRM will inject |
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one MSI interrupt to CPU. |
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The 3nd cell contains MSI timer value representing time for |
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which FlexRM will wait to accumulate N completion messages |
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where N is the value specified by 2nd cell above. If FlexRM |
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does not get required number of completion messages in time |
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specified by this cell then it will inject one MSI interrupt |
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to CPU provided atleast one completion message is available. |
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Optional properties: |
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-------------------- |
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- dma-coherent: Present if DMA operations made by the FlexRM engine (such |
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as DMA descriptor access, access to buffers pointed by DMA |
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descriptors and read/write pointer updates to DDR) are |
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cache coherent with the CPU. |
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Example: |
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-------- |
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crypto_mbox: mbox@67000000 { |
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compatible = "brcm,iproc-flexrm-mbox"; |
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reg = <0x67000000 0x200000>; |
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msi-parent = <&gic_its 0x7f00>; |
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#mbox-cells = <3>; |
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}; |
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crypto@672c0000 { |
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compatible = "brcm,spu2-v2-crypto"; |
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reg = <0x672c0000 0x1000>; |
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mboxes = <&crypto_mbox 0 0x1 0xffff>, |
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<&crypto_mbox 1 0x1 0xffff>, |
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<&crypto_mbox 16 0x1 0xffff>, |
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<&crypto_mbox 17 0x1 0xffff>, |
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<&crypto_mbox 30 0x1 0xffff>, |
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<&crypto_mbox 31 0x1 0xffff>; |
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};
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