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Changes included (and more): 1. Dynamic RAM merge 2. Real-time page scan and allocation 3. Cache compression 4. Real-time IRQ checks 5. Dynamic I/O allocation for Java heap 6. Java page migration 7. Contiguous memory allocation 8. Idle pages tracking 9. Per CPU RAM usage tracking 10. ARM NEON scalar multiplication library 11. NEON/ARMv8 crypto extensions 12. NEON SHA, Blake, RIPEMD crypto extensions 13. Parallel NEON crypto engine for multi-algo based CPU stress reduction
60 lines
1.2 KiB
YAML
60 lines
1.2 KiB
YAML
# SPDX-License-Identifier: GPL-2.0
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/dma/sifive,fu540-c000-pdma.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: SiFive Unleashed Rev C000 Platform DMA
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maintainers:
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- Green Wan <green.wan@sifive.com>
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- Palmer Debbelt <palmer@sifive.com>
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- Paul Walmsley <paul.walmsley@sifive.com>
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description: |
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Platform DMA is a DMA engine of SiFive Unleashed. It supports 4
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channels. Each channel has 2 interrupts. One is for DMA done and
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the other is for DME error.
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In different SoC, DMA could be attached to different IRQ line.
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DT file need to be changed to meet the difference. For technical
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doc,
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https://static.dev.sifive.com/FU540-C000-v1.0.pdf
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allOf:
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- $ref: "dma-controller.yaml#"
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properties:
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compatible:
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items:
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- const: sifive,fu540-c000-pdma
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reg:
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maxItems: 1
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interrupts:
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minItems: 1
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maxItems: 8
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'#dma-cells':
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const: 1
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required:
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- compatible
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- reg
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- interrupts
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unevaluatedProperties: false
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examples:
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- |
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dma-controller@3000000 {
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compatible = "sifive,fu540-c000-pdma";
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reg = <0x3000000 0x8000>;
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interrupts = <23>, <24>, <25>, <26>, <27>, <28>, <29>, <30>;
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#dma-cells = <1>;
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};
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...
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