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711 lines
22 KiB
711 lines
22 KiB
/* SPDX-License-Identifier: GPL-2.0 */ |
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#ifndef __LINUX_UHCI_HCD_H |
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#define __LINUX_UHCI_HCD_H |
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#include <linux/list.h> |
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#include <linux/usb.h> |
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#include <linux/clk.h> |
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#define usb_packetid(pipe) (usb_pipein(pipe) ? USB_PID_IN : USB_PID_OUT) |
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#define PIPE_DEVEP_MASK 0x0007ff00 |
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/* |
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* Universal Host Controller Interface data structures and defines |
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*/ |
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/* Command register */ |
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#define USBCMD 0 |
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#define USBCMD_RS 0x0001 /* Run/Stop */ |
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#define USBCMD_HCRESET 0x0002 /* Host reset */ |
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#define USBCMD_GRESET 0x0004 /* Global reset */ |
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#define USBCMD_EGSM 0x0008 /* Global Suspend Mode */ |
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#define USBCMD_FGR 0x0010 /* Force Global Resume */ |
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#define USBCMD_SWDBG 0x0020 /* SW Debug mode */ |
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#define USBCMD_CF 0x0040 /* Config Flag (sw only) */ |
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#define USBCMD_MAXP 0x0080 /* Max Packet (0 = 32, 1 = 64) */ |
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/* Status register */ |
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#define USBSTS 2 |
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#define USBSTS_USBINT 0x0001 /* Interrupt due to IOC */ |
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#define USBSTS_ERROR 0x0002 /* Interrupt due to error */ |
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#define USBSTS_RD 0x0004 /* Resume Detect */ |
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#define USBSTS_HSE 0x0008 /* Host System Error: PCI problems */ |
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#define USBSTS_HCPE 0x0010 /* Host Controller Process Error: |
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* the schedule is buggy */ |
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#define USBSTS_HCH 0x0020 /* HC Halted */ |
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/* Interrupt enable register */ |
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#define USBINTR 4 |
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#define USBINTR_TIMEOUT 0x0001 /* Timeout/CRC error enable */ |
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#define USBINTR_RESUME 0x0002 /* Resume interrupt enable */ |
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#define USBINTR_IOC 0x0004 /* Interrupt On Complete enable */ |
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#define USBINTR_SP 0x0008 /* Short packet interrupt enable */ |
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#define USBFRNUM 6 |
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#define USBFLBASEADD 8 |
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#define USBSOF 12 |
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#define USBSOF_DEFAULT 64 /* Frame length is exactly 1 ms */ |
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/* USB port status and control registers */ |
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#define USBPORTSC1 16 |
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#define USBPORTSC2 18 |
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#define USBPORTSC3 20 |
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#define USBPORTSC4 22 |
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#define USBPORTSC_CCS 0x0001 /* Current Connect Status |
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* ("device present") */ |
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#define USBPORTSC_CSC 0x0002 /* Connect Status Change */ |
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#define USBPORTSC_PE 0x0004 /* Port Enable */ |
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#define USBPORTSC_PEC 0x0008 /* Port Enable Change */ |
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#define USBPORTSC_DPLUS 0x0010 /* D+ high (line status) */ |
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#define USBPORTSC_DMINUS 0x0020 /* D- high (line status) */ |
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#define USBPORTSC_RD 0x0040 /* Resume Detect */ |
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#define USBPORTSC_RES1 0x0080 /* reserved, always 1 */ |
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#define USBPORTSC_LSDA 0x0100 /* Low Speed Device Attached */ |
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#define USBPORTSC_PR 0x0200 /* Port Reset */ |
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/* OC and OCC from Intel 430TX and later (not UHCI 1.1d spec) */ |
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#define USBPORTSC_OC 0x0400 /* Over Current condition */ |
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#define USBPORTSC_OCC 0x0800 /* Over Current Change R/WC */ |
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#define USBPORTSC_SUSP 0x1000 /* Suspend */ |
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#define USBPORTSC_RES2 0x2000 /* reserved, write zeroes */ |
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#define USBPORTSC_RES3 0x4000 /* reserved, write zeroes */ |
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#define USBPORTSC_RES4 0x8000 /* reserved, write zeroes */ |
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/* PCI legacy support register */ |
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#define USBLEGSUP 0xc0 |
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#define USBLEGSUP_DEFAULT 0x2000 /* only PIRQ enable set */ |
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#define USBLEGSUP_RWC 0x8f00 /* the R/WC bits */ |
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#define USBLEGSUP_RO 0x5040 /* R/O and reserved bits */ |
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/* PCI Intel-specific resume-enable register */ |
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#define USBRES_INTEL 0xc4 |
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#define USBPORT1EN 0x01 |
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#define USBPORT2EN 0x02 |
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#define UHCI_PTR_BITS(uhci) cpu_to_hc32((uhci), 0x000F) |
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#define UHCI_PTR_TERM(uhci) cpu_to_hc32((uhci), 0x0001) |
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#define UHCI_PTR_QH(uhci) cpu_to_hc32((uhci), 0x0002) |
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#define UHCI_PTR_DEPTH(uhci) cpu_to_hc32((uhci), 0x0004) |
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#define UHCI_PTR_BREADTH(uhci) cpu_to_hc32((uhci), 0x0000) |
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#define UHCI_NUMFRAMES 1024 /* in the frame list [array] */ |
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#define UHCI_MAX_SOF_NUMBER 2047 /* in an SOF packet */ |
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#define CAN_SCHEDULE_FRAMES 1000 /* how far in the future frames |
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* can be scheduled */ |
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#define MAX_PHASE 32 /* Periodic scheduling length */ |
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/* When no queues need Full-Speed Bandwidth Reclamation, |
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* delay this long before turning FSBR off */ |
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#define FSBR_OFF_DELAY msecs_to_jiffies(10) |
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/* If a queue hasn't advanced after this much time, assume it is stuck */ |
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#define QH_WAIT_TIMEOUT msecs_to_jiffies(200) |
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/* |
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* __hc32 and __hc16 are "Host Controller" types, they may be equivalent to |
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* __leXX (normally) or __beXX (given UHCI_BIG_ENDIAN_DESC), depending on |
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* the host controller implementation. |
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* |
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* To facilitate the strongest possible byte-order checking from "sparse" |
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* and so on, we use __leXX unless that's not practical. |
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*/ |
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#ifdef CONFIG_USB_UHCI_BIG_ENDIAN_DESC |
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typedef __u32 __bitwise __hc32; |
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typedef __u16 __bitwise __hc16; |
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#else |
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#define __hc32 __le32 |
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#define __hc16 __le16 |
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#endif |
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/* |
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* Queue Headers |
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*/ |
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/* |
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* One role of a QH is to hold a queue of TDs for some endpoint. One QH goes |
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* with each endpoint, and qh->element (updated by the HC) is either: |
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* - the next unprocessed TD in the endpoint's queue, or |
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* - UHCI_PTR_TERM (when there's no more traffic for this endpoint). |
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* |
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* The other role of a QH is to serve as a "skeleton" framelist entry, so we |
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* can easily splice a QH for some endpoint into the schedule at the right |
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* place. Then qh->element is UHCI_PTR_TERM. |
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* |
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* In the schedule, qh->link maintains a list of QHs seen by the HC: |
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* skel1 --> ep1-qh --> ep2-qh --> ... --> skel2 --> ... |
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* |
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* qh->node is the software equivalent of qh->link. The differences |
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* are that the software list is doubly-linked and QHs in the UNLINKING |
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* state are on the software list but not the hardware schedule. |
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* |
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* For bookkeeping purposes we maintain QHs even for Isochronous endpoints, |
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* but they never get added to the hardware schedule. |
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*/ |
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#define QH_STATE_IDLE 1 /* QH is not being used */ |
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#define QH_STATE_UNLINKING 2 /* QH has been removed from the |
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* schedule but the hardware may |
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* still be using it */ |
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#define QH_STATE_ACTIVE 3 /* QH is on the schedule */ |
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struct uhci_qh { |
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/* Hardware fields */ |
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__hc32 link; /* Next QH in the schedule */ |
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__hc32 element; /* Queue element (TD) pointer */ |
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/* Software fields */ |
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dma_addr_t dma_handle; |
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struct list_head node; /* Node in the list of QHs */ |
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struct usb_host_endpoint *hep; /* Endpoint information */ |
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struct usb_device *udev; |
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struct list_head queue; /* Queue of urbps for this QH */ |
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struct uhci_td *dummy_td; /* Dummy TD to end the queue */ |
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struct uhci_td *post_td; /* Last TD completed */ |
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struct usb_iso_packet_descriptor *iso_packet_desc; |
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/* Next urb->iso_frame_desc entry */ |
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unsigned long advance_jiffies; /* Time of last queue advance */ |
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unsigned int unlink_frame; /* When the QH was unlinked */ |
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unsigned int period; /* For Interrupt and Isochronous QHs */ |
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short phase; /* Between 0 and period-1 */ |
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short load; /* Periodic time requirement, in us */ |
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unsigned int iso_frame; /* Frame # for iso_packet_desc */ |
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int state; /* QH_STATE_xxx; see above */ |
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int type; /* Queue type (control, bulk, etc) */ |
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int skel; /* Skeleton queue number */ |
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unsigned int initial_toggle:1; /* Endpoint's current toggle value */ |
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unsigned int needs_fixup:1; /* Must fix the TD toggle values */ |
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unsigned int is_stopped:1; /* Queue was stopped by error/unlink */ |
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unsigned int wait_expired:1; /* QH_WAIT_TIMEOUT has expired */ |
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unsigned int bandwidth_reserved:1; /* Periodic bandwidth has |
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* been allocated */ |
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} __attribute__((aligned(16))); |
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/* |
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* We need a special accessor for the element pointer because it is |
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* subject to asynchronous updates by the controller. |
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*/ |
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#define qh_element(qh) READ_ONCE((qh)->element) |
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#define LINK_TO_QH(uhci, qh) (UHCI_PTR_QH((uhci)) | \ |
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cpu_to_hc32((uhci), (qh)->dma_handle)) |
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/* |
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* Transfer Descriptors |
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*/ |
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/* |
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* for TD <status>: |
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*/ |
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#define TD_CTRL_SPD (1 << 29) /* Short Packet Detect */ |
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#define TD_CTRL_C_ERR_MASK (3 << 27) /* Error Counter bits */ |
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#define TD_CTRL_C_ERR_SHIFT 27 |
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#define TD_CTRL_LS (1 << 26) /* Low Speed Device */ |
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#define TD_CTRL_IOS (1 << 25) /* Isochronous Select */ |
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#define TD_CTRL_IOC (1 << 24) /* Interrupt on Complete */ |
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#define TD_CTRL_ACTIVE (1 << 23) /* TD Active */ |
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#define TD_CTRL_STALLED (1 << 22) /* TD Stalled */ |
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#define TD_CTRL_DBUFERR (1 << 21) /* Data Buffer Error */ |
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#define TD_CTRL_BABBLE (1 << 20) /* Babble Detected */ |
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#define TD_CTRL_NAK (1 << 19) /* NAK Received */ |
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#define TD_CTRL_CRCTIMEO (1 << 18) /* CRC/Time Out Error */ |
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#define TD_CTRL_BITSTUFF (1 << 17) /* Bit Stuff Error */ |
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#define TD_CTRL_ACTLEN_MASK 0x7FF /* actual length, encoded as n - 1 */ |
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#define uhci_maxerr(err) ((err) << TD_CTRL_C_ERR_SHIFT) |
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#define uhci_status_bits(ctrl_sts) ((ctrl_sts) & 0xF60000) |
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#define uhci_actual_length(ctrl_sts) (((ctrl_sts) + 1) & \ |
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TD_CTRL_ACTLEN_MASK) /* 1-based */ |
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/* |
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* for TD <info>: (a.k.a. Token) |
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*/ |
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#define td_token(uhci, td) hc32_to_cpu((uhci), (td)->token) |
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#define TD_TOKEN_DEVADDR_SHIFT 8 |
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#define TD_TOKEN_TOGGLE_SHIFT 19 |
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#define TD_TOKEN_TOGGLE (1 << 19) |
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#define TD_TOKEN_EXPLEN_SHIFT 21 |
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#define TD_TOKEN_EXPLEN_MASK 0x7FF /* expected length, encoded as n-1 */ |
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#define TD_TOKEN_PID_MASK 0xFF |
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#define uhci_explen(len) ((((len) - 1) & TD_TOKEN_EXPLEN_MASK) << \ |
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TD_TOKEN_EXPLEN_SHIFT) |
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#define uhci_expected_length(token) ((((token) >> TD_TOKEN_EXPLEN_SHIFT) + \ |
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1) & TD_TOKEN_EXPLEN_MASK) |
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#define uhci_toggle(token) (((token) >> TD_TOKEN_TOGGLE_SHIFT) & 1) |
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#define uhci_endpoint(token) (((token) >> 15) & 0xf) |
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#define uhci_devaddr(token) (((token) >> TD_TOKEN_DEVADDR_SHIFT) & 0x7f) |
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#define uhci_devep(token) (((token) >> TD_TOKEN_DEVADDR_SHIFT) & 0x7ff) |
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#define uhci_packetid(token) ((token) & TD_TOKEN_PID_MASK) |
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#define uhci_packetout(token) (uhci_packetid(token) != USB_PID_IN) |
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#define uhci_packetin(token) (uhci_packetid(token) == USB_PID_IN) |
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/* |
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* The documentation says "4 words for hardware, 4 words for software". |
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* |
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* That's silly, the hardware doesn't care. The hardware only cares that |
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* the hardware words are 16-byte aligned, and we can have any amount of |
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* sw space after the TD entry. |
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* |
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* td->link points to either another TD (not necessarily for the same urb or |
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* even the same endpoint), or nothing (PTR_TERM), or a QH. |
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*/ |
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struct uhci_td { |
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/* Hardware fields */ |
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__hc32 link; |
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__hc32 status; |
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__hc32 token; |
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__hc32 buffer; |
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/* Software fields */ |
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dma_addr_t dma_handle; |
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struct list_head list; |
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int frame; /* for iso: what frame? */ |
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struct list_head fl_list; |
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} __attribute__((aligned(16))); |
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/* |
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* We need a special accessor for the control/status word because it is |
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* subject to asynchronous updates by the controller. |
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*/ |
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#define td_status(uhci, td) hc32_to_cpu((uhci), \ |
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READ_ONCE((td)->status)) |
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#define LINK_TO_TD(uhci, td) (cpu_to_hc32((uhci), (td)->dma_handle)) |
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/* |
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* Skeleton Queue Headers |
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*/ |
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/* |
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* The UHCI driver uses QHs with Interrupt, Control and Bulk URBs for |
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* automatic queuing. To make it easy to insert entries into the schedule, |
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* we have a skeleton of QHs for each predefined Interrupt latency. |
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* Asynchronous QHs (low-speed control, full-speed control, and bulk) |
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* go onto the period-1 interrupt list, since they all get accessed on |
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* every frame. |
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* |
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* When we want to add a new QH, we add it to the list starting from the |
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* appropriate skeleton QH. For instance, the schedule can look like this: |
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* |
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* skel int128 QH |
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* dev 1 interrupt QH |
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* dev 5 interrupt QH |
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* skel int64 QH |
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* skel int32 QH |
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* ... |
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* skel int1 + async QH |
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* dev 5 low-speed control QH |
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* dev 1 bulk QH |
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* dev 2 bulk QH |
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* |
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* There is a special terminating QH used to keep full-speed bandwidth |
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* reclamation active when no full-speed control or bulk QHs are linked |
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* into the schedule. It has an inactive TD (to work around a PIIX bug, |
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* see the Intel errata) and it points back to itself. |
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* |
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* There's a special skeleton QH for Isochronous QHs which never appears |
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* on the schedule. Isochronous TDs go on the schedule before the |
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* the skeleton QHs. The hardware accesses them directly rather than |
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* through their QH, which is used only for bookkeeping purposes. |
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* While the UHCI spec doesn't forbid the use of QHs for Isochronous, |
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* it doesn't use them either. And the spec says that queues never |
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* advance on an error completion status, which makes them totally |
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* unsuitable for Isochronous transfers. |
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* |
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* There's also a special skeleton QH used for QHs which are in the process |
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* of unlinking and so may still be in use by the hardware. It too never |
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* appears on the schedule. |
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*/ |
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#define UHCI_NUM_SKELQH 11 |
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#define SKEL_UNLINK 0 |
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#define skel_unlink_qh skelqh[SKEL_UNLINK] |
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#define SKEL_ISO 1 |
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#define skel_iso_qh skelqh[SKEL_ISO] |
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/* int128, int64, ..., int1 = 2, 3, ..., 9 */ |
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#define SKEL_INDEX(exponent) (9 - exponent) |
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#define SKEL_ASYNC 9 |
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#define skel_async_qh skelqh[SKEL_ASYNC] |
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#define SKEL_TERM 10 |
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#define skel_term_qh skelqh[SKEL_TERM] |
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/* The following entries refer to sublists of skel_async_qh */ |
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#define SKEL_LS_CONTROL 20 |
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#define SKEL_FS_CONTROL 21 |
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#define SKEL_FSBR SKEL_FS_CONTROL |
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#define SKEL_BULK 22 |
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/* |
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* The UHCI controller and root hub |
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*/ |
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/* |
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* States for the root hub: |
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* |
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* To prevent "bouncing" in the presence of electrical noise, |
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* when there are no devices attached we delay for 1 second in the |
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* RUNNING_NODEVS state before switching to the AUTO_STOPPED state. |
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* |
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* (Note that the AUTO_STOPPED state won't be necessary once the hub |
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* driver learns to autosuspend.) |
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*/ |
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enum uhci_rh_state { |
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/* In the following states the HC must be halted. |
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* These two must come first. */ |
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UHCI_RH_RESET, |
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UHCI_RH_SUSPENDED, |
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UHCI_RH_AUTO_STOPPED, |
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UHCI_RH_RESUMING, |
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/* In this state the HC changes from running to halted, |
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* so it can legally appear either way. */ |
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UHCI_RH_SUSPENDING, |
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/* In the following states it's an error if the HC is halted. |
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* These two must come last. */ |
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UHCI_RH_RUNNING, /* The normal state */ |
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UHCI_RH_RUNNING_NODEVS, /* Running with no devices attached */ |
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}; |
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/* |
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* The full UHCI controller information: |
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*/ |
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struct uhci_hcd { |
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/* Grabbed from PCI */ |
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unsigned long io_addr; |
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/* Used when registers are memory mapped */ |
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void __iomem *regs; |
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struct dma_pool *qh_pool; |
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struct dma_pool *td_pool; |
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struct uhci_td *term_td; /* Terminating TD, see UHCI bug */ |
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struct uhci_qh *skelqh[UHCI_NUM_SKELQH]; /* Skeleton QHs */ |
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struct uhci_qh *next_qh; /* Next QH to scan */ |
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spinlock_t lock; |
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dma_addr_t frame_dma_handle; /* Hardware frame list */ |
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__hc32 *frame; |
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void **frame_cpu; /* CPU's frame list */ |
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enum uhci_rh_state rh_state; |
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unsigned long auto_stop_time; /* When to AUTO_STOP */ |
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unsigned int frame_number; /* As of last check */ |
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unsigned int is_stopped; |
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#define UHCI_IS_STOPPED 9999 /* Larger than a frame # */ |
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unsigned int last_iso_frame; /* Frame of last scan */ |
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unsigned int cur_iso_frame; /* Frame for current scan */ |
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unsigned int scan_in_progress:1; /* Schedule scan is running */ |
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unsigned int need_rescan:1; /* Redo the schedule scan */ |
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unsigned int dead:1; /* Controller has died */ |
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unsigned int RD_enable:1; /* Suspended root hub with |
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Resume-Detect interrupts |
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enabled */ |
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unsigned int is_initialized:1; /* Data structure is usable */ |
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unsigned int fsbr_is_on:1; /* FSBR is turned on */ |
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unsigned int fsbr_is_wanted:1; /* Does any URB want FSBR? */ |
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unsigned int fsbr_expiring:1; /* FSBR is timing out */ |
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struct timer_list fsbr_timer; /* For turning off FBSR */ |
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/* Silicon quirks */ |
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unsigned int oc_low:1; /* OverCurrent bit active low */ |
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unsigned int wait_for_hp:1; /* Wait for HP port reset */ |
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unsigned int big_endian_mmio:1; /* Big endian registers */ |
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unsigned int big_endian_desc:1; /* Big endian descriptors */ |
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unsigned int is_aspeed:1; /* Aspeed impl. workarounds */ |
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/* Support for port suspend/resume/reset */ |
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unsigned long port_c_suspend; /* Bit-arrays of ports */ |
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unsigned long resuming_ports; |
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unsigned long ports_timeout; /* Time to stop signalling */ |
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struct list_head idle_qh_list; /* Where the idle QHs live */ |
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int rh_numports; /* Number of root-hub ports */ |
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wait_queue_head_t waitqh; /* endpoint_disable waiters */ |
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int num_waiting; /* Number of waiters */ |
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int total_load; /* Sum of array values */ |
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short load[MAX_PHASE]; /* Periodic allocations */ |
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struct clk *clk; /* (optional) clock source */ |
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/* Reset host controller */ |
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void (*reset_hc) (struct uhci_hcd *uhci); |
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int (*check_and_reset_hc) (struct uhci_hcd *uhci); |
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/* configure_hc should perform arch specific settings, if needed */ |
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void (*configure_hc) (struct uhci_hcd *uhci); |
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/* Check for broken resume detect interrupts */ |
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int (*resume_detect_interrupts_are_broken) (struct uhci_hcd *uhci); |
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/* Check for broken global suspend */ |
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int (*global_suspend_mode_is_broken) (struct uhci_hcd *uhci); |
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}; |
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/* Convert between a usb_hcd pointer and the corresponding uhci_hcd */ |
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static inline struct uhci_hcd *hcd_to_uhci(struct usb_hcd *hcd) |
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{ |
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return (struct uhci_hcd *) (hcd->hcd_priv); |
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} |
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static inline struct usb_hcd *uhci_to_hcd(struct uhci_hcd *uhci) |
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{ |
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return container_of((void *) uhci, struct usb_hcd, hcd_priv); |
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} |
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#define uhci_dev(u) (uhci_to_hcd(u)->self.controller) |
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|
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/* Utility macro for comparing frame numbers */ |
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#define uhci_frame_before_eq(f1, f2) (0 <= (int) ((f2) - (f1))) |
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/* |
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* Private per-URB data |
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*/ |
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struct urb_priv { |
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struct list_head node; /* Node in the QH's urbp list */ |
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struct urb *urb; |
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struct uhci_qh *qh; /* QH for this URB */ |
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struct list_head td_list; |
|
|
|
unsigned fsbr:1; /* URB wants FSBR */ |
|
}; |
|
|
|
|
|
/* Some special IDs */ |
|
|
|
#define PCI_VENDOR_ID_GENESYS 0x17a0 |
|
#define PCI_DEVICE_ID_GL880S_UHCI 0x8083 |
|
|
|
/* Aspeed SoC needs some quirks */ |
|
static inline bool uhci_is_aspeed(const struct uhci_hcd *uhci) |
|
{ |
|
return IS_ENABLED(CONFIG_USB_UHCI_ASPEED) && uhci->is_aspeed; |
|
} |
|
|
|
/* |
|
* Functions used to access controller registers. The UCHI spec says that host |
|
* controller I/O registers are mapped into PCI I/O space. For non-PCI hosts |
|
* we use memory mapped registers. |
|
*/ |
|
|
|
#ifndef CONFIG_USB_UHCI_SUPPORT_NON_PCI_HC |
|
/* Support PCI only */ |
|
static inline u32 uhci_readl(const struct uhci_hcd *uhci, int reg) |
|
{ |
|
return inl(uhci->io_addr + reg); |
|
} |
|
|
|
static inline void uhci_writel(const struct uhci_hcd *uhci, u32 val, int reg) |
|
{ |
|
outl(val, uhci->io_addr + reg); |
|
} |
|
|
|
static inline u16 uhci_readw(const struct uhci_hcd *uhci, int reg) |
|
{ |
|
return inw(uhci->io_addr + reg); |
|
} |
|
|
|
static inline void uhci_writew(const struct uhci_hcd *uhci, u16 val, int reg) |
|
{ |
|
outw(val, uhci->io_addr + reg); |
|
} |
|
|
|
static inline u8 uhci_readb(const struct uhci_hcd *uhci, int reg) |
|
{ |
|
return inb(uhci->io_addr + reg); |
|
} |
|
|
|
static inline void uhci_writeb(const struct uhci_hcd *uhci, u8 val, int reg) |
|
{ |
|
outb(val, uhci->io_addr + reg); |
|
} |
|
|
|
#else |
|
/* Support non-PCI host controllers */ |
|
#ifdef CONFIG_USB_PCI |
|
/* Support PCI and non-PCI host controllers */ |
|
#define uhci_has_pci_registers(u) ((u)->io_addr != 0) |
|
#else |
|
/* Support non-PCI host controllers only */ |
|
#define uhci_has_pci_registers(u) 0 |
|
#endif |
|
|
|
#ifdef CONFIG_USB_UHCI_BIG_ENDIAN_MMIO |
|
/* Support (non-PCI) big endian host controllers */ |
|
#define uhci_big_endian_mmio(u) ((u)->big_endian_mmio) |
|
#else |
|
#define uhci_big_endian_mmio(u) 0 |
|
#endif |
|
|
|
static inline int uhci_aspeed_reg(unsigned int reg) |
|
{ |
|
switch (reg) { |
|
case USBCMD: |
|
return 00; |
|
case USBSTS: |
|
return 0x04; |
|
case USBINTR: |
|
return 0x08; |
|
case USBFRNUM: |
|
return 0x80; |
|
case USBFLBASEADD: |
|
return 0x0c; |
|
case USBSOF: |
|
return 0x84; |
|
case USBPORTSC1: |
|
return 0x88; |
|
case USBPORTSC2: |
|
return 0x8c; |
|
case USBPORTSC3: |
|
return 0x90; |
|
case USBPORTSC4: |
|
return 0x94; |
|
default: |
|
pr_warn("UHCI: Unsupported register 0x%02x on Aspeed\n", reg); |
|
/* Return an unimplemented register */ |
|
return 0x10; |
|
} |
|
} |
|
|
|
static inline u32 uhci_readl(const struct uhci_hcd *uhci, int reg) |
|
{ |
|
if (uhci_has_pci_registers(uhci)) |
|
return inl(uhci->io_addr + reg); |
|
else if (uhci_is_aspeed(uhci)) |
|
return readl(uhci->regs + uhci_aspeed_reg(reg)); |
|
#ifdef CONFIG_USB_UHCI_BIG_ENDIAN_MMIO |
|
else if (uhci_big_endian_mmio(uhci)) |
|
return readl_be(uhci->regs + reg); |
|
#endif |
|
else |
|
return readl(uhci->regs + reg); |
|
} |
|
|
|
static inline void uhci_writel(const struct uhci_hcd *uhci, u32 val, int reg) |
|
{ |
|
if (uhci_has_pci_registers(uhci)) |
|
outl(val, uhci->io_addr + reg); |
|
else if (uhci_is_aspeed(uhci)) |
|
writel(val, uhci->regs + uhci_aspeed_reg(reg)); |
|
#ifdef CONFIG_USB_UHCI_BIG_ENDIAN_MMIO |
|
else if (uhci_big_endian_mmio(uhci)) |
|
writel_be(val, uhci->regs + reg); |
|
#endif |
|
else |
|
writel(val, uhci->regs + reg); |
|
} |
|
|
|
static inline u16 uhci_readw(const struct uhci_hcd *uhci, int reg) |
|
{ |
|
if (uhci_has_pci_registers(uhci)) |
|
return inw(uhci->io_addr + reg); |
|
else if (uhci_is_aspeed(uhci)) |
|
return readl(uhci->regs + uhci_aspeed_reg(reg)); |
|
#ifdef CONFIG_USB_UHCI_BIG_ENDIAN_MMIO |
|
else if (uhci_big_endian_mmio(uhci)) |
|
return readw_be(uhci->regs + reg); |
|
#endif |
|
else |
|
return readw(uhci->regs + reg); |
|
} |
|
|
|
static inline void uhci_writew(const struct uhci_hcd *uhci, u16 val, int reg) |
|
{ |
|
if (uhci_has_pci_registers(uhci)) |
|
outw(val, uhci->io_addr + reg); |
|
else if (uhci_is_aspeed(uhci)) |
|
writel(val, uhci->regs + uhci_aspeed_reg(reg)); |
|
#ifdef CONFIG_USB_UHCI_BIG_ENDIAN_MMIO |
|
else if (uhci_big_endian_mmio(uhci)) |
|
writew_be(val, uhci->regs + reg); |
|
#endif |
|
else |
|
writew(val, uhci->regs + reg); |
|
} |
|
|
|
static inline u8 uhci_readb(const struct uhci_hcd *uhci, int reg) |
|
{ |
|
if (uhci_has_pci_registers(uhci)) |
|
return inb(uhci->io_addr + reg); |
|
else if (uhci_is_aspeed(uhci)) |
|
return readl(uhci->regs + uhci_aspeed_reg(reg)); |
|
#ifdef CONFIG_USB_UHCI_BIG_ENDIAN_MMIO |
|
else if (uhci_big_endian_mmio(uhci)) |
|
return readb_be(uhci->regs + reg); |
|
#endif |
|
else |
|
return readb(uhci->regs + reg); |
|
} |
|
|
|
static inline void uhci_writeb(const struct uhci_hcd *uhci, u8 val, int reg) |
|
{ |
|
if (uhci_has_pci_registers(uhci)) |
|
outb(val, uhci->io_addr + reg); |
|
else if (uhci_is_aspeed(uhci)) |
|
writel(val, uhci->regs + uhci_aspeed_reg(reg)); |
|
#ifdef CONFIG_USB_UHCI_BIG_ENDIAN_MMIO |
|
else if (uhci_big_endian_mmio(uhci)) |
|
writeb_be(val, uhci->regs + reg); |
|
#endif |
|
else |
|
writeb(val, uhci->regs + reg); |
|
} |
|
#endif /* CONFIG_USB_UHCI_SUPPORT_NON_PCI_HC */ |
|
|
|
/* |
|
* The GRLIB GRUSBHC controller can use big endian format for its descriptors. |
|
* |
|
* UHCI controllers accessed through PCI work normally (little-endian |
|
* everywhere), so we don't bother supporting a BE-only mode. |
|
*/ |
|
#ifdef CONFIG_USB_UHCI_BIG_ENDIAN_DESC |
|
#define uhci_big_endian_desc(u) ((u)->big_endian_desc) |
|
|
|
/* cpu to uhci */ |
|
static inline __hc32 cpu_to_hc32(const struct uhci_hcd *uhci, const u32 x) |
|
{ |
|
return uhci_big_endian_desc(uhci) |
|
? (__force __hc32)cpu_to_be32(x) |
|
: (__force __hc32)cpu_to_le32(x); |
|
} |
|
|
|
/* uhci to cpu */ |
|
static inline u32 hc32_to_cpu(const struct uhci_hcd *uhci, const __hc32 x) |
|
{ |
|
return uhci_big_endian_desc(uhci) |
|
? be32_to_cpu((__force __be32)x) |
|
: le32_to_cpu((__force __le32)x); |
|
} |
|
|
|
#else |
|
/* cpu to uhci */ |
|
static inline __hc32 cpu_to_hc32(const struct uhci_hcd *uhci, const u32 x) |
|
{ |
|
return cpu_to_le32(x); |
|
} |
|
|
|
/* uhci to cpu */ |
|
static inline u32 hc32_to_cpu(const struct uhci_hcd *uhci, const __hc32 x) |
|
{ |
|
return le32_to_cpu(x); |
|
} |
|
#endif |
|
|
|
#endif
|
|
|