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443 lines
12 KiB
443 lines
12 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* driver for Microsemi PQI-based storage controllers |
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* Copyright (c) 2019-2020 Microchip Technology Inc. and its subsidiaries |
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* Copyright (c) 2016-2018 Microsemi Corporation |
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* Copyright (c) 2016 PMC-Sierra, Inc. |
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* |
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* Questions/Comments/Bugfixes to [email protected] |
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* |
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*/ |
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#include <linux/module.h> |
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#include <linux/kernel.h> |
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#include <linux/delay.h> |
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#include <linux/pci.h> |
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#include <scsi/scsi_device.h> |
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#include <asm/unaligned.h> |
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#include "smartpqi.h" |
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#include "smartpqi_sis.h" |
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/* legacy SIS interface commands */ |
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#define SIS_CMD_GET_ADAPTER_PROPERTIES 0x19 |
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#define SIS_CMD_INIT_BASE_STRUCT_ADDRESS 0x1b |
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#define SIS_CMD_GET_PQI_CAPABILITIES 0x3000 |
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/* for submission of legacy SIS commands */ |
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#define SIS_REENABLE_SIS_MODE 0x1 |
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#define SIS_ENABLE_MSIX 0x40 |
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#define SIS_ENABLE_INTX 0x80 |
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#define SIS_SOFT_RESET 0x100 |
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#define SIS_CMD_READY 0x200 |
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#define SIS_TRIGGER_SHUTDOWN 0x800000 |
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#define SIS_PQI_RESET_QUIESCE 0x1000000 |
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#define SIS_CMD_COMPLETE 0x1000 |
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#define SIS_CLEAR_CTRL_TO_HOST_DOORBELL 0x1000 |
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#define SIS_CMD_STATUS_SUCCESS 0x1 |
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#define SIS_CMD_COMPLETE_TIMEOUT_SECS 30 |
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#define SIS_CMD_COMPLETE_POLL_INTERVAL_MSECS 10 |
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/* used with SIS_CMD_GET_ADAPTER_PROPERTIES command */ |
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#define SIS_EXTENDED_PROPERTIES_SUPPORTED 0x800000 |
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#define SIS_SMARTARRAY_FEATURES_SUPPORTED 0x2 |
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#define SIS_PQI_MODE_SUPPORTED 0x4 |
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#define SIS_PQI_RESET_QUIESCE_SUPPORTED 0x8 |
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#define SIS_REQUIRED_EXTENDED_PROPERTIES \ |
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(SIS_SMARTARRAY_FEATURES_SUPPORTED | SIS_PQI_MODE_SUPPORTED) |
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/* used with SIS_CMD_INIT_BASE_STRUCT_ADDRESS command */ |
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#define SIS_BASE_STRUCT_REVISION 9 |
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#define SIS_BASE_STRUCT_ALIGNMENT 16 |
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#define SIS_CTRL_KERNEL_UP 0x80 |
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#define SIS_CTRL_KERNEL_PANIC 0x100 |
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#define SIS_CTRL_READY_TIMEOUT_SECS 180 |
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#define SIS_CTRL_READY_RESUME_TIMEOUT_SECS 90 |
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#define SIS_CTRL_READY_POLL_INTERVAL_MSECS 10 |
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#pragma pack(1) |
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/* for use with SIS_CMD_INIT_BASE_STRUCT_ADDRESS command */ |
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struct sis_base_struct { |
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__le32 revision; /* revision of this structure */ |
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__le32 flags; /* reserved */ |
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__le32 error_buffer_paddr_low; /* lower 32 bits of physical memory */ |
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/* buffer for PQI error response */ |
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/* data */ |
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__le32 error_buffer_paddr_high; /* upper 32 bits of physical */ |
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/* memory buffer for PQI */ |
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/* error response data */ |
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__le32 error_buffer_element_length; /* length of each PQI error */ |
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/* response buffer element */ |
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/* in bytes */ |
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__le32 error_buffer_num_elements; /* total number of PQI error */ |
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/* response buffers available */ |
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}; |
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#pragma pack() |
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static int sis_wait_for_ctrl_ready_with_timeout(struct pqi_ctrl_info *ctrl_info, |
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unsigned int timeout_secs) |
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{ |
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unsigned long timeout; |
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u32 status; |
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timeout = (timeout_secs * PQI_HZ) + jiffies; |
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while (1) { |
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status = readl(&ctrl_info->registers->sis_firmware_status); |
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if (status != ~0) { |
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if (status & SIS_CTRL_KERNEL_PANIC) { |
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dev_err(&ctrl_info->pci_dev->dev, |
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"controller is offline: status code 0x%x\n", |
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readl( |
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&ctrl_info->registers->sis_mailbox[7])); |
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return -ENODEV; |
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} |
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if (status & SIS_CTRL_KERNEL_UP) |
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break; |
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} |
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if (time_after(jiffies, timeout)) { |
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dev_err(&ctrl_info->pci_dev->dev, |
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"controller not ready after %u seconds\n", |
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timeout_secs); |
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return -ETIMEDOUT; |
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} |
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msleep(SIS_CTRL_READY_POLL_INTERVAL_MSECS); |
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} |
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return 0; |
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} |
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int sis_wait_for_ctrl_ready(struct pqi_ctrl_info *ctrl_info) |
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{ |
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return sis_wait_for_ctrl_ready_with_timeout(ctrl_info, |
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SIS_CTRL_READY_TIMEOUT_SECS); |
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} |
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int sis_wait_for_ctrl_ready_resume(struct pqi_ctrl_info *ctrl_info) |
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{ |
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return sis_wait_for_ctrl_ready_with_timeout(ctrl_info, |
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SIS_CTRL_READY_RESUME_TIMEOUT_SECS); |
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} |
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bool sis_is_firmware_running(struct pqi_ctrl_info *ctrl_info) |
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{ |
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bool running; |
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u32 status; |
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status = readl(&ctrl_info->registers->sis_firmware_status); |
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if (status & SIS_CTRL_KERNEL_PANIC) |
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running = false; |
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else |
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running = true; |
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if (!running) |
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dev_err(&ctrl_info->pci_dev->dev, |
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"controller is offline: status code 0x%x\n", |
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readl(&ctrl_info->registers->sis_mailbox[7])); |
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return running; |
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} |
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bool sis_is_kernel_up(struct pqi_ctrl_info *ctrl_info) |
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{ |
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return readl(&ctrl_info->registers->sis_firmware_status) & |
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SIS_CTRL_KERNEL_UP; |
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} |
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u32 sis_get_product_id(struct pqi_ctrl_info *ctrl_info) |
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{ |
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return readl(&ctrl_info->registers->sis_product_identifier); |
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} |
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/* used for passing command parameters/results when issuing SIS commands */ |
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struct sis_sync_cmd_params { |
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u32 mailbox[6]; /* mailboxes 0-5 */ |
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}; |
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static int sis_send_sync_cmd(struct pqi_ctrl_info *ctrl_info, |
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u32 cmd, struct sis_sync_cmd_params *params) |
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{ |
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struct pqi_ctrl_registers __iomem *registers; |
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unsigned int i; |
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unsigned long timeout; |
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u32 doorbell; |
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u32 cmd_status; |
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registers = ctrl_info->registers; |
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/* Write the command to mailbox 0. */ |
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writel(cmd, ®isters->sis_mailbox[0]); |
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/* |
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* Write the command parameters to mailboxes 1-4 (mailbox 5 is not used |
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* when sending a command to the controller). |
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*/ |
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for (i = 1; i <= 4; i++) |
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writel(params->mailbox[i], ®isters->sis_mailbox[i]); |
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/* Clear the command doorbell. */ |
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writel(SIS_CLEAR_CTRL_TO_HOST_DOORBELL, |
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®isters->sis_ctrl_to_host_doorbell_clear); |
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/* Disable doorbell interrupts by masking all interrupts. */ |
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writel(~0, ®isters->sis_interrupt_mask); |
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/* |
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* Force the completion of the interrupt mask register write before |
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* submitting the command. |
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*/ |
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readl(®isters->sis_interrupt_mask); |
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/* Submit the command to the controller. */ |
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writel(SIS_CMD_READY, ®isters->sis_host_to_ctrl_doorbell); |
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/* |
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* Poll for command completion. Note that the call to msleep() is at |
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* the top of the loop in order to give the controller time to start |
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* processing the command before we start polling. |
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*/ |
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timeout = (SIS_CMD_COMPLETE_TIMEOUT_SECS * PQI_HZ) + jiffies; |
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while (1) { |
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msleep(SIS_CMD_COMPLETE_POLL_INTERVAL_MSECS); |
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doorbell = readl(®isters->sis_ctrl_to_host_doorbell); |
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if (doorbell & SIS_CMD_COMPLETE) |
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break; |
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if (time_after(jiffies, timeout)) |
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return -ETIMEDOUT; |
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} |
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/* Read the command status from mailbox 0. */ |
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cmd_status = readl(®isters->sis_mailbox[0]); |
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if (cmd_status != SIS_CMD_STATUS_SUCCESS) { |
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dev_err(&ctrl_info->pci_dev->dev, |
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"SIS command failed for command 0x%x: status = 0x%x\n", |
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cmd, cmd_status); |
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return -EINVAL; |
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} |
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/* |
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* The command completed successfully, so save the command status and |
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* read the values returned in mailboxes 1-5. |
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*/ |
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params->mailbox[0] = cmd_status; |
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for (i = 1; i < ARRAY_SIZE(params->mailbox); i++) |
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params->mailbox[i] = readl(®isters->sis_mailbox[i]); |
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return 0; |
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} |
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/* |
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* This function verifies that we are talking to a controller that speaks PQI. |
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*/ |
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int sis_get_ctrl_properties(struct pqi_ctrl_info *ctrl_info) |
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{ |
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int rc; |
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u32 properties; |
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u32 extended_properties; |
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struct sis_sync_cmd_params params; |
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memset(¶ms, 0, sizeof(params)); |
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rc = sis_send_sync_cmd(ctrl_info, SIS_CMD_GET_ADAPTER_PROPERTIES, |
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¶ms); |
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if (rc) |
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return rc; |
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properties = params.mailbox[1]; |
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if (!(properties & SIS_EXTENDED_PROPERTIES_SUPPORTED)) |
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return -ENODEV; |
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extended_properties = params.mailbox[4]; |
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if ((extended_properties & SIS_REQUIRED_EXTENDED_PROPERTIES) != |
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SIS_REQUIRED_EXTENDED_PROPERTIES) |
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return -ENODEV; |
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if (extended_properties & SIS_PQI_RESET_QUIESCE_SUPPORTED) |
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ctrl_info->pqi_reset_quiesce_supported = true; |
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return 0; |
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} |
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int sis_get_pqi_capabilities(struct pqi_ctrl_info *ctrl_info) |
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{ |
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int rc; |
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struct sis_sync_cmd_params params; |
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memset(¶ms, 0, sizeof(params)); |
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rc = sis_send_sync_cmd(ctrl_info, SIS_CMD_GET_PQI_CAPABILITIES, |
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¶ms); |
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if (rc) |
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return rc; |
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ctrl_info->max_sg_entries = params.mailbox[1]; |
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ctrl_info->max_transfer_size = params.mailbox[2]; |
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ctrl_info->max_outstanding_requests = params.mailbox[3]; |
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ctrl_info->config_table_offset = params.mailbox[4]; |
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ctrl_info->config_table_length = params.mailbox[5]; |
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return 0; |
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} |
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int sis_init_base_struct_addr(struct pqi_ctrl_info *ctrl_info) |
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{ |
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int rc; |
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void *base_struct_unaligned; |
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struct sis_base_struct *base_struct; |
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struct sis_sync_cmd_params params; |
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unsigned long error_buffer_paddr; |
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dma_addr_t bus_address; |
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base_struct_unaligned = kzalloc(sizeof(*base_struct) |
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+ SIS_BASE_STRUCT_ALIGNMENT - 1, GFP_KERNEL); |
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if (!base_struct_unaligned) |
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return -ENOMEM; |
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base_struct = PTR_ALIGN(base_struct_unaligned, |
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SIS_BASE_STRUCT_ALIGNMENT); |
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error_buffer_paddr = (unsigned long)ctrl_info->error_buffer_dma_handle; |
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put_unaligned_le32(SIS_BASE_STRUCT_REVISION, &base_struct->revision); |
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put_unaligned_le32(lower_32_bits(error_buffer_paddr), |
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&base_struct->error_buffer_paddr_low); |
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put_unaligned_le32(upper_32_bits(error_buffer_paddr), |
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&base_struct->error_buffer_paddr_high); |
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put_unaligned_le32(PQI_ERROR_BUFFER_ELEMENT_LENGTH, |
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&base_struct->error_buffer_element_length); |
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put_unaligned_le32(ctrl_info->max_io_slots, |
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&base_struct->error_buffer_num_elements); |
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bus_address = dma_map_single(&ctrl_info->pci_dev->dev, base_struct, |
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sizeof(*base_struct), DMA_TO_DEVICE); |
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if (dma_mapping_error(&ctrl_info->pci_dev->dev, bus_address)) { |
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rc = -ENOMEM; |
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goto out; |
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} |
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memset(¶ms, 0, sizeof(params)); |
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params.mailbox[1] = lower_32_bits((u64)bus_address); |
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params.mailbox[2] = upper_32_bits((u64)bus_address); |
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params.mailbox[3] = sizeof(*base_struct); |
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rc = sis_send_sync_cmd(ctrl_info, SIS_CMD_INIT_BASE_STRUCT_ADDRESS, |
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¶ms); |
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dma_unmap_single(&ctrl_info->pci_dev->dev, bus_address, |
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sizeof(*base_struct), DMA_TO_DEVICE); |
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out: |
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kfree(base_struct_unaligned); |
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return rc; |
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} |
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#define SIS_DOORBELL_BIT_CLEAR_TIMEOUT_SECS 30 |
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static int sis_wait_for_doorbell_bit_to_clear( |
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struct pqi_ctrl_info *ctrl_info, u32 bit) |
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{ |
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int rc = 0; |
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u32 doorbell_register; |
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unsigned long timeout; |
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timeout = (SIS_DOORBELL_BIT_CLEAR_TIMEOUT_SECS * PQI_HZ) + jiffies; |
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while (1) { |
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doorbell_register = |
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readl(&ctrl_info->registers->sis_host_to_ctrl_doorbell); |
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if ((doorbell_register & bit) == 0) |
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break; |
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if (readl(&ctrl_info->registers->sis_firmware_status) & |
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SIS_CTRL_KERNEL_PANIC) { |
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rc = -ENODEV; |
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break; |
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} |
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if (time_after(jiffies, timeout)) { |
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dev_err(&ctrl_info->pci_dev->dev, |
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"doorbell register bit 0x%x not cleared\n", |
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bit); |
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rc = -ETIMEDOUT; |
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break; |
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} |
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usleep_range(1000, 2000); |
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} |
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return rc; |
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} |
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static inline int sis_set_doorbell_bit(struct pqi_ctrl_info *ctrl_info, u32 bit) |
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{ |
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writel(bit, &ctrl_info->registers->sis_host_to_ctrl_doorbell); |
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return sis_wait_for_doorbell_bit_to_clear(ctrl_info, bit); |
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} |
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void sis_enable_msix(struct pqi_ctrl_info *ctrl_info) |
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{ |
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sis_set_doorbell_bit(ctrl_info, SIS_ENABLE_MSIX); |
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} |
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void sis_enable_intx(struct pqi_ctrl_info *ctrl_info) |
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{ |
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sis_set_doorbell_bit(ctrl_info, SIS_ENABLE_INTX); |
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} |
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void sis_shutdown_ctrl(struct pqi_ctrl_info *ctrl_info) |
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{ |
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if (readl(&ctrl_info->registers->sis_firmware_status) & |
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SIS_CTRL_KERNEL_PANIC) |
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return; |
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writel(SIS_TRIGGER_SHUTDOWN, |
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&ctrl_info->registers->sis_host_to_ctrl_doorbell); |
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} |
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int sis_pqi_reset_quiesce(struct pqi_ctrl_info *ctrl_info) |
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{ |
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return sis_set_doorbell_bit(ctrl_info, SIS_PQI_RESET_QUIESCE); |
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} |
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int sis_reenable_sis_mode(struct pqi_ctrl_info *ctrl_info) |
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{ |
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return sis_set_doorbell_bit(ctrl_info, SIS_REENABLE_SIS_MODE); |
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} |
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void sis_write_driver_scratch(struct pqi_ctrl_info *ctrl_info, u32 value) |
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{ |
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writel(value, &ctrl_info->registers->sis_driver_scratch); |
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} |
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u32 sis_read_driver_scratch(struct pqi_ctrl_info *ctrl_info) |
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{ |
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return readl(&ctrl_info->registers->sis_driver_scratch); |
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} |
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void sis_soft_reset(struct pqi_ctrl_info *ctrl_info) |
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{ |
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writel(SIS_SOFT_RESET, |
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&ctrl_info->registers->sis_host_to_ctrl_doorbell); |
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} |
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static void __attribute__((unused)) verify_structures(void) |
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{ |
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BUILD_BUG_ON(offsetof(struct sis_base_struct, |
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revision) != 0x0); |
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BUILD_BUG_ON(offsetof(struct sis_base_struct, |
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flags) != 0x4); |
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BUILD_BUG_ON(offsetof(struct sis_base_struct, |
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error_buffer_paddr_low) != 0x8); |
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BUILD_BUG_ON(offsetof(struct sis_base_struct, |
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error_buffer_paddr_high) != 0xc); |
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BUILD_BUG_ON(offsetof(struct sis_base_struct, |
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error_buffer_element_length) != 0x10); |
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BUILD_BUG_ON(offsetof(struct sis_base_struct, |
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error_buffer_num_elements) != 0x14); |
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BUILD_BUG_ON(sizeof(struct sis_base_struct) != 0x18); |
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}
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