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440 lines
15 KiB
440 lines
15 KiB
/* SPDX-License-Identifier: GPL-2.0-only */ |
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/* |
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* Copyright (c) 2005-2014 Brocade Communications Systems, Inc. |
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* Copyright (c) 2014- QLogic Corporation. |
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* All rights reserved |
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* www.qlogic.com |
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* |
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* Linux driver for QLogic BR-series Fibre Channel Host Bus Adapter. |
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*/ |
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#ifndef __BFA_H__ |
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#define __BFA_H__ |
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#include "bfad_drv.h" |
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#include "bfa_cs.h" |
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#include "bfa_plog.h" |
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#include "bfa_defs_svc.h" |
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#include "bfi.h" |
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#include "bfa_ioc.h" |
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struct bfa_s; |
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typedef void (*bfa_isr_func_t) (struct bfa_s *bfa, struct bfi_msg_s *m); |
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typedef void (*bfa_cb_cbfn_status_t) (void *cbarg, bfa_status_t status); |
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/* |
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* Interrupt message handlers |
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*/ |
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void bfa_isr_unhandled(struct bfa_s *bfa, struct bfi_msg_s *m); |
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/* |
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* Request and response queue related defines |
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*/ |
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#define BFA_REQQ_NELEMS_MIN (4) |
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#define BFA_RSPQ_NELEMS_MIN (4) |
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#define bfa_reqq_pi(__bfa, __reqq) ((__bfa)->iocfc.req_cq_pi[__reqq]) |
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#define bfa_reqq_ci(__bfa, __reqq) \ |
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(*(u32 *)((__bfa)->iocfc.req_cq_shadow_ci[__reqq].kva)) |
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#define bfa_reqq_full(__bfa, __reqq) \ |
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(((bfa_reqq_pi(__bfa, __reqq) + 1) & \ |
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((__bfa)->iocfc.cfg.drvcfg.num_reqq_elems - 1)) == \ |
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bfa_reqq_ci(__bfa, __reqq)) |
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#define bfa_reqq_next(__bfa, __reqq) \ |
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(bfa_reqq_full(__bfa, __reqq) ? NULL : \ |
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((void *)((struct bfi_msg_s *)((__bfa)->iocfc.req_cq_ba[__reqq].kva) \ |
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+ bfa_reqq_pi((__bfa), (__reqq))))) |
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#define bfa_reqq_produce(__bfa, __reqq, __mh) do { \ |
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(__mh).mtag.h2i.qid = (__bfa)->iocfc.hw_qid[__reqq];\ |
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(__bfa)->iocfc.req_cq_pi[__reqq]++; \ |
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(__bfa)->iocfc.req_cq_pi[__reqq] &= \ |
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((__bfa)->iocfc.cfg.drvcfg.num_reqq_elems - 1); \ |
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writel((__bfa)->iocfc.req_cq_pi[__reqq], \ |
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(__bfa)->iocfc.bfa_regs.cpe_q_pi[__reqq]); \ |
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} while (0) |
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#define bfa_rspq_pi(__bfa, __rspq) \ |
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(*(u32 *)((__bfa)->iocfc.rsp_cq_shadow_pi[__rspq].kva)) |
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#define bfa_rspq_ci(__bfa, __rspq) ((__bfa)->iocfc.rsp_cq_ci[__rspq]) |
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#define bfa_rspq_elem(__bfa, __rspq, __ci) \ |
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(&((struct bfi_msg_s *)((__bfa)->iocfc.rsp_cq_ba[__rspq].kva))[__ci]) |
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#define CQ_INCR(__index, __size) do { \ |
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(__index)++; \ |
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(__index) &= ((__size) - 1); \ |
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} while (0) |
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/* |
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* Circular queue usage assignments |
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*/ |
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enum { |
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BFA_REQQ_IOC = 0, /* all low-priority IOC msgs */ |
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BFA_REQQ_FCXP = 0, /* all FCXP messages */ |
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BFA_REQQ_LPS = 0, /* all lport service msgs */ |
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BFA_REQQ_PORT = 0, /* all port messages */ |
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BFA_REQQ_FLASH = 0, /* for flash module */ |
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BFA_REQQ_DIAG = 0, /* for diag module */ |
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BFA_REQQ_RPORT = 0, /* all port messages */ |
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BFA_REQQ_SBOOT = 0, /* all san boot messages */ |
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BFA_REQQ_QOS_LO = 1, /* all low priority IO */ |
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BFA_REQQ_QOS_MD = 2, /* all medium priority IO */ |
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BFA_REQQ_QOS_HI = 3, /* all high priority IO */ |
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}; |
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static inline void |
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bfa_reqq_winit(struct bfa_reqq_wait_s *wqe, void (*qresume) (void *cbarg), |
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void *cbarg) |
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{ |
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wqe->qresume = qresume; |
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wqe->cbarg = cbarg; |
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} |
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#define bfa_reqq(__bfa, __reqq) (&(__bfa)->reqq_waitq[__reqq]) |
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/* |
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* static inline void |
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* bfa_reqq_wait(struct bfa_s *bfa, int reqq, struct bfa_reqq_wait_s *wqe) |
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*/ |
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#define bfa_reqq_wait(__bfa, __reqq, __wqe) do { \ |
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\ |
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struct list_head *waitq = bfa_reqq(__bfa, __reqq); \ |
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\ |
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WARN_ON(((__reqq) >= BFI_IOC_MAX_CQS)); \ |
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WARN_ON(!((__wqe)->qresume && (__wqe)->cbarg)); \ |
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\ |
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list_add_tail(&(__wqe)->qe, waitq); \ |
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} while (0) |
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#define bfa_reqq_wcancel(__wqe) list_del(&(__wqe)->qe) |
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#define bfa_cb_queue(__bfa, __hcb_qe, __cbfn, __cbarg) do { \ |
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(__hcb_qe)->cbfn = (__cbfn); \ |
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(__hcb_qe)->cbarg = (__cbarg); \ |
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(__hcb_qe)->pre_rmv = BFA_FALSE; \ |
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list_add_tail(&(__hcb_qe)->qe, &(__bfa)->comp_q); \ |
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} while (0) |
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#define bfa_cb_dequeue(__hcb_qe) list_del(&(__hcb_qe)->qe) |
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#define bfa_cb_queue_once(__bfa, __hcb_qe, __cbfn, __cbarg) do { \ |
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(__hcb_qe)->cbfn = (__cbfn); \ |
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(__hcb_qe)->cbarg = (__cbarg); \ |
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if (!(__hcb_qe)->once) { \ |
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list_add_tail(&(__hcb_qe)->qe, &(__bfa)->comp_q); \ |
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(__hcb_qe)->once = BFA_TRUE; \ |
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} \ |
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} while (0) |
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#define bfa_cb_queue_status(__bfa, __hcb_qe, __status) do { \ |
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(__hcb_qe)->fw_status = (__status); \ |
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list_add_tail(&(__hcb_qe)->qe, &(__bfa)->comp_q); \ |
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} while (0) |
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#define bfa_cb_queue_done(__hcb_qe) do { \ |
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(__hcb_qe)->once = BFA_FALSE; \ |
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} while (0) |
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/* |
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* PCI devices supported by the current BFA |
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*/ |
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struct bfa_pciid_s { |
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u16 device_id; |
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u16 vendor_id; |
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}; |
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extern char bfa_version[]; |
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struct bfa_iocfc_regs_s { |
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void __iomem *intr_status; |
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void __iomem *intr_mask; |
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void __iomem *cpe_q_pi[BFI_IOC_MAX_CQS]; |
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void __iomem *cpe_q_ci[BFI_IOC_MAX_CQS]; |
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void __iomem *cpe_q_ctrl[BFI_IOC_MAX_CQS]; |
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void __iomem *rme_q_ci[BFI_IOC_MAX_CQS]; |
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void __iomem *rme_q_pi[BFI_IOC_MAX_CQS]; |
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void __iomem *rme_q_ctrl[BFI_IOC_MAX_CQS]; |
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}; |
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/* |
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* MSIX vector handlers |
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*/ |
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#define BFA_MSIX_MAX_VECTORS 22 |
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typedef void (*bfa_msix_handler_t)(struct bfa_s *bfa, int vec); |
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struct bfa_msix_s { |
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int nvecs; |
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bfa_msix_handler_t handler[BFA_MSIX_MAX_VECTORS]; |
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}; |
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/* |
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* Chip specific interfaces |
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*/ |
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struct bfa_hwif_s { |
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void (*hw_reginit)(struct bfa_s *bfa); |
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void (*hw_reqq_ack)(struct bfa_s *bfa, int reqq); |
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void (*hw_rspq_ack)(struct bfa_s *bfa, int rspq, u32 ci); |
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void (*hw_msix_init)(struct bfa_s *bfa, int nvecs); |
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void (*hw_msix_ctrl_install)(struct bfa_s *bfa); |
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void (*hw_msix_queue_install)(struct bfa_s *bfa); |
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void (*hw_msix_uninstall)(struct bfa_s *bfa); |
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void (*hw_isr_mode_set)(struct bfa_s *bfa, bfa_boolean_t msix); |
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void (*hw_msix_getvecs)(struct bfa_s *bfa, u32 *vecmap, |
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u32 *nvecs, u32 *maxvec); |
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void (*hw_msix_get_rme_range) (struct bfa_s *bfa, u32 *start, |
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u32 *end); |
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int cpe_vec_q0; |
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int rme_vec_q0; |
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}; |
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typedef void (*bfa_cb_iocfc_t) (void *cbarg, enum bfa_status status); |
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struct bfa_faa_cbfn_s { |
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bfa_cb_iocfc_t faa_cbfn; |
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void *faa_cbarg; |
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}; |
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#define BFA_FAA_ENABLED 1 |
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#define BFA_FAA_DISABLED 2 |
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/* |
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* FAA attributes |
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*/ |
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struct bfa_faa_attr_s { |
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wwn_t faa; |
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u8 faa_state; |
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u8 pwwn_source; |
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u8 rsvd[6]; |
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}; |
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struct bfa_faa_args_s { |
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struct bfa_faa_attr_s *faa_attr; |
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struct bfa_faa_cbfn_s faa_cb; |
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u8 faa_state; |
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bfa_boolean_t busy; |
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}; |
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struct bfa_iocfc_s { |
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bfa_fsm_t fsm; |
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struct bfa_s *bfa; |
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struct bfa_iocfc_cfg_s cfg; |
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u32 req_cq_pi[BFI_IOC_MAX_CQS]; |
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u32 rsp_cq_ci[BFI_IOC_MAX_CQS]; |
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u8 hw_qid[BFI_IOC_MAX_CQS]; |
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struct bfa_cb_qe_s init_hcb_qe; |
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struct bfa_cb_qe_s stop_hcb_qe; |
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struct bfa_cb_qe_s dis_hcb_qe; |
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struct bfa_cb_qe_s en_hcb_qe; |
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struct bfa_cb_qe_s stats_hcb_qe; |
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bfa_boolean_t submod_enabled; |
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bfa_boolean_t cb_reqd; /* Driver call back reqd */ |
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bfa_status_t op_status; /* Status of bfa iocfc op */ |
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struct bfa_dma_s cfg_info; |
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struct bfi_iocfc_cfg_s *cfginfo; |
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struct bfa_dma_s cfgrsp_dma; |
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struct bfi_iocfc_cfgrsp_s *cfgrsp; |
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struct bfa_dma_s req_cq_ba[BFI_IOC_MAX_CQS]; |
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struct bfa_dma_s req_cq_shadow_ci[BFI_IOC_MAX_CQS]; |
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struct bfa_dma_s rsp_cq_ba[BFI_IOC_MAX_CQS]; |
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struct bfa_dma_s rsp_cq_shadow_pi[BFI_IOC_MAX_CQS]; |
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struct bfa_iocfc_regs_s bfa_regs; /* BFA device registers */ |
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struct bfa_hwif_s hwif; |
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bfa_cb_iocfc_t updateq_cbfn; /* bios callback function */ |
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void *updateq_cbarg; /* bios callback arg */ |
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u32 intr_mask; |
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struct bfa_faa_args_s faa_args; |
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struct bfa_mem_dma_s ioc_dma; |
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struct bfa_mem_dma_s iocfc_dma; |
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struct bfa_mem_dma_s reqq_dma[BFI_IOC_MAX_CQS]; |
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struct bfa_mem_dma_s rspq_dma[BFI_IOC_MAX_CQS]; |
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struct bfa_mem_kva_s kva_seg; |
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}; |
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#define BFA_MEM_IOC_DMA(_bfa) (&((_bfa)->iocfc.ioc_dma)) |
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#define BFA_MEM_IOCFC_DMA(_bfa) (&((_bfa)->iocfc.iocfc_dma)) |
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#define BFA_MEM_REQQ_DMA(_bfa, _qno) (&((_bfa)->iocfc.reqq_dma[(_qno)])) |
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#define BFA_MEM_RSPQ_DMA(_bfa, _qno) (&((_bfa)->iocfc.rspq_dma[(_qno)])) |
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#define BFA_MEM_IOCFC_KVA(_bfa) (&((_bfa)->iocfc.kva_seg)) |
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#define bfa_fn_lpu(__bfa) \ |
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bfi_fn_lpu(bfa_ioc_pcifn(&(__bfa)->ioc), bfa_ioc_portid(&(__bfa)->ioc)) |
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#define bfa_msix_init(__bfa, __nvecs) \ |
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((__bfa)->iocfc.hwif.hw_msix_init(__bfa, __nvecs)) |
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#define bfa_msix_ctrl_install(__bfa) \ |
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((__bfa)->iocfc.hwif.hw_msix_ctrl_install(__bfa)) |
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#define bfa_msix_queue_install(__bfa) \ |
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((__bfa)->iocfc.hwif.hw_msix_queue_install(__bfa)) |
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#define bfa_msix_uninstall(__bfa) \ |
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((__bfa)->iocfc.hwif.hw_msix_uninstall(__bfa)) |
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#define bfa_isr_rspq_ack(__bfa, __queue, __ci) \ |
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((__bfa)->iocfc.hwif.hw_rspq_ack(__bfa, __queue, __ci)) |
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#define bfa_isr_reqq_ack(__bfa, __queue) do { \ |
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if ((__bfa)->iocfc.hwif.hw_reqq_ack) \ |
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(__bfa)->iocfc.hwif.hw_reqq_ack(__bfa, __queue); \ |
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} while (0) |
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#define bfa_isr_mode_set(__bfa, __msix) do { \ |
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if ((__bfa)->iocfc.hwif.hw_isr_mode_set) \ |
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(__bfa)->iocfc.hwif.hw_isr_mode_set(__bfa, __msix); \ |
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} while (0) |
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#define bfa_msix_getvecs(__bfa, __vecmap, __nvecs, __maxvec) \ |
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((__bfa)->iocfc.hwif.hw_msix_getvecs(__bfa, __vecmap, \ |
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__nvecs, __maxvec)) |
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#define bfa_msix_get_rme_range(__bfa, __start, __end) \ |
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((__bfa)->iocfc.hwif.hw_msix_get_rme_range(__bfa, __start, __end)) |
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#define bfa_msix(__bfa, __vec) \ |
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((__bfa)->msix.handler[__vec](__bfa, __vec)) |
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/* |
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* FC specific IOC functions. |
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*/ |
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void bfa_iocfc_meminfo(struct bfa_iocfc_cfg_s *cfg, |
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struct bfa_meminfo_s *meminfo, |
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struct bfa_s *bfa); |
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void bfa_iocfc_attach(struct bfa_s *bfa, void *bfad, |
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struct bfa_iocfc_cfg_s *cfg, |
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struct bfa_pcidev_s *pcidev); |
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void bfa_iocfc_init(struct bfa_s *bfa); |
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void bfa_iocfc_start(struct bfa_s *bfa); |
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void bfa_iocfc_stop(struct bfa_s *bfa); |
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void bfa_iocfc_isr(void *bfa, struct bfi_mbmsg_s *msg); |
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void bfa_iocfc_set_snsbase(struct bfa_s *bfa, int seg_no, u64 snsbase_pa); |
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bfa_boolean_t bfa_iocfc_is_operational(struct bfa_s *bfa); |
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void bfa_iocfc_reset_queues(struct bfa_s *bfa); |
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void bfa_msix_all(struct bfa_s *bfa, int vec); |
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void bfa_msix_reqq(struct bfa_s *bfa, int vec); |
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void bfa_msix_rspq(struct bfa_s *bfa, int vec); |
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void bfa_msix_lpu_err(struct bfa_s *bfa, int vec); |
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void bfa_hwcb_reginit(struct bfa_s *bfa); |
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void bfa_hwcb_rspq_ack(struct bfa_s *bfa, int rspq, u32 ci); |
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void bfa_hwcb_msix_init(struct bfa_s *bfa, int nvecs); |
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void bfa_hwcb_msix_ctrl_install(struct bfa_s *bfa); |
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void bfa_hwcb_msix_queue_install(struct bfa_s *bfa); |
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void bfa_hwcb_msix_uninstall(struct bfa_s *bfa); |
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void bfa_hwcb_isr_mode_set(struct bfa_s *bfa, bfa_boolean_t msix); |
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void bfa_hwcb_msix_getvecs(struct bfa_s *bfa, u32 *vecmap, u32 *nvecs, |
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u32 *maxvec); |
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void bfa_hwcb_msix_get_rme_range(struct bfa_s *bfa, u32 *start, |
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u32 *end); |
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void bfa_hwct_reginit(struct bfa_s *bfa); |
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void bfa_hwct2_reginit(struct bfa_s *bfa); |
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void bfa_hwct_reqq_ack(struct bfa_s *bfa, int rspq); |
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void bfa_hwct_rspq_ack(struct bfa_s *bfa, int rspq, u32 ci); |
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void bfa_hwct2_rspq_ack(struct bfa_s *bfa, int rspq, u32 ci); |
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void bfa_hwct_msix_init(struct bfa_s *bfa, int nvecs); |
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void bfa_hwct_msix_ctrl_install(struct bfa_s *bfa); |
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void bfa_hwct_msix_queue_install(struct bfa_s *bfa); |
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void bfa_hwct_msix_uninstall(struct bfa_s *bfa); |
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void bfa_hwct_isr_mode_set(struct bfa_s *bfa, bfa_boolean_t msix); |
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void bfa_hwct_msix_getvecs(struct bfa_s *bfa, u32 *vecmap, u32 *nvecs, |
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u32 *maxvec); |
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void bfa_hwct_msix_get_rme_range(struct bfa_s *bfa, u32 *start, |
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u32 *end); |
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void bfa_iocfc_get_bootwwns(struct bfa_s *bfa, u8 *nwwns, wwn_t *wwns); |
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int bfa_iocfc_get_pbc_vports(struct bfa_s *bfa, |
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struct bfi_pbc_vport_s *pbc_vport); |
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/* |
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*---------------------------------------------------------------------- |
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* BFA public interfaces |
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*---------------------------------------------------------------------- |
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*/ |
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#define bfa_stats(_mod, _stats) ((_mod)->stats._stats++) |
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#define bfa_ioc_get_stats(__bfa, __ioc_stats) \ |
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bfa_ioc_fetch_stats(&(__bfa)->ioc, __ioc_stats) |
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#define bfa_ioc_clear_stats(__bfa) \ |
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bfa_ioc_clr_stats(&(__bfa)->ioc) |
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#define bfa_get_nports(__bfa) \ |
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bfa_ioc_get_nports(&(__bfa)->ioc) |
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#define bfa_get_adapter_manufacturer(__bfa, __manufacturer) \ |
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bfa_ioc_get_adapter_manufacturer(&(__bfa)->ioc, __manufacturer) |
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#define bfa_get_adapter_model(__bfa, __model) \ |
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bfa_ioc_get_adapter_model(&(__bfa)->ioc, __model) |
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#define bfa_get_adapter_serial_num(__bfa, __serial_num) \ |
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bfa_ioc_get_adapter_serial_num(&(__bfa)->ioc, __serial_num) |
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#define bfa_get_adapter_fw_ver(__bfa, __fw_ver) \ |
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bfa_ioc_get_adapter_fw_ver(&(__bfa)->ioc, __fw_ver) |
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#define bfa_get_adapter_optrom_ver(__bfa, __optrom_ver) \ |
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bfa_ioc_get_adapter_optrom_ver(&(__bfa)->ioc, __optrom_ver) |
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#define bfa_get_pci_chip_rev(__bfa, __chip_rev) \ |
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bfa_ioc_get_pci_chip_rev(&(__bfa)->ioc, __chip_rev) |
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#define bfa_get_ioc_state(__bfa) \ |
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bfa_ioc_get_state(&(__bfa)->ioc) |
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#define bfa_get_type(__bfa) \ |
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bfa_ioc_get_type(&(__bfa)->ioc) |
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#define bfa_get_mac(__bfa) \ |
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bfa_ioc_get_mac(&(__bfa)->ioc) |
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#define bfa_get_mfg_mac(__bfa) \ |
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bfa_ioc_get_mfg_mac(&(__bfa)->ioc) |
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#define bfa_get_fw_clock_res(__bfa) \ |
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((__bfa)->iocfc.cfgrsp->fwcfg.fw_tick_res) |
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/* |
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* lun mask macros return NULL when min cfg is enabled and there is |
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* no memory allocated for lunmask. |
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*/ |
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#define bfa_get_lun_mask(__bfa) \ |
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((&(__bfa)->modules.dconf_mod)->min_cfg) ? NULL : \ |
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(&(BFA_DCONF_MOD(__bfa)->dconf->lun_mask)) |
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#define bfa_get_lun_mask_list(_bfa) \ |
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((&(_bfa)->modules.dconf_mod)->min_cfg) ? NULL : \ |
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(bfa_get_lun_mask(_bfa)->lun_list) |
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#define bfa_get_lun_mask_status(_bfa) \ |
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(((&(_bfa)->modules.dconf_mod)->min_cfg) \ |
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? BFA_LUNMASK_MINCFG : ((bfa_get_lun_mask(_bfa))->status)) |
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void bfa_get_pciids(struct bfa_pciid_s **pciids, int *npciids); |
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void bfa_cfg_get_default(struct bfa_iocfc_cfg_s *cfg); |
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void bfa_cfg_get_min(struct bfa_iocfc_cfg_s *cfg); |
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void bfa_cfg_get_meminfo(struct bfa_iocfc_cfg_s *cfg, |
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struct bfa_meminfo_s *meminfo, |
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struct bfa_s *bfa); |
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void bfa_attach(struct bfa_s *bfa, void *bfad, struct bfa_iocfc_cfg_s *cfg, |
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struct bfa_meminfo_s *meminfo, |
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struct bfa_pcidev_s *pcidev); |
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void bfa_detach(struct bfa_s *bfa); |
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void bfa_cb_init(void *bfad, bfa_status_t status); |
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void bfa_cb_updateq(void *bfad, bfa_status_t status); |
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bfa_boolean_t bfa_intx(struct bfa_s *bfa); |
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void bfa_isr_enable(struct bfa_s *bfa); |
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void bfa_isr_disable(struct bfa_s *bfa); |
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void bfa_comp_deq(struct bfa_s *bfa, struct list_head *comp_q); |
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void bfa_comp_process(struct bfa_s *bfa, struct list_head *comp_q); |
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void bfa_comp_free(struct bfa_s *bfa, struct list_head *comp_q); |
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typedef void (*bfa_cb_ioc_t) (void *cbarg, enum bfa_status status); |
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void bfa_iocfc_get_attr(struct bfa_s *bfa, struct bfa_iocfc_attr_s *attr); |
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bfa_status_t bfa_iocfc_israttr_set(struct bfa_s *bfa, |
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struct bfa_iocfc_intr_attr_s *attr); |
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void bfa_iocfc_enable(struct bfa_s *bfa); |
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void bfa_iocfc_disable(struct bfa_s *bfa); |
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#define bfa_timer_start(_bfa, _timer, _timercb, _arg, _timeout) \ |
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bfa_timer_begin(&(_bfa)->timer_mod, _timer, _timercb, _arg, _timeout) |
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struct bfa_cb_pending_q_s { |
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struct bfa_cb_qe_s hcb_qe; |
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void *data; /* Driver buffer */ |
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}; |
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/* Common macros to operate on pending stats/attr apis */ |
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#define bfa_pending_q_init(__qe, __cbfn, __cbarg, __data) do { \ |
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bfa_q_qe_init(&((__qe)->hcb_qe.qe)); \ |
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(__qe)->hcb_qe.cbfn = (__cbfn); \ |
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(__qe)->hcb_qe.cbarg = (__cbarg); \ |
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(__qe)->hcb_qe.pre_rmv = BFA_TRUE; \ |
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(__qe)->data = (__data); \ |
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} while (0) |
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#endif /* __BFA_H__ */
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