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446 lines
11 KiB
446 lines
11 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* SPI Driver for Microchip MCP795 RTC |
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* |
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* Copyright (C) Josef Gajdusek <[email protected]> |
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* |
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* based on other Linux RTC drivers |
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* |
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* Device datasheet: |
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* https://ww1.microchip.com/downloads/en/DeviceDoc/22280A.pdf |
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*/ |
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#include <linux/module.h> |
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#include <linux/kernel.h> |
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#include <linux/device.h> |
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#include <linux/printk.h> |
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#include <linux/spi/spi.h> |
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#include <linux/rtc.h> |
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#include <linux/of.h> |
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#include <linux/bcd.h> |
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#include <linux/delay.h> |
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/* MCP795 Instructions, see datasheet table 3-1 */ |
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#define MCP795_EEREAD 0x03 |
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#define MCP795_EEWRITE 0x02 |
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#define MCP795_EEWRDI 0x04 |
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#define MCP795_EEWREN 0x06 |
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#define MCP795_SRREAD 0x05 |
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#define MCP795_SRWRITE 0x01 |
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#define MCP795_READ 0x13 |
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#define MCP795_WRITE 0x12 |
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#define MCP795_UNLOCK 0x14 |
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#define MCP795_IDWRITE 0x32 |
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#define MCP795_IDREAD 0x33 |
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#define MCP795_CLRWDT 0x44 |
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#define MCP795_CLRRAM 0x54 |
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/* MCP795 RTCC registers, see datasheet table 4-1 */ |
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#define MCP795_REG_SECONDS 0x01 |
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#define MCP795_REG_DAY 0x04 |
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#define MCP795_REG_MONTH 0x06 |
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#define MCP795_REG_CONTROL 0x08 |
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#define MCP795_REG_ALM0_SECONDS 0x0C |
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#define MCP795_REG_ALM0_DAY 0x0F |
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#define MCP795_ST_BIT BIT(7) |
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#define MCP795_24_BIT BIT(6) |
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#define MCP795_LP_BIT BIT(5) |
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#define MCP795_EXTOSC_BIT BIT(3) |
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#define MCP795_OSCON_BIT BIT(5) |
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#define MCP795_ALM0_BIT BIT(4) |
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#define MCP795_ALM1_BIT BIT(5) |
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#define MCP795_ALM0IF_BIT BIT(3) |
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#define MCP795_ALM0C0_BIT BIT(4) |
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#define MCP795_ALM0C1_BIT BIT(5) |
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#define MCP795_ALM0C2_BIT BIT(6) |
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#define SEC_PER_DAY (24 * 60 * 60) |
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static int mcp795_rtcc_read(struct device *dev, u8 addr, u8 *buf, u8 count) |
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{ |
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struct spi_device *spi = to_spi_device(dev); |
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int ret; |
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u8 tx[2]; |
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tx[0] = MCP795_READ; |
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tx[1] = addr; |
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ret = spi_write_then_read(spi, tx, sizeof(tx), buf, count); |
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if (ret) |
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dev_err(dev, "Failed reading %d bytes from address %x.\n", |
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count, addr); |
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return ret; |
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} |
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static int mcp795_rtcc_write(struct device *dev, u8 addr, u8 *data, u8 count) |
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{ |
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struct spi_device *spi = to_spi_device(dev); |
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int ret; |
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u8 tx[257]; |
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tx[0] = MCP795_WRITE; |
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tx[1] = addr; |
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memcpy(&tx[2], data, count); |
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ret = spi_write(spi, tx, 2 + count); |
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if (ret) |
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dev_err(dev, "Failed to write %d bytes to address %x.\n", |
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count, addr); |
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return ret; |
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} |
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static int mcp795_rtcc_set_bits(struct device *dev, u8 addr, u8 mask, u8 state) |
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{ |
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int ret; |
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u8 tmp; |
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ret = mcp795_rtcc_read(dev, addr, &tmp, 1); |
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if (ret) |
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return ret; |
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if ((tmp & mask) != state) { |
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tmp = (tmp & ~mask) | state; |
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ret = mcp795_rtcc_write(dev, addr, &tmp, 1); |
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} |
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return ret; |
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} |
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static int mcp795_stop_oscillator(struct device *dev, bool *extosc) |
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{ |
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int retries = 5; |
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int ret; |
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u8 data; |
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ret = mcp795_rtcc_set_bits(dev, MCP795_REG_SECONDS, MCP795_ST_BIT, 0); |
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if (ret) |
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return ret; |
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ret = mcp795_rtcc_read(dev, MCP795_REG_CONTROL, &data, 1); |
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if (ret) |
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return ret; |
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*extosc = !!(data & MCP795_EXTOSC_BIT); |
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ret = mcp795_rtcc_set_bits( |
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dev, MCP795_REG_CONTROL, MCP795_EXTOSC_BIT, 0); |
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if (ret) |
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return ret; |
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/* wait for the OSCON bit to clear */ |
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do { |
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usleep_range(700, 800); |
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ret = mcp795_rtcc_read(dev, MCP795_REG_DAY, &data, 1); |
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if (ret) |
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break; |
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if (!(data & MCP795_OSCON_BIT)) |
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break; |
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} while (--retries); |
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return !retries ? -EIO : ret; |
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} |
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static int mcp795_start_oscillator(struct device *dev, bool *extosc) |
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{ |
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if (extosc) { |
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u8 data = *extosc ? MCP795_EXTOSC_BIT : 0; |
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int ret; |
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ret = mcp795_rtcc_set_bits( |
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dev, MCP795_REG_CONTROL, MCP795_EXTOSC_BIT, data); |
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if (ret) |
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return ret; |
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} |
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return mcp795_rtcc_set_bits( |
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dev, MCP795_REG_SECONDS, MCP795_ST_BIT, MCP795_ST_BIT); |
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} |
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/* Enable or disable Alarm 0 in RTC */ |
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static int mcp795_update_alarm(struct device *dev, bool enable) |
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{ |
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int ret; |
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dev_dbg(dev, "%s alarm\n", enable ? "Enable" : "Disable"); |
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if (enable) { |
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/* clear ALM0IF (Alarm 0 Interrupt Flag) bit */ |
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ret = mcp795_rtcc_set_bits(dev, MCP795_REG_ALM0_DAY, |
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MCP795_ALM0IF_BIT, 0); |
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if (ret) |
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return ret; |
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/* enable alarm 0 */ |
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ret = mcp795_rtcc_set_bits(dev, MCP795_REG_CONTROL, |
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MCP795_ALM0_BIT, MCP795_ALM0_BIT); |
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} else { |
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/* disable alarm 0 and alarm 1 */ |
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ret = mcp795_rtcc_set_bits(dev, MCP795_REG_CONTROL, |
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MCP795_ALM0_BIT | MCP795_ALM1_BIT, 0); |
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} |
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return ret; |
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} |
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static int mcp795_set_time(struct device *dev, struct rtc_time *tim) |
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{ |
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int ret; |
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u8 data[7]; |
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bool extosc; |
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/* Stop RTC and store current value of EXTOSC bit */ |
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ret = mcp795_stop_oscillator(dev, &extosc); |
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if (ret) |
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return ret; |
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/* Read first, so we can leave config bits untouched */ |
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ret = mcp795_rtcc_read(dev, MCP795_REG_SECONDS, data, sizeof(data)); |
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if (ret) |
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return ret; |
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data[0] = (data[0] & 0x80) | bin2bcd(tim->tm_sec); |
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data[1] = (data[1] & 0x80) | bin2bcd(tim->tm_min); |
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data[2] = bin2bcd(tim->tm_hour); |
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data[3] = (data[3] & 0xF8) | bin2bcd(tim->tm_wday + 1); |
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data[4] = bin2bcd(tim->tm_mday); |
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data[5] = (data[5] & MCP795_LP_BIT) | bin2bcd(tim->tm_mon + 1); |
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if (tim->tm_year > 100) |
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tim->tm_year -= 100; |
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data[6] = bin2bcd(tim->tm_year); |
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/* Always write the date and month using a separate Write command. |
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* This is a workaround for a know silicon issue that some combinations |
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* of date and month values may result in the date being reset to 1. |
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*/ |
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ret = mcp795_rtcc_write(dev, MCP795_REG_SECONDS, data, 5); |
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if (ret) |
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return ret; |
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ret = mcp795_rtcc_write(dev, MCP795_REG_MONTH, &data[5], 2); |
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if (ret) |
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return ret; |
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/* Start back RTC and restore previous value of EXTOSC bit. |
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* There is no need to clear EXTOSC bit when the previous value was 0 |
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* because it was already cleared when stopping the RTC oscillator. |
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*/ |
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ret = mcp795_start_oscillator(dev, extosc ? &extosc : NULL); |
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if (ret) |
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return ret; |
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dev_dbg(dev, "Set mcp795: %ptR\n", tim); |
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return 0; |
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} |
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static int mcp795_read_time(struct device *dev, struct rtc_time *tim) |
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{ |
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int ret; |
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u8 data[7]; |
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ret = mcp795_rtcc_read(dev, MCP795_REG_SECONDS, data, sizeof(data)); |
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if (ret) |
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return ret; |
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tim->tm_sec = bcd2bin(data[0] & 0x7F); |
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tim->tm_min = bcd2bin(data[1] & 0x7F); |
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tim->tm_hour = bcd2bin(data[2] & 0x3F); |
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tim->tm_wday = bcd2bin(data[3] & 0x07) - 1; |
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tim->tm_mday = bcd2bin(data[4] & 0x3F); |
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tim->tm_mon = bcd2bin(data[5] & 0x1F) - 1; |
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tim->tm_year = bcd2bin(data[6]) + 100; /* Assume we are in 20xx */ |
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dev_dbg(dev, "Read from mcp795: %ptR\n", tim); |
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return 0; |
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} |
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static int mcp795_set_alarm(struct device *dev, struct rtc_wkalrm *alm) |
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{ |
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struct rtc_time now_tm; |
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time64_t now; |
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time64_t later; |
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u8 tmp[6]; |
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int ret; |
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/* Read current time from RTC hardware */ |
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ret = mcp795_read_time(dev, &now_tm); |
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if (ret) |
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return ret; |
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/* Get the number of seconds since 1970 */ |
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now = rtc_tm_to_time64(&now_tm); |
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later = rtc_tm_to_time64(&alm->time); |
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if (later <= now) |
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return -EINVAL; |
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/* make sure alarm fires within the next one year */ |
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if ((later - now) >= |
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(SEC_PER_DAY * (365 + is_leap_year(alm->time.tm_year)))) |
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return -EDOM; |
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/* disable alarm */ |
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ret = mcp795_update_alarm(dev, false); |
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if (ret) |
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return ret; |
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/* Read registers, so we can leave configuration bits untouched */ |
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ret = mcp795_rtcc_read(dev, MCP795_REG_ALM0_SECONDS, tmp, sizeof(tmp)); |
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if (ret) |
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return ret; |
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alm->time.tm_year = -1; |
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alm->time.tm_isdst = -1; |
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alm->time.tm_yday = -1; |
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tmp[0] = (tmp[0] & 0x80) | bin2bcd(alm->time.tm_sec); |
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tmp[1] = (tmp[1] & 0x80) | bin2bcd(alm->time.tm_min); |
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tmp[2] = (tmp[2] & 0xE0) | bin2bcd(alm->time.tm_hour); |
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tmp[3] = (tmp[3] & 0x80) | bin2bcd(alm->time.tm_wday + 1); |
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/* set alarm match: seconds, minutes, hour, day, date and month */ |
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tmp[3] |= (MCP795_ALM0C2_BIT | MCP795_ALM0C1_BIT | MCP795_ALM0C0_BIT); |
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tmp[4] = (tmp[4] & 0xC0) | bin2bcd(alm->time.tm_mday); |
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tmp[5] = (tmp[5] & 0xE0) | bin2bcd(alm->time.tm_mon + 1); |
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ret = mcp795_rtcc_write(dev, MCP795_REG_ALM0_SECONDS, tmp, sizeof(tmp)); |
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if (ret) |
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return ret; |
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/* enable alarm if requested */ |
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if (alm->enabled) { |
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ret = mcp795_update_alarm(dev, true); |
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if (ret) |
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return ret; |
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dev_dbg(dev, "Alarm IRQ armed\n"); |
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} |
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dev_dbg(dev, "Set alarm: %ptRdr(%d) %ptRt\n", |
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&alm->time, alm->time.tm_wday, &alm->time); |
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return 0; |
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} |
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static int mcp795_read_alarm(struct device *dev, struct rtc_wkalrm *alm) |
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{ |
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u8 data[6]; |
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int ret; |
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ret = mcp795_rtcc_read( |
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dev, MCP795_REG_ALM0_SECONDS, data, sizeof(data)); |
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if (ret) |
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return ret; |
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alm->time.tm_sec = bcd2bin(data[0] & 0x7F); |
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alm->time.tm_min = bcd2bin(data[1] & 0x7F); |
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alm->time.tm_hour = bcd2bin(data[2] & 0x1F); |
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alm->time.tm_wday = bcd2bin(data[3] & 0x07) - 1; |
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alm->time.tm_mday = bcd2bin(data[4] & 0x3F); |
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alm->time.tm_mon = bcd2bin(data[5] & 0x1F) - 1; |
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alm->time.tm_year = -1; |
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alm->time.tm_isdst = -1; |
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alm->time.tm_yday = -1; |
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dev_dbg(dev, "Read alarm: %ptRdr(%d) %ptRt\n", |
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&alm->time, alm->time.tm_wday, &alm->time); |
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return 0; |
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} |
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static int mcp795_alarm_irq_enable(struct device *dev, unsigned int enabled) |
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{ |
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return mcp795_update_alarm(dev, !!enabled); |
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} |
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static irqreturn_t mcp795_irq(int irq, void *data) |
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{ |
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struct spi_device *spi = data; |
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struct rtc_device *rtc = spi_get_drvdata(spi); |
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int ret; |
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rtc_lock(rtc); |
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/* Disable alarm. |
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* There is no need to clear ALM0IF (Alarm 0 Interrupt Flag) bit, |
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* because it is done every time when alarm is enabled. |
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*/ |
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ret = mcp795_update_alarm(&spi->dev, false); |
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if (ret) |
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dev_err(&spi->dev, |
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"Failed to disable alarm in IRQ (ret=%d)\n", ret); |
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rtc_update_irq(rtc, 1, RTC_AF | RTC_IRQF); |
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rtc_unlock(rtc); |
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return IRQ_HANDLED; |
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} |
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static const struct rtc_class_ops mcp795_rtc_ops = { |
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.read_time = mcp795_read_time, |
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.set_time = mcp795_set_time, |
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.read_alarm = mcp795_read_alarm, |
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.set_alarm = mcp795_set_alarm, |
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.alarm_irq_enable = mcp795_alarm_irq_enable |
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}; |
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static int mcp795_probe(struct spi_device *spi) |
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{ |
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struct rtc_device *rtc; |
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int ret; |
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spi->mode = SPI_MODE_0; |
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spi->bits_per_word = 8; |
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ret = spi_setup(spi); |
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if (ret) { |
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dev_err(&spi->dev, "Unable to setup SPI\n"); |
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return ret; |
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} |
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/* Start the oscillator but don't set the value of EXTOSC bit */ |
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mcp795_start_oscillator(&spi->dev, NULL); |
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/* Clear the 12 hour mode flag*/ |
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mcp795_rtcc_set_bits(&spi->dev, 0x03, MCP795_24_BIT, 0); |
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rtc = devm_rtc_device_register(&spi->dev, "rtc-mcp795", |
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&mcp795_rtc_ops, THIS_MODULE); |
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if (IS_ERR(rtc)) |
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return PTR_ERR(rtc); |
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spi_set_drvdata(spi, rtc); |
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if (spi->irq > 0) { |
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dev_dbg(&spi->dev, "Alarm support enabled\n"); |
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/* Clear any pending alarm (ALM0IF bit) before requesting |
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* the interrupt. |
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*/ |
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mcp795_rtcc_set_bits(&spi->dev, MCP795_REG_ALM0_DAY, |
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MCP795_ALM0IF_BIT, 0); |
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ret = devm_request_threaded_irq(&spi->dev, spi->irq, NULL, |
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mcp795_irq, IRQF_TRIGGER_FALLING | IRQF_ONESHOT, |
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dev_name(&rtc->dev), spi); |
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if (ret) |
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dev_err(&spi->dev, "Failed to request IRQ: %d: %d\n", |
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spi->irq, ret); |
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else |
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device_init_wakeup(&spi->dev, true); |
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} |
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return 0; |
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} |
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#ifdef CONFIG_OF |
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static const struct of_device_id mcp795_of_match[] = { |
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{ .compatible = "maxim,mcp795" }, |
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{ } |
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}; |
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MODULE_DEVICE_TABLE(of, mcp795_of_match); |
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#endif |
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static struct spi_driver mcp795_driver = { |
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.driver = { |
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.name = "rtc-mcp795", |
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.of_match_table = of_match_ptr(mcp795_of_match), |
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}, |
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.probe = mcp795_probe, |
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}; |
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module_spi_driver(mcp795_driver); |
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MODULE_DESCRIPTION("MCP795 RTC SPI Driver"); |
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MODULE_AUTHOR("Josef Gajdusek <[email protected]>"); |
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MODULE_LICENSE("GPL"); |
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MODULE_ALIAS("spi:mcp795");
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