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733 lines
21 KiB
733 lines
21 KiB
/* |
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* Copyright (c) 2008-2011 Atheros Communications Inc. |
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* |
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* Permission to use, copy, modify, and/or distribute this software for any |
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* purpose with or without fee is hereby granted, provided that the above |
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* copyright notice and this permission notice appear in all copies. |
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* |
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
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*/ |
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#ifndef EEPROM_H |
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#define EEPROM_H |
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#define AR_EEPROM_MODAL_SPURS 5 |
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#include "../ath.h" |
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#include <net/cfg80211.h> |
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#include "ar9003_eeprom.h" |
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|
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/* helpers to swap EEPROM fields, which are stored as __le16 or __le32. Since |
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* we are 100% sure about it we __force these to u16/u32 for the swab calls to |
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* silence the sparse checks. These macros are used when we have a Big Endian |
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* EEPROM (according to AR5416_EEPMISC_BIG_ENDIAN) and need to convert the |
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* fields to __le16/__le32. |
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*/ |
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#define EEPROM_FIELD_SWAB16(field) \ |
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(field = (__force __le16)swab16((__force u16)field)) |
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#define EEPROM_FIELD_SWAB32(field) \ |
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(field = (__force __le32)swab32((__force u32)field)) |
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#ifdef __BIG_ENDIAN |
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#define AR5416_EEPROM_MAGIC 0x5aa5 |
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#else |
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#define AR5416_EEPROM_MAGIC 0xa55a |
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#endif |
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#define CTRY_DEBUG 0x1ff |
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#define CTRY_DEFAULT 0 |
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#define AR_EEPROM_EEPCAP_COMPRESS_DIS 0x0001 |
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#define AR_EEPROM_EEPCAP_AES_DIS 0x0002 |
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#define AR_EEPROM_EEPCAP_FASTFRAME_DIS 0x0004 |
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#define AR_EEPROM_EEPCAP_BURST_DIS 0x0008 |
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#define AR_EEPROM_EEPCAP_MAXQCU 0x01F0 |
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#define AR_EEPROM_EEPCAP_MAXQCU_S 4 |
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#define AR_EEPROM_EEPCAP_HEAVY_CLIP_EN 0x0200 |
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#define AR_EEPROM_EEPCAP_KC_ENTRIES 0xF000 |
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#define AR_EEPROM_EEPCAP_KC_ENTRIES_S 12 |
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#define AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND 0x0040 |
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#define AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN 0x0080 |
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#define AR_EEPROM_EEREGCAP_EN_KK_U2 0x0100 |
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#define AR_EEPROM_EEREGCAP_EN_KK_MIDBAND 0x0200 |
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#define AR_EEPROM_EEREGCAP_EN_KK_U1_ODD 0x0400 |
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#define AR_EEPROM_EEREGCAP_EN_KK_NEW_11A 0x0800 |
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#define AR_EEPROM_EEREGCAP_EN_KK_U1_ODD_PRE4_0 0x4000 |
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#define AR_EEPROM_EEREGCAP_EN_KK_NEW_11A_PRE4_0 0x8000 |
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#define AR5416_EEPROM_MAGIC_OFFSET 0x0 |
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#define AR5416_EEPROM_S 2 |
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#define AR5416_EEPROM_OFFSET 0x2000 |
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#define AR5416_EEPROM_MAX 0xae0 |
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#define AR5416_EEPROM_START_ADDR \ |
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(AR_SREV_9100(ah)) ? 0x1fff1000 : 0x503f1200 |
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#define SD_NO_CTL 0xE0 |
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#define NO_CTL 0xff |
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#define CTL_MODE_M 0xf |
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#define CTL_11A 0 |
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#define CTL_11B 1 |
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#define CTL_11G 2 |
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#define CTL_2GHT20 5 |
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#define CTL_5GHT20 6 |
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#define CTL_2GHT40 7 |
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#define CTL_5GHT40 8 |
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#define EXT_ADDITIVE (0x8000) |
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#define CTL_11A_EXT (CTL_11A | EXT_ADDITIVE) |
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#define CTL_11G_EXT (CTL_11G | EXT_ADDITIVE) |
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#define CTL_11B_EXT (CTL_11B | EXT_ADDITIVE) |
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#define SUB_NUM_CTL_MODES_AT_5G_40 2 |
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#define SUB_NUM_CTL_MODES_AT_2G_40 3 |
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#define POWER_CORRECTION_FOR_TWO_CHAIN 6 /* 10*log10(2)*2 */ |
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#define POWER_CORRECTION_FOR_THREE_CHAIN 10 /* 10*log10(3)*2 */ |
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/* |
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* For AR9285 and later chipsets, the following bits are not being programmed |
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* in EEPROM and so need to be enabled always. |
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* |
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* Bit 0: en_fcc_mid |
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* Bit 1: en_jap_mid |
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* Bit 2: en_fcc_dfs_ht40 |
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* Bit 3: en_jap_ht40 |
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* Bit 4: en_jap_dfs_ht40 |
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*/ |
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#define AR9285_RDEXT_DEFAULT 0x1F |
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#define ATH9K_POW_SM(_r, _s) (((_r) & 0x3f) << (_s)) |
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#define FREQ2FBIN(x, y) (u8)((y) ? ((x) - 2300) : (((x) - 4800) / 5)) |
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#define FBIN2FREQ(x, y) ((y) ? (2300 + x) : (4800 + 5 * x)) |
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#define ath9k_hw_use_flash(_ah) (!(_ah->ah_flags & AH_USE_EEPROM)) |
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#define OLC_FOR_AR9280_20_LATER (AR_SREV_9280_20_OR_LATER(ah) && \ |
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ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) |
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#define OLC_FOR_AR9287_10_LATER (AR_SREV_9287_11_OR_LATER(ah) && \ |
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ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) |
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#define EEP_RFSILENT_ENABLED 0x0001 |
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#define EEP_RFSILENT_ENABLED_S 0 |
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#define EEP_RFSILENT_POLARITY 0x0002 |
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#define EEP_RFSILENT_POLARITY_S 1 |
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#define EEP_RFSILENT_GPIO_SEL ((AR_SREV_9462(ah) || AR_SREV_9565(ah)) ? 0x00fc : 0x001c) |
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#define EEP_RFSILENT_GPIO_SEL_S 2 |
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#define AR5416_OPFLAGS_11A 0x01 |
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#define AR5416_OPFLAGS_11G 0x02 |
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#define AR5416_OPFLAGS_N_5G_HT40 0x04 |
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#define AR5416_OPFLAGS_N_2G_HT40 0x08 |
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#define AR5416_OPFLAGS_N_5G_HT20 0x10 |
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#define AR5416_OPFLAGS_N_2G_HT20 0x20 |
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#define AR5416_EEP_NO_BACK_VER 0x1 |
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#define AR5416_EEP_VER 0xE |
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#define AR5416_EEP_VER_MAJOR_SHIFT 12 |
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#define AR5416_EEP_VER_MAJOR_MASK 0xF000 |
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#define AR5416_EEP_VER_MINOR_MASK 0x0FFF |
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#define AR5416_EEP_MINOR_VER_2 0x2 |
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#define AR5416_EEP_MINOR_VER_3 0x3 |
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#define AR5416_EEP_MINOR_VER_7 0x7 |
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#define AR5416_EEP_MINOR_VER_9 0x9 |
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#define AR5416_EEP_MINOR_VER_16 0x10 |
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#define AR5416_EEP_MINOR_VER_17 0x11 |
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#define AR5416_EEP_MINOR_VER_19 0x13 |
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#define AR5416_EEP_MINOR_VER_20 0x14 |
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#define AR5416_EEP_MINOR_VER_21 0x15 |
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#define AR5416_EEP_MINOR_VER_22 0x16 |
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#define AR5416_NUM_5G_CAL_PIERS 8 |
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#define AR5416_NUM_2G_CAL_PIERS 4 |
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#define AR5416_NUM_5G_20_TARGET_POWERS 8 |
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#define AR5416_NUM_5G_40_TARGET_POWERS 8 |
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#define AR5416_NUM_2G_CCK_TARGET_POWERS 3 |
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#define AR5416_NUM_2G_20_TARGET_POWERS 4 |
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#define AR5416_NUM_2G_40_TARGET_POWERS 4 |
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#define AR5416_NUM_CTLS 24 |
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#define AR5416_NUM_BAND_EDGES 8 |
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#define AR5416_NUM_PD_GAINS 4 |
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#define AR5416_PD_GAINS_IN_MASK 4 |
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#define AR5416_PD_GAIN_ICEPTS 5 |
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#define AR5416_NUM_PDADC_VALUES 128 |
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#define AR5416_BCHAN_UNUSED 0xFF |
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#define AR5416_MAX_PWR_RANGE_IN_HALF_DB 64 |
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#define AR5416_MAX_CHAINS 3 |
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#define AR9300_MAX_CHAINS 3 |
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#define AR5416_PWR_TABLE_OFFSET_DB -5 |
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|
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/* Rx gain type values */ |
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#define AR5416_EEP_RXGAIN_23DB_BACKOFF 0 |
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#define AR5416_EEP_RXGAIN_13DB_BACKOFF 1 |
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#define AR5416_EEP_RXGAIN_ORIG 2 |
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/* Tx gain type values */ |
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#define AR5416_EEP_TXGAIN_ORIGINAL 0 |
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#define AR5416_EEP_TXGAIN_HIGH_POWER 1 |
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|
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/* Endianness of EEPROM content */ |
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#define AR5416_EEPMISC_BIG_ENDIAN 0x01 |
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#define AR5416_EEP4K_START_LOC 64 |
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#define AR5416_EEP4K_NUM_2G_CAL_PIERS 3 |
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#define AR5416_EEP4K_NUM_2G_CCK_TARGET_POWERS 3 |
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#define AR5416_EEP4K_NUM_2G_20_TARGET_POWERS 3 |
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#define AR5416_EEP4K_NUM_2G_40_TARGET_POWERS 3 |
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#define AR5416_EEP4K_NUM_CTLS 12 |
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#define AR5416_EEP4K_NUM_BAND_EDGES 4 |
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#define AR5416_EEP4K_NUM_PD_GAINS 2 |
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#define AR5416_EEP4K_MAX_CHAINS 1 |
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#define AR9280_TX_GAIN_TABLE_SIZE 22 |
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#define AR9287_EEP_VER 0xE |
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#define AR9287_EEP_MINOR_VER_1 0x1 |
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#define AR9287_EEP_MINOR_VER_2 0x2 |
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#define AR9287_EEP_MINOR_VER_3 0x3 |
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#define AR9287_EEP_MINOR_VER AR9287_EEP_MINOR_VER_3 |
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#define AR9287_EEP_MINOR_VER_b AR9287_EEP_MINOR_VER |
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#define AR9287_EEP_NO_BACK_VER AR9287_EEP_MINOR_VER_1 |
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#define AR9287_EEP_START_LOC 128 |
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#define AR9287_HTC_EEP_START_LOC 256 |
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#define AR9287_NUM_2G_CAL_PIERS 3 |
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#define AR9287_NUM_2G_CCK_TARGET_POWERS 3 |
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#define AR9287_NUM_2G_20_TARGET_POWERS 3 |
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#define AR9287_NUM_2G_40_TARGET_POWERS 3 |
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#define AR9287_NUM_CTLS 12 |
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#define AR9287_NUM_BAND_EDGES 4 |
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#define AR9287_PD_GAIN_ICEPTS 1 |
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#define AR9287_EEPMISC_WOW 0x02 |
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#define AR9287_MAX_CHAINS 2 |
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#define AR9287_ANT_16S 32 |
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#define AR9287_DATA_SZ 32 |
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#define AR9287_PWR_TABLE_OFFSET_DB -5 |
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#define AR9287_CHECKSUM_LOCATION (AR9287_EEP_START_LOC + 1) |
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#define CTL_EDGE_TPOWER(_ctl) ((_ctl) & 0x3f) |
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#define CTL_EDGE_FLAGS(_ctl) (((_ctl) >> 6) & 0x03) |
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#define LNA_CTL_BUF_MODE BIT(0) |
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#define LNA_CTL_ISEL_LO BIT(1) |
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#define LNA_CTL_ISEL_HI BIT(2) |
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#define LNA_CTL_BUF_IN BIT(3) |
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#define LNA_CTL_FEM_BAND BIT(4) |
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#define LNA_CTL_LOCAL_BIAS BIT(5) |
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#define LNA_CTL_FORCE_XPA BIT(6) |
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#define LNA_CTL_USE_ANT1 BIT(7) |
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enum eeprom_param { |
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EEP_NFTHRESH_5, |
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EEP_NFTHRESH_2, |
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EEP_MAC_MSW, |
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EEP_MAC_MID, |
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EEP_MAC_LSW, |
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EEP_REG_0, |
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EEP_OP_CAP, |
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EEP_OP_MODE, |
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EEP_RF_SILENT, |
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EEP_OB_5, |
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EEP_DB_5, |
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EEP_OB_2, |
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EEP_DB_2, |
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EEP_TX_MASK, |
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EEP_RX_MASK, |
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EEP_FSTCLK_5G, |
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EEP_RXGAIN_TYPE, |
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EEP_OL_PWRCTRL, |
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EEP_TXGAIN_TYPE, |
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EEP_RC_CHAIN_MASK, |
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EEP_DAC_HPWR_5G, |
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EEP_FRAC_N_5G, |
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EEP_DEV_TYPE, |
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EEP_TEMPSENSE_SLOPE, |
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EEP_TEMPSENSE_SLOPE_PAL_ON, |
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EEP_PWR_TABLE_OFFSET, |
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EEP_PAPRD, |
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EEP_MODAL_VER, |
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EEP_ANT_DIV_CTL1, |
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EEP_CHAIN_MASK_REDUCE, |
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EEP_ANTENNA_GAIN_2G, |
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EEP_ANTENNA_GAIN_5G, |
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}; |
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enum ar5416_rates { |
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rate6mb, rate9mb, rate12mb, rate18mb, |
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rate24mb, rate36mb, rate48mb, rate54mb, |
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rate1l, rate2l, rate2s, rate5_5l, |
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rate5_5s, rate11l, rate11s, rateXr, |
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rateHt20_0, rateHt20_1, rateHt20_2, rateHt20_3, |
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rateHt20_4, rateHt20_5, rateHt20_6, rateHt20_7, |
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rateHt40_0, rateHt40_1, rateHt40_2, rateHt40_3, |
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rateHt40_4, rateHt40_5, rateHt40_6, rateHt40_7, |
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rateDupCck, rateDupOfdm, rateExtCck, rateExtOfdm, |
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Ar5416RateSize |
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}; |
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enum ath9k_hal_freq_band { |
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ATH9K_HAL_FREQ_BAND_5GHZ = 0, |
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ATH9K_HAL_FREQ_BAND_2GHZ = 1 |
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}; |
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struct base_eep_header { |
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__le16 length; |
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__le16 checksum; |
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__le16 version; |
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u8 opCapFlags; |
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u8 eepMisc; |
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__le16 regDmn[2]; |
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u8 macAddr[6]; |
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u8 rxMask; |
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u8 txMask; |
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__le16 rfSilent; |
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__le16 blueToothOptions; |
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__le16 deviceCap; |
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__le32 binBuildNumber; |
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u8 deviceType; |
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u8 pwdclkind; |
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u8 fastClk5g; |
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u8 divChain; |
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u8 rxGainType; |
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u8 dacHiPwrMode_5G; |
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u8 openLoopPwrCntl; |
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u8 dacLpMode; |
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u8 txGainType; |
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u8 rcChainMask; |
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u8 desiredScaleCCK; |
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u8 pwr_table_offset; |
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u8 frac_n_5g; |
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u8 futureBase_3[21]; |
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} __packed; |
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struct base_eep_header_4k { |
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__le16 length; |
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__le16 checksum; |
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__le16 version; |
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u8 opCapFlags; |
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u8 eepMisc; |
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__le16 regDmn[2]; |
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u8 macAddr[6]; |
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u8 rxMask; |
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u8 txMask; |
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__le16 rfSilent; |
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__le16 blueToothOptions; |
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__le16 deviceCap; |
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__le32 binBuildNumber; |
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u8 deviceType; |
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u8 txGainType; |
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} __packed; |
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struct spur_chan { |
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__le16 spurChan; |
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u8 spurRangeLow; |
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u8 spurRangeHigh; |
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} __packed; |
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struct modal_eep_header { |
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__le32 antCtrlChain[AR5416_MAX_CHAINS]; |
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__le32 antCtrlCommon; |
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u8 antennaGainCh[AR5416_MAX_CHAINS]; |
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u8 switchSettling; |
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u8 txRxAttenCh[AR5416_MAX_CHAINS]; |
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u8 rxTxMarginCh[AR5416_MAX_CHAINS]; |
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u8 adcDesiredSize; |
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u8 pgaDesiredSize; |
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u8 xlnaGainCh[AR5416_MAX_CHAINS]; |
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u8 txEndToXpaOff; |
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u8 txEndToRxOn; |
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u8 txFrameToXpaOn; |
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u8 thresh62; |
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u8 noiseFloorThreshCh[AR5416_MAX_CHAINS]; |
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u8 xpdGain; |
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u8 xpd; |
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u8 iqCalICh[AR5416_MAX_CHAINS]; |
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u8 iqCalQCh[AR5416_MAX_CHAINS]; |
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u8 pdGainOverlap; |
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u8 ob; |
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u8 db; |
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u8 xpaBiasLvl; |
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u8 pwrDecreaseFor2Chain; |
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u8 pwrDecreaseFor3Chain; |
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u8 txFrameToDataStart; |
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u8 txFrameToPaOn; |
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u8 ht40PowerIncForPdadc; |
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u8 bswAtten[AR5416_MAX_CHAINS]; |
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u8 bswMargin[AR5416_MAX_CHAINS]; |
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u8 swSettleHt40; |
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u8 xatten2Db[AR5416_MAX_CHAINS]; |
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u8 xatten2Margin[AR5416_MAX_CHAINS]; |
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u8 ob_ch1; |
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u8 db_ch1; |
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u8 lna_ctl; |
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u8 miscBits; |
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__le16 xpaBiasLvlFreq[3]; |
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u8 futureModal[6]; |
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|
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struct spur_chan spurChans[AR_EEPROM_MODAL_SPURS]; |
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} __packed; |
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struct calDataPerFreqOpLoop { |
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u8 pwrPdg[2][5]; |
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u8 vpdPdg[2][5]; |
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u8 pcdac[2][5]; |
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u8 empty[2][5]; |
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} __packed; |
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struct modal_eep_4k_header { |
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__le32 antCtrlChain[AR5416_EEP4K_MAX_CHAINS]; |
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__le32 antCtrlCommon; |
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u8 antennaGainCh[AR5416_EEP4K_MAX_CHAINS]; |
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u8 switchSettling; |
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u8 txRxAttenCh[AR5416_EEP4K_MAX_CHAINS]; |
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u8 rxTxMarginCh[AR5416_EEP4K_MAX_CHAINS]; |
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u8 adcDesiredSize; |
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u8 pgaDesiredSize; |
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u8 xlnaGainCh[AR5416_EEP4K_MAX_CHAINS]; |
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u8 txEndToXpaOff; |
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u8 txEndToRxOn; |
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u8 txFrameToXpaOn; |
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u8 thresh62; |
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u8 noiseFloorThreshCh[AR5416_EEP4K_MAX_CHAINS]; |
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u8 xpdGain; |
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u8 xpd; |
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u8 iqCalICh[AR5416_EEP4K_MAX_CHAINS]; |
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u8 iqCalQCh[AR5416_EEP4K_MAX_CHAINS]; |
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u8 pdGainOverlap; |
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#ifdef __BIG_ENDIAN_BITFIELD |
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u8 ob_1:4, ob_0:4; |
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u8 db1_1:4, db1_0:4; |
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#else |
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u8 ob_0:4, ob_1:4; |
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u8 db1_0:4, db1_1:4; |
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#endif |
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u8 xpaBiasLvl; |
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u8 txFrameToDataStart; |
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u8 txFrameToPaOn; |
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u8 ht40PowerIncForPdadc; |
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u8 bswAtten[AR5416_EEP4K_MAX_CHAINS]; |
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u8 bswMargin[AR5416_EEP4K_MAX_CHAINS]; |
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u8 swSettleHt40; |
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u8 xatten2Db[AR5416_EEP4K_MAX_CHAINS]; |
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u8 xatten2Margin[AR5416_EEP4K_MAX_CHAINS]; |
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#ifdef __BIG_ENDIAN_BITFIELD |
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u8 db2_1:4, db2_0:4; |
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#else |
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u8 db2_0:4, db2_1:4; |
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#endif |
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u8 version; |
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#ifdef __BIG_ENDIAN_BITFIELD |
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u8 ob_3:4, ob_2:4; |
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u8 antdiv_ctl1:4, ob_4:4; |
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u8 db1_3:4, db1_2:4; |
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u8 antdiv_ctl2:4, db1_4:4; |
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u8 db2_2:4, db2_3:4; |
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u8 reserved:4, db2_4:4; |
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#else |
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u8 ob_2:4, ob_3:4; |
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u8 ob_4:4, antdiv_ctl1:4; |
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u8 db1_2:4, db1_3:4; |
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u8 db1_4:4, antdiv_ctl2:4; |
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u8 db2_2:4, db2_3:4; |
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u8 db2_4:4, reserved:4; |
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#endif |
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u8 tx_diversity; |
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u8 flc_pwr_thresh; |
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u8 bb_scale_smrt_antenna; |
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#define EEP_4K_BB_DESIRED_SCALE_MASK 0x1f |
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u8 futureModal[1]; |
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struct spur_chan spurChans[AR_EEPROM_MODAL_SPURS]; |
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} __packed; |
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|
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struct base_eep_ar9287_header { |
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__le16 length; |
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__le16 checksum; |
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__le16 version; |
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u8 opCapFlags; |
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u8 eepMisc; |
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__le16 regDmn[2]; |
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u8 macAddr[6]; |
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u8 rxMask; |
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u8 txMask; |
|
__le16 rfSilent; |
|
__le16 blueToothOptions; |
|
__le16 deviceCap; |
|
__le32 binBuildNumber; |
|
u8 deviceType; |
|
u8 openLoopPwrCntl; |
|
int8_t pwrTableOffset; |
|
int8_t tempSensSlope; |
|
int8_t tempSensSlopePalOn; |
|
u8 futureBase[29]; |
|
} __packed; |
|
|
|
struct modal_eep_ar9287_header { |
|
__le32 antCtrlChain[AR9287_MAX_CHAINS]; |
|
__le32 antCtrlCommon; |
|
int8_t antennaGainCh[AR9287_MAX_CHAINS]; |
|
u8 switchSettling; |
|
u8 txRxAttenCh[AR9287_MAX_CHAINS]; |
|
u8 rxTxMarginCh[AR9287_MAX_CHAINS]; |
|
int8_t adcDesiredSize; |
|
u8 txEndToXpaOff; |
|
u8 txEndToRxOn; |
|
u8 txFrameToXpaOn; |
|
u8 thresh62; |
|
int8_t noiseFloorThreshCh[AR9287_MAX_CHAINS]; |
|
u8 xpdGain; |
|
u8 xpd; |
|
int8_t iqCalICh[AR9287_MAX_CHAINS]; |
|
int8_t iqCalQCh[AR9287_MAX_CHAINS]; |
|
u8 pdGainOverlap; |
|
u8 xpaBiasLvl; |
|
u8 txFrameToDataStart; |
|
u8 txFrameToPaOn; |
|
u8 ht40PowerIncForPdadc; |
|
u8 bswAtten[AR9287_MAX_CHAINS]; |
|
u8 bswMargin[AR9287_MAX_CHAINS]; |
|
u8 swSettleHt40; |
|
u8 version; |
|
u8 db1; |
|
u8 db2; |
|
u8 ob_cck; |
|
u8 ob_psk; |
|
u8 ob_qam; |
|
u8 ob_pal_off; |
|
u8 futureModal[30]; |
|
struct spur_chan spurChans[AR_EEPROM_MODAL_SPURS]; |
|
} __packed; |
|
|
|
struct cal_data_per_freq { |
|
u8 pwrPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS]; |
|
u8 vpdPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS]; |
|
} __packed; |
|
|
|
struct cal_data_per_freq_4k { |
|
u8 pwrPdg[AR5416_EEP4K_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS]; |
|
u8 vpdPdg[AR5416_EEP4K_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS]; |
|
} __packed; |
|
|
|
struct cal_target_power_leg { |
|
u8 bChannel; |
|
u8 tPow2x[4]; |
|
} __packed; |
|
|
|
struct cal_target_power_ht { |
|
u8 bChannel; |
|
u8 tPow2x[8]; |
|
} __packed; |
|
|
|
struct cal_ctl_edges { |
|
u8 bChannel; |
|
u8 ctl; |
|
} __packed; |
|
|
|
struct cal_data_op_loop_ar9287 { |
|
u8 pwrPdg[2][5]; |
|
u8 vpdPdg[2][5]; |
|
u8 pcdac[2][5]; |
|
u8 empty[2][5]; |
|
} __packed; |
|
|
|
struct cal_data_per_freq_ar9287 { |
|
u8 pwrPdg[AR5416_NUM_PD_GAINS][AR9287_PD_GAIN_ICEPTS]; |
|
u8 vpdPdg[AR5416_NUM_PD_GAINS][AR9287_PD_GAIN_ICEPTS]; |
|
} __packed; |
|
|
|
union cal_data_per_freq_ar9287_u { |
|
struct cal_data_op_loop_ar9287 calDataOpen; |
|
struct cal_data_per_freq_ar9287 calDataClose; |
|
} __packed; |
|
|
|
struct cal_ctl_data_ar9287 { |
|
struct cal_ctl_edges |
|
ctlEdges[AR9287_MAX_CHAINS][AR9287_NUM_BAND_EDGES]; |
|
} __packed; |
|
|
|
struct cal_ctl_data { |
|
struct cal_ctl_edges |
|
ctlEdges[AR5416_MAX_CHAINS][AR5416_NUM_BAND_EDGES]; |
|
} __packed; |
|
|
|
struct cal_ctl_data_4k { |
|
struct cal_ctl_edges |
|
ctlEdges[AR5416_EEP4K_MAX_CHAINS][AR5416_EEP4K_NUM_BAND_EDGES]; |
|
} __packed; |
|
|
|
struct ar5416_eeprom_def { |
|
struct base_eep_header baseEepHeader; |
|
u8 custData[64]; |
|
struct modal_eep_header modalHeader[2]; |
|
u8 calFreqPier5G[AR5416_NUM_5G_CAL_PIERS]; |
|
u8 calFreqPier2G[AR5416_NUM_2G_CAL_PIERS]; |
|
struct cal_data_per_freq |
|
calPierData5G[AR5416_MAX_CHAINS][AR5416_NUM_5G_CAL_PIERS]; |
|
struct cal_data_per_freq |
|
calPierData2G[AR5416_MAX_CHAINS][AR5416_NUM_2G_CAL_PIERS]; |
|
struct cal_target_power_leg |
|
calTargetPower5G[AR5416_NUM_5G_20_TARGET_POWERS]; |
|
struct cal_target_power_ht |
|
calTargetPower5GHT20[AR5416_NUM_5G_20_TARGET_POWERS]; |
|
struct cal_target_power_ht |
|
calTargetPower5GHT40[AR5416_NUM_5G_40_TARGET_POWERS]; |
|
struct cal_target_power_leg |
|
calTargetPowerCck[AR5416_NUM_2G_CCK_TARGET_POWERS]; |
|
struct cal_target_power_leg |
|
calTargetPower2G[AR5416_NUM_2G_20_TARGET_POWERS]; |
|
struct cal_target_power_ht |
|
calTargetPower2GHT20[AR5416_NUM_2G_20_TARGET_POWERS]; |
|
struct cal_target_power_ht |
|
calTargetPower2GHT40[AR5416_NUM_2G_40_TARGET_POWERS]; |
|
u8 ctlIndex[AR5416_NUM_CTLS]; |
|
struct cal_ctl_data ctlData[AR5416_NUM_CTLS]; |
|
u8 padding; |
|
} __packed; |
|
|
|
struct ar5416_eeprom_4k { |
|
struct base_eep_header_4k baseEepHeader; |
|
u8 custData[20]; |
|
struct modal_eep_4k_header modalHeader; |
|
u8 calFreqPier2G[AR5416_EEP4K_NUM_2G_CAL_PIERS]; |
|
struct cal_data_per_freq_4k |
|
calPierData2G[AR5416_EEP4K_MAX_CHAINS][AR5416_EEP4K_NUM_2G_CAL_PIERS]; |
|
struct cal_target_power_leg |
|
calTargetPowerCck[AR5416_EEP4K_NUM_2G_CCK_TARGET_POWERS]; |
|
struct cal_target_power_leg |
|
calTargetPower2G[AR5416_EEP4K_NUM_2G_20_TARGET_POWERS]; |
|
struct cal_target_power_ht |
|
calTargetPower2GHT20[AR5416_EEP4K_NUM_2G_20_TARGET_POWERS]; |
|
struct cal_target_power_ht |
|
calTargetPower2GHT40[AR5416_EEP4K_NUM_2G_40_TARGET_POWERS]; |
|
u8 ctlIndex[AR5416_EEP4K_NUM_CTLS]; |
|
struct cal_ctl_data_4k ctlData[AR5416_EEP4K_NUM_CTLS]; |
|
u8 padding; |
|
} __packed; |
|
|
|
struct ar9287_eeprom { |
|
struct base_eep_ar9287_header baseEepHeader; |
|
u8 custData[AR9287_DATA_SZ]; |
|
struct modal_eep_ar9287_header modalHeader; |
|
u8 calFreqPier2G[AR9287_NUM_2G_CAL_PIERS]; |
|
union cal_data_per_freq_ar9287_u |
|
calPierData2G[AR9287_MAX_CHAINS][AR9287_NUM_2G_CAL_PIERS]; |
|
struct cal_target_power_leg |
|
calTargetPowerCck[AR9287_NUM_2G_CCK_TARGET_POWERS]; |
|
struct cal_target_power_leg |
|
calTargetPower2G[AR9287_NUM_2G_20_TARGET_POWERS]; |
|
struct cal_target_power_ht |
|
calTargetPower2GHT20[AR9287_NUM_2G_20_TARGET_POWERS]; |
|
struct cal_target_power_ht |
|
calTargetPower2GHT40[AR9287_NUM_2G_40_TARGET_POWERS]; |
|
u8 ctlIndex[AR9287_NUM_CTLS]; |
|
struct cal_ctl_data_ar9287 ctlData[AR9287_NUM_CTLS]; |
|
u8 padding; |
|
} __packed; |
|
|
|
enum reg_ext_bitmap { |
|
REG_EXT_FCC_MIDBAND = 0, |
|
REG_EXT_JAPAN_MIDBAND = 1, |
|
REG_EXT_FCC_DFS_HT40 = 2, |
|
REG_EXT_JAPAN_NONDFS_HT40 = 3, |
|
REG_EXT_JAPAN_DFS_HT40 = 4 |
|
}; |
|
|
|
struct ath9k_country_entry { |
|
u16 countryCode; |
|
u16 regDmnEnum; |
|
u16 regDmn5G; |
|
u16 regDmn2G; |
|
u8 isMultidomain; |
|
u8 iso[3]; |
|
}; |
|
|
|
struct eeprom_ops { |
|
int (*check_eeprom)(struct ath_hw *hw); |
|
u32 (*get_eeprom)(struct ath_hw *hw, enum eeprom_param param); |
|
bool (*fill_eeprom)(struct ath_hw *hw); |
|
u32 (*dump_eeprom)(struct ath_hw *hw, bool dump_base_hdr, u8 *buf, |
|
u32 len, u32 size); |
|
int (*get_eeprom_ver)(struct ath_hw *hw); |
|
int (*get_eeprom_rev)(struct ath_hw *hw); |
|
void (*set_board_values)(struct ath_hw *hw, struct ath9k_channel *chan); |
|
void (*set_addac)(struct ath_hw *hw, struct ath9k_channel *chan); |
|
void (*set_txpower)(struct ath_hw *hw, struct ath9k_channel *chan, |
|
u16 cfgCtl, u8 twiceAntennaReduction, |
|
u8 powerLimit, bool test); |
|
u16 (*get_spur_channel)(struct ath_hw *ah, u16 i, bool is2GHz); |
|
u8 (*get_eepmisc)(struct ath_hw *ah); |
|
}; |
|
|
|
void ath9k_hw_analog_shift_regwrite(struct ath_hw *ah, u32 reg, u32 val); |
|
void ath9k_hw_analog_shift_rmw(struct ath_hw *ah, u32 reg, u32 mask, |
|
u32 shift, u32 val); |
|
int16_t ath9k_hw_interpolate(u16 target, u16 srcLeft, u16 srcRight, |
|
int16_t targetLeft, |
|
int16_t targetRight); |
|
bool ath9k_hw_get_lower_upper_index(u8 target, u8 *pList, u16 listSize, |
|
u16 *indexL, u16 *indexR); |
|
bool ath9k_hw_nvram_read(struct ath_hw *ah, u32 off, u16 *data); |
|
int ath9k_hw_nvram_swap_data(struct ath_hw *ah, bool *swap_needed, int size); |
|
bool ath9k_hw_nvram_validate_checksum(struct ath_hw *ah, int size); |
|
bool ath9k_hw_nvram_check_version(struct ath_hw *ah, int version, int minrev); |
|
void ath9k_hw_usb_gen_fill_eeprom(struct ath_hw *ah, u16 *eep_data, |
|
int eep_start_loc, int size); |
|
void ath9k_hw_fill_vpd_table(u8 pwrMin, u8 pwrMax, u8 *pPwrList, |
|
u8 *pVpdList, u16 numIntercepts, |
|
u8 *pRetVpdList); |
|
void ath9k_hw_get_legacy_target_powers(struct ath_hw *ah, |
|
struct ath9k_channel *chan, |
|
struct cal_target_power_leg *powInfo, |
|
u16 numChannels, |
|
struct cal_target_power_leg *pNewPower, |
|
u16 numRates, bool isExtTarget); |
|
void ath9k_hw_get_target_powers(struct ath_hw *ah, |
|
struct ath9k_channel *chan, |
|
struct cal_target_power_ht *powInfo, |
|
u16 numChannels, |
|
struct cal_target_power_ht *pNewPower, |
|
u16 numRates, bool isHt40Target); |
|
u16 ath9k_hw_get_max_edge_power(u16 freq, struct cal_ctl_edges *pRdEdgesPower, |
|
bool is2GHz, int num_band_edges); |
|
u16 ath9k_hw_get_scaled_power(struct ath_hw *ah, u16 power_limit, |
|
u8 antenna_reduction); |
|
void ath9k_hw_update_regulatory_maxpower(struct ath_hw *ah); |
|
int ath9k_hw_eeprom_init(struct ath_hw *ah); |
|
|
|
void ath9k_hw_get_gain_boundaries_pdadcs(struct ath_hw *ah, |
|
struct ath9k_channel *chan, |
|
void *pRawDataSet, |
|
u8 *bChans, u16 availPiers, |
|
u16 tPdGainOverlap, |
|
u16 *pPdGainBoundaries, u8 *pPDADCValues, |
|
u16 numXpdGains); |
|
|
|
static inline u16 ath9k_hw_fbin2freq(u8 fbin, bool is2GHz) |
|
{ |
|
if (fbin == AR5416_BCHAN_UNUSED) |
|
return fbin; |
|
|
|
return (u16) ((is2GHz) ? (2300 + fbin) : (4800 + 5 * fbin)); |
|
} |
|
|
|
#define ar5416_get_ntxchains(_txchainmask) \ |
|
(((_txchainmask >> 2) & 1) + \ |
|
((_txchainmask >> 1) & 1) + (_txchainmask & 1)) |
|
|
|
extern const struct eeprom_ops eep_def_ops; |
|
extern const struct eeprom_ops eep_4k_ops; |
|
extern const struct eeprom_ops eep_ar9287_ops; |
|
extern const struct eeprom_ops eep_ar9287_ops; |
|
extern const struct eeprom_ops eep_ar9300_ops; |
|
|
|
#endif /* EEPROM_H */
|
|
|