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196 lines
5.5 KiB
196 lines
5.5 KiB
/* SPDX-License-Identifier: BSD-3-Clause-Clear */ |
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/* |
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* Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. |
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*/ |
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#ifndef ATH11K_CE_H |
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#define ATH11K_CE_H |
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#define CE_COUNT_MAX 12 |
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/* Byte swap data words */ |
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#define CE_ATTR_BYTE_SWAP_DATA 2 |
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/* no interrupt on copy completion */ |
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#define CE_ATTR_DIS_INTR 8 |
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/* Host software's Copy Engine configuration. */ |
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#ifdef __BIG_ENDIAN |
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#define CE_ATTR_FLAGS CE_ATTR_BYTE_SWAP_DATA |
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#else |
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#define CE_ATTR_FLAGS 0 |
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#endif |
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/* Threshold to poll for tx completion in case of Interrupt disabled CE's */ |
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#define ATH11K_CE_USAGE_THRESHOLD 32 |
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void ath11k_ce_byte_swap(void *mem, u32 len); |
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/* |
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* Directions for interconnect pipe configuration. |
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* These definitions may be used during configuration and are shared |
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* between Host and Target. |
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* |
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* Pipe Directions are relative to the Host, so PIPEDIR_IN means |
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* "coming IN over air through Target to Host" as with a WiFi Rx operation. |
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* Conversely, PIPEDIR_OUT means "going OUT from Host through Target over air" |
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* as with a WiFi Tx operation. This is somewhat awkward for the "middle-man" |
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* Target since things that are "PIPEDIR_OUT" are coming IN to the Target |
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* over the interconnect. |
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*/ |
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#define PIPEDIR_NONE 0 |
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#define PIPEDIR_IN 1 /* Target-->Host, WiFi Rx direction */ |
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#define PIPEDIR_OUT 2 /* Host->Target, WiFi Tx direction */ |
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#define PIPEDIR_INOUT 3 /* bidirectional */ |
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#define PIPEDIR_INOUT_H2H 4 /* bidirectional, host to host */ |
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/* CE address/mask */ |
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#define CE_HOST_IE_ADDRESS 0x00A1803C |
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#define CE_HOST_IE_2_ADDRESS 0x00A18040 |
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#define CE_HOST_IE_3_ADDRESS CE_HOST_IE_ADDRESS |
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#define CE_HOST_IE_3_SHIFT 0xC |
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#define CE_RING_IDX_INCR(nentries_mask, idx) (((idx) + 1) & (nentries_mask)) |
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#define ATH11K_CE_RX_POST_RETRY_JIFFIES 50 |
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struct ath11k_base; |
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/* |
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* Establish a mapping between a service/direction and a pipe. |
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* Configuration information for a Copy Engine pipe and services. |
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* Passed from Host to Target through QMI message and must be in |
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* little endian format. |
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*/ |
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struct service_to_pipe { |
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__le32 service_id; |
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__le32 pipedir; |
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__le32 pipenum; |
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}; |
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/* |
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* Configuration information for a Copy Engine pipe. |
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* Passed from Host to Target through QMI message during startup (one per CE). |
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* |
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* NOTE: Structure is shared between Host software and Target firmware! |
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*/ |
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struct ce_pipe_config { |
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__le32 pipenum; |
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__le32 pipedir; |
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__le32 nentries; |
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__le32 nbytes_max; |
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__le32 flags; |
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__le32 reserved; |
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}; |
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struct ce_attr { |
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/* CE_ATTR_* values */ |
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unsigned int flags; |
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/* #entries in source ring - Must be a power of 2 */ |
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unsigned int src_nentries; |
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/* |
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* Max source send size for this CE. |
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* This is also the minimum size of a destination buffer. |
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*/ |
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unsigned int src_sz_max; |
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/* #entries in destination ring - Must be a power of 2 */ |
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unsigned int dest_nentries; |
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void (*recv_cb)(struct ath11k_base *, struct sk_buff *); |
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}; |
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#define CE_DESC_RING_ALIGN 8 |
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struct ath11k_ce_ring { |
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/* Number of entries in this ring; must be power of 2 */ |
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unsigned int nentries; |
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unsigned int nentries_mask; |
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/* For dest ring, this is the next index to be processed |
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* by software after it was/is received into. |
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* |
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* For src ring, this is the last descriptor that was sent |
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* and completion processed by software. |
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* |
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* Regardless of src or dest ring, this is an invariant |
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* (modulo ring size): |
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* write index >= read index >= sw_index |
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*/ |
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unsigned int sw_index; |
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/* cached copy */ |
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unsigned int write_index; |
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/* Start of DMA-coherent area reserved for descriptors */ |
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/* Host address space */ |
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void *base_addr_owner_space_unaligned; |
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/* CE address space */ |
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u32 base_addr_ce_space_unaligned; |
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/* Actual start of descriptors. |
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* Aligned to descriptor-size boundary. |
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* Points into reserved DMA-coherent area, above. |
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*/ |
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/* Host address space */ |
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void *base_addr_owner_space; |
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/* CE address space */ |
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u32 base_addr_ce_space; |
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/* HAL ring id */ |
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u32 hal_ring_id; |
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/* keep last */ |
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struct sk_buff *skb[0]; |
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}; |
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struct ath11k_ce_pipe { |
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struct ath11k_base *ab; |
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u16 pipe_num; |
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unsigned int attr_flags; |
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unsigned int buf_sz; |
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unsigned int rx_buf_needed; |
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void (*send_cb)(struct ath11k_ce_pipe *); |
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void (*recv_cb)(struct ath11k_base *, struct sk_buff *); |
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struct tasklet_struct intr_tq; |
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struct ath11k_ce_ring *src_ring; |
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struct ath11k_ce_ring *dest_ring; |
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struct ath11k_ce_ring *status_ring; |
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u64 timestamp; |
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}; |
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struct ath11k_ce { |
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struct ath11k_ce_pipe ce_pipe[CE_COUNT_MAX]; |
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/* Protects rings of all ce pipes */ |
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spinlock_t ce_lock; |
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struct ath11k_hp_update_timer hp_timer[CE_COUNT_MAX]; |
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}; |
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extern const struct ce_attr ath11k_host_ce_config_ipq8074[]; |
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extern const struct ce_attr ath11k_host_ce_config_qca6390[]; |
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extern const struct ce_attr ath11k_host_ce_config_qcn9074[]; |
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void ath11k_ce_cleanup_pipes(struct ath11k_base *ab); |
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void ath11k_ce_rx_replenish_retry(struct timer_list *t); |
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void ath11k_ce_per_engine_service(struct ath11k_base *ab, u16 ce_id); |
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int ath11k_ce_send(struct ath11k_base *ab, struct sk_buff *skb, u8 pipe_id, |
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u16 transfer_id); |
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void ath11k_ce_rx_post_buf(struct ath11k_base *ab); |
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int ath11k_ce_init_pipes(struct ath11k_base *ab); |
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int ath11k_ce_alloc_pipes(struct ath11k_base *ab); |
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void ath11k_ce_free_pipes(struct ath11k_base *ab); |
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int ath11k_ce_get_attr_flags(struct ath11k_base *ab, int ce_id); |
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void ath11k_ce_poll_send_completed(struct ath11k_base *ab, u8 pipe_id); |
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int ath11k_ce_map_service_to_pipe(struct ath11k_base *ab, u16 service_id, |
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u8 *ul_pipe, u8 *dl_pipe); |
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int ath11k_ce_attr_attach(struct ath11k_base *ab); |
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void ath11k_ce_get_shadow_config(struct ath11k_base *ab, |
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u32 **shadow_cfg, u32 *shadow_cfg_len); |
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void ath11k_ce_stop_shadow_timers(struct ath11k_base *ab); |
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#endif
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