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444 lines
11 KiB
444 lines
11 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. |
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*/ |
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/* Qualcomm Technologies, Inc. EMAC SGMII Controller driver. |
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*/ |
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#include <linux/interrupt.h> |
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#include <linux/iopoll.h> |
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#include <linux/acpi.h> |
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#include <linux/of_device.h> |
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#include "emac.h" |
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#include "emac-mac.h" |
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#include "emac-sgmii.h" |
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/* EMAC_SGMII register offsets */ |
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#define EMAC_SGMII_PHY_AUTONEG_CFG2 0x0048 |
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#define EMAC_SGMII_PHY_SPEED_CFG1 0x0074 |
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#define EMAC_SGMII_PHY_IRQ_CMD 0x00ac |
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#define EMAC_SGMII_PHY_INTERRUPT_CLEAR 0x00b0 |
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#define EMAC_SGMII_PHY_INTERRUPT_MASK 0x00b4 |
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#define EMAC_SGMII_PHY_INTERRUPT_STATUS 0x00b8 |
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#define EMAC_SGMII_PHY_RX_CHK_STATUS 0x00d4 |
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#define FORCE_AN_TX_CFG BIT(5) |
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#define FORCE_AN_RX_CFG BIT(4) |
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#define AN_ENABLE BIT(0) |
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#define DUPLEX_MODE BIT(4) |
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#define SPDMODE_1000 BIT(1) |
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#define SPDMODE_100 BIT(0) |
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#define SPDMODE_10 0 |
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#define CDR_ALIGN_DET BIT(6) |
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#define IRQ_GLOBAL_CLEAR BIT(0) |
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#define DECODE_CODE_ERR BIT(7) |
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#define DECODE_DISP_ERR BIT(6) |
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#define SGMII_PHY_IRQ_CLR_WAIT_TIME 10 |
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#define SGMII_PHY_INTERRUPT_ERR (DECODE_CODE_ERR | DECODE_DISP_ERR) |
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#define SGMII_ISR_MASK (SGMII_PHY_INTERRUPT_ERR) |
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#define SERDES_START_WAIT_TIMES 100 |
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int emac_sgmii_init(struct emac_adapter *adpt) |
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{ |
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if (!(adpt->phy.sgmii_ops && adpt->phy.sgmii_ops->init)) |
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return 0; |
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return adpt->phy.sgmii_ops->init(adpt); |
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} |
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int emac_sgmii_open(struct emac_adapter *adpt) |
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{ |
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if (!(adpt->phy.sgmii_ops && adpt->phy.sgmii_ops->open)) |
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return 0; |
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return adpt->phy.sgmii_ops->open(adpt); |
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} |
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void emac_sgmii_close(struct emac_adapter *adpt) |
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{ |
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if (!(adpt->phy.sgmii_ops && adpt->phy.sgmii_ops->close)) |
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return; |
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adpt->phy.sgmii_ops->close(adpt); |
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} |
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int emac_sgmii_link_change(struct emac_adapter *adpt, bool link_state) |
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{ |
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if (!(adpt->phy.sgmii_ops && adpt->phy.sgmii_ops->link_change)) |
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return 0; |
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return adpt->phy.sgmii_ops->link_change(adpt, link_state); |
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} |
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void emac_sgmii_reset(struct emac_adapter *adpt) |
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{ |
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if (!(adpt->phy.sgmii_ops && adpt->phy.sgmii_ops->reset)) |
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return; |
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adpt->phy.sgmii_ops->reset(adpt); |
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} |
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/* Initialize the SGMII link between the internal and external PHYs. */ |
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static void emac_sgmii_link_init(struct emac_adapter *adpt) |
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{ |
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struct emac_sgmii *phy = &adpt->phy; |
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u32 val; |
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/* Always use autonegotiation. It works no matter how the external |
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* PHY is configured. |
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*/ |
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val = readl(phy->base + EMAC_SGMII_PHY_AUTONEG_CFG2); |
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val &= ~(FORCE_AN_RX_CFG | FORCE_AN_TX_CFG); |
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val |= AN_ENABLE; |
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writel(val, phy->base + EMAC_SGMII_PHY_AUTONEG_CFG2); |
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} |
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static int emac_sgmii_irq_clear(struct emac_adapter *adpt, u8 irq_bits) |
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{ |
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struct emac_sgmii *phy = &adpt->phy; |
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u8 status; |
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writel_relaxed(irq_bits, phy->base + EMAC_SGMII_PHY_INTERRUPT_CLEAR); |
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writel_relaxed(IRQ_GLOBAL_CLEAR, phy->base + EMAC_SGMII_PHY_IRQ_CMD); |
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/* Ensure interrupt clear command is written to HW */ |
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wmb(); |
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/* After set the IRQ_GLOBAL_CLEAR bit, the status clearing must |
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* be confirmed before clearing the bits in other registers. |
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* It takes a few cycles for hw to clear the interrupt status. |
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*/ |
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if (readl_poll_timeout_atomic(phy->base + |
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EMAC_SGMII_PHY_INTERRUPT_STATUS, |
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status, !(status & irq_bits), 1, |
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SGMII_PHY_IRQ_CLR_WAIT_TIME)) { |
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net_err_ratelimited("%s: failed to clear SGMII irq: status:0x%x bits:0x%x\n", |
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adpt->netdev->name, status, irq_bits); |
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return -EIO; |
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} |
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/* Finalize clearing procedure */ |
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writel_relaxed(0, phy->base + EMAC_SGMII_PHY_IRQ_CMD); |
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writel_relaxed(0, phy->base + EMAC_SGMII_PHY_INTERRUPT_CLEAR); |
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/* Ensure that clearing procedure finalization is written to HW */ |
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wmb(); |
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return 0; |
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} |
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/* The number of decode errors that triggers a reset */ |
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#define DECODE_ERROR_LIMIT 2 |
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static irqreturn_t emac_sgmii_interrupt(int irq, void *data) |
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{ |
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struct emac_adapter *adpt = data; |
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struct emac_sgmii *phy = &adpt->phy; |
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u8 status; |
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status = readl(phy->base + EMAC_SGMII_PHY_INTERRUPT_STATUS); |
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status &= SGMII_ISR_MASK; |
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if (!status) |
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return IRQ_HANDLED; |
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/* If we get a decoding error and CDR is not locked, then try |
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* resetting the internal PHY. The internal PHY uses an embedded |
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* clock with Clock and Data Recovery (CDR) to recover the |
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* clock and data. |
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*/ |
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if (status & SGMII_PHY_INTERRUPT_ERR) { |
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int count; |
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/* The SGMII is capable of recovering from some decode |
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* errors automatically. However, if we get multiple |
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* decode errors in a row, then assume that something |
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* is wrong and reset the interface. |
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*/ |
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count = atomic_inc_return(&phy->decode_error_count); |
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if (count == DECODE_ERROR_LIMIT) { |
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schedule_work(&adpt->work_thread); |
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atomic_set(&phy->decode_error_count, 0); |
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} |
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} else { |
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/* We only care about consecutive decode errors. */ |
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atomic_set(&phy->decode_error_count, 0); |
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} |
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if (emac_sgmii_irq_clear(adpt, status)) |
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schedule_work(&adpt->work_thread); |
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return IRQ_HANDLED; |
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} |
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static void emac_sgmii_reset_prepare(struct emac_adapter *adpt) |
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{ |
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struct emac_sgmii *phy = &adpt->phy; |
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u32 val; |
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/* Reset PHY */ |
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val = readl(phy->base + EMAC_EMAC_WRAPPER_CSR2); |
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writel(((val & ~PHY_RESET) | PHY_RESET), phy->base + |
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EMAC_EMAC_WRAPPER_CSR2); |
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/* Ensure phy-reset command is written to HW before the release cmd */ |
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msleep(50); |
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val = readl(phy->base + EMAC_EMAC_WRAPPER_CSR2); |
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writel((val & ~PHY_RESET), phy->base + EMAC_EMAC_WRAPPER_CSR2); |
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/* Ensure phy-reset release command is written to HW before initializing |
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* SGMII |
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*/ |
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msleep(50); |
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} |
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static void emac_sgmii_common_reset(struct emac_adapter *adpt) |
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{ |
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int ret; |
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emac_sgmii_reset_prepare(adpt); |
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emac_sgmii_link_init(adpt); |
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ret = emac_sgmii_init(adpt); |
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if (ret) |
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netdev_err(adpt->netdev, |
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"could not reinitialize internal PHY (error=%i)\n", |
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ret); |
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} |
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static int emac_sgmii_common_open(struct emac_adapter *adpt) |
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{ |
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struct emac_sgmii *sgmii = &adpt->phy; |
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int ret; |
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if (sgmii->irq) { |
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/* Make sure interrupts are cleared and disabled first */ |
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ret = emac_sgmii_irq_clear(adpt, 0xff); |
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if (ret) |
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return ret; |
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writel(0, sgmii->base + EMAC_SGMII_PHY_INTERRUPT_MASK); |
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ret = request_irq(sgmii->irq, emac_sgmii_interrupt, 0, |
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"emac-sgmii", adpt); |
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if (ret) { |
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netdev_err(adpt->netdev, |
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"could not register handler for internal PHY\n"); |
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return ret; |
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} |
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} |
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return 0; |
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} |
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static void emac_sgmii_common_close(struct emac_adapter *adpt) |
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{ |
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struct emac_sgmii *sgmii = &adpt->phy; |
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/* Make sure interrupts are disabled */ |
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writel(0, sgmii->base + EMAC_SGMII_PHY_INTERRUPT_MASK); |
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free_irq(sgmii->irq, adpt); |
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} |
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/* The error interrupts are only valid after the link is up */ |
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static int emac_sgmii_common_link_change(struct emac_adapter *adpt, bool linkup) |
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{ |
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struct emac_sgmii *sgmii = &adpt->phy; |
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int ret; |
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if (linkup) { |
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/* Clear and enable interrupts */ |
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ret = emac_sgmii_irq_clear(adpt, 0xff); |
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if (ret) |
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return ret; |
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writel(SGMII_ISR_MASK, |
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sgmii->base + EMAC_SGMII_PHY_INTERRUPT_MASK); |
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} else { |
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/* Disable interrupts */ |
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writel(0, sgmii->base + EMAC_SGMII_PHY_INTERRUPT_MASK); |
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synchronize_irq(sgmii->irq); |
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} |
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return 0; |
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} |
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static struct sgmii_ops fsm9900_ops = { |
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.init = emac_sgmii_init_fsm9900, |
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.open = emac_sgmii_common_open, |
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.close = emac_sgmii_common_close, |
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.link_change = emac_sgmii_common_link_change, |
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.reset = emac_sgmii_common_reset, |
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}; |
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static struct sgmii_ops qdf2432_ops = { |
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.init = emac_sgmii_init_qdf2432, |
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.open = emac_sgmii_common_open, |
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.close = emac_sgmii_common_close, |
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.link_change = emac_sgmii_common_link_change, |
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.reset = emac_sgmii_common_reset, |
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}; |
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#ifdef CONFIG_ACPI |
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static struct sgmii_ops qdf2400_ops = { |
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.init = emac_sgmii_init_qdf2400, |
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.open = emac_sgmii_common_open, |
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.close = emac_sgmii_common_close, |
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.link_change = emac_sgmii_common_link_change, |
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.reset = emac_sgmii_common_reset, |
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}; |
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#endif |
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static int emac_sgmii_acpi_match(struct device *dev, void *data) |
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{ |
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#ifdef CONFIG_ACPI |
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static const struct acpi_device_id match_table[] = { |
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{ |
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.id = "QCOM8071", |
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}, |
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{} |
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}; |
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const struct acpi_device_id *id = acpi_match_device(match_table, dev); |
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struct sgmii_ops **ops = data; |
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if (id) { |
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acpi_handle handle = ACPI_HANDLE(dev); |
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unsigned long long hrv; |
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acpi_status status; |
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status = acpi_evaluate_integer(handle, "_HRV", NULL, &hrv); |
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if (status) { |
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if (status == AE_NOT_FOUND) |
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/* Older versions of the QDF2432 ACPI tables do |
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* not have an _HRV property. |
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*/ |
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hrv = 1; |
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else |
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/* Something is wrong with the tables */ |
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return 0; |
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} |
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switch (hrv) { |
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case 1: |
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*ops = &qdf2432_ops; |
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return 1; |
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case 2: |
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*ops = &qdf2400_ops; |
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return 1; |
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} |
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} |
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#endif |
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return 0; |
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} |
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static const struct of_device_id emac_sgmii_dt_match[] = { |
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{ |
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.compatible = "qcom,fsm9900-emac-sgmii", |
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.data = &fsm9900_ops, |
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}, |
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{ |
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.compatible = "qcom,qdf2432-emac-sgmii", |
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.data = &qdf2432_ops, |
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}, |
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{} |
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}; |
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int emac_sgmii_config(struct platform_device *pdev, struct emac_adapter *adpt) |
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{ |
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struct platform_device *sgmii_pdev = NULL; |
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struct emac_sgmii *phy = &adpt->phy; |
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struct resource *res; |
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int ret; |
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if (has_acpi_companion(&pdev->dev)) { |
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struct device *dev; |
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dev = device_find_child(&pdev->dev, &phy->sgmii_ops, |
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emac_sgmii_acpi_match); |
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if (!dev) { |
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dev_warn(&pdev->dev, "cannot find internal phy node\n"); |
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return 0; |
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} |
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sgmii_pdev = to_platform_device(dev); |
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} else { |
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const struct of_device_id *match; |
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struct device_node *np; |
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np = of_parse_phandle(pdev->dev.of_node, "internal-phy", 0); |
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if (!np) { |
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dev_err(&pdev->dev, "missing internal-phy property\n"); |
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return -ENODEV; |
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} |
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sgmii_pdev = of_find_device_by_node(np); |
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of_node_put(np); |
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if (!sgmii_pdev) { |
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dev_err(&pdev->dev, "invalid internal-phy property\n"); |
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return -ENODEV; |
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} |
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match = of_match_device(emac_sgmii_dt_match, &sgmii_pdev->dev); |
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if (!match) { |
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dev_err(&pdev->dev, "unrecognized internal phy node\n"); |
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ret = -ENODEV; |
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goto error_put_device; |
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} |
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phy->sgmii_ops = (struct sgmii_ops *)match->data; |
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} |
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/* Base address is the first address */ |
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res = platform_get_resource(sgmii_pdev, IORESOURCE_MEM, 0); |
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if (!res) { |
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ret = -EINVAL; |
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goto error_put_device; |
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} |
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phy->base = ioremap(res->start, resource_size(res)); |
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if (!phy->base) { |
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ret = -ENOMEM; |
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goto error_put_device; |
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} |
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/* v2 SGMII has a per-lane digital digital, so parse it if it exists */ |
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res = platform_get_resource(sgmii_pdev, IORESOURCE_MEM, 1); |
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if (res) { |
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phy->digital = ioremap(res->start, resource_size(res)); |
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if (!phy->digital) { |
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ret = -ENOMEM; |
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goto error_unmap_base; |
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} |
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} |
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ret = emac_sgmii_init(adpt); |
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if (ret) |
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goto error; |
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emac_sgmii_link_init(adpt); |
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ret = platform_get_irq(sgmii_pdev, 0); |
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if (ret > 0) |
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phy->irq = ret; |
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/* We've remapped the addresses, so we don't need the device any |
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* more. of_find_device_by_node() says we should release it. |
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*/ |
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put_device(&sgmii_pdev->dev); |
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return 0; |
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error: |
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if (phy->digital) |
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iounmap(phy->digital); |
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error_unmap_base: |
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iounmap(phy->base); |
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error_put_device: |
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put_device(&sgmii_pdev->dev); |
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return ret; |
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}
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