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191 lines
4.4 KiB
191 lines
4.4 KiB
/* SPDX-License-Identifier: GPL-2.0 */ |
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/* Copyright(c) 1999 - 2018 Intel Corporation. */ |
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#ifndef __IXGBE_VF_H__ |
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#define __IXGBE_VF_H__ |
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#include <linux/pci.h> |
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#include <linux/delay.h> |
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#include <linux/interrupt.h> |
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#include <linux/if_ether.h> |
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#include <linux/netdevice.h> |
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#include "defines.h" |
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#include "regs.h" |
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#include "mbx.h" |
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struct ixgbe_hw; |
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struct ixgbe_mac_operations { |
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s32 (*init_hw)(struct ixgbe_hw *); |
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s32 (*reset_hw)(struct ixgbe_hw *); |
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s32 (*start_hw)(struct ixgbe_hw *); |
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s32 (*clear_hw_cntrs)(struct ixgbe_hw *); |
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enum ixgbe_media_type (*get_media_type)(struct ixgbe_hw *); |
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s32 (*get_mac_addr)(struct ixgbe_hw *, u8 *); |
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s32 (*stop_adapter)(struct ixgbe_hw *); |
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s32 (*get_bus_info)(struct ixgbe_hw *); |
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s32 (*negotiate_api_version)(struct ixgbe_hw *hw, int api); |
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/* Link */ |
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s32 (*setup_link)(struct ixgbe_hw *, ixgbe_link_speed, bool, bool); |
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s32 (*check_link)(struct ixgbe_hw *, ixgbe_link_speed *, bool *, bool); |
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s32 (*get_link_capabilities)(struct ixgbe_hw *, ixgbe_link_speed *, |
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bool *); |
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/* RAR, Multicast, VLAN */ |
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s32 (*set_rar)(struct ixgbe_hw *, u32, u8 *, u32); |
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s32 (*set_uc_addr)(struct ixgbe_hw *, u32, u8 *); |
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s32 (*init_rx_addrs)(struct ixgbe_hw *); |
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s32 (*update_mc_addr_list)(struct ixgbe_hw *, struct net_device *); |
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s32 (*update_xcast_mode)(struct ixgbe_hw *, int); |
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s32 (*enable_mc)(struct ixgbe_hw *); |
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s32 (*disable_mc)(struct ixgbe_hw *); |
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s32 (*clear_vfta)(struct ixgbe_hw *); |
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s32 (*set_vfta)(struct ixgbe_hw *, u32, u32, bool); |
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s32 (*set_rlpml)(struct ixgbe_hw *, u16); |
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}; |
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enum ixgbe_mac_type { |
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ixgbe_mac_unknown = 0, |
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ixgbe_mac_82599_vf, |
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ixgbe_mac_X540_vf, |
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ixgbe_mac_X550_vf, |
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ixgbe_mac_X550EM_x_vf, |
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ixgbe_mac_x550em_a_vf, |
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ixgbe_num_macs |
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}; |
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struct ixgbe_mac_info { |
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struct ixgbe_mac_operations ops; |
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u8 addr[6]; |
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u8 perm_addr[6]; |
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enum ixgbe_mac_type type; |
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s32 mc_filter_type; |
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bool get_link_status; |
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u32 max_tx_queues; |
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u32 max_rx_queues; |
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u32 max_msix_vectors; |
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}; |
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struct ixgbe_mbx_operations { |
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s32 (*init_params)(struct ixgbe_hw *hw); |
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s32 (*read)(struct ixgbe_hw *, u32 *, u16); |
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s32 (*write)(struct ixgbe_hw *, u32 *, u16); |
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s32 (*read_posted)(struct ixgbe_hw *, u32 *, u16); |
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s32 (*write_posted)(struct ixgbe_hw *, u32 *, u16); |
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s32 (*check_for_msg)(struct ixgbe_hw *); |
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s32 (*check_for_ack)(struct ixgbe_hw *); |
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s32 (*check_for_rst)(struct ixgbe_hw *); |
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}; |
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struct ixgbe_mbx_stats { |
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u32 msgs_tx; |
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u32 msgs_rx; |
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u32 acks; |
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u32 reqs; |
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u32 rsts; |
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}; |
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struct ixgbe_mbx_info { |
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struct ixgbe_mbx_operations ops; |
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struct ixgbe_mbx_stats stats; |
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u32 timeout; |
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u32 udelay; |
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u32 v2p_mailbox; |
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u16 size; |
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}; |
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struct ixgbe_hw { |
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void *back; |
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u8 __iomem *hw_addr; |
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struct ixgbe_mac_info mac; |
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struct ixgbe_mbx_info mbx; |
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u16 device_id; |
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u16 subsystem_vendor_id; |
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u16 subsystem_device_id; |
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u16 vendor_id; |
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u8 revision_id; |
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bool adapter_stopped; |
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int api_version; |
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}; |
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struct ixgbevf_hw_stats { |
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u64 base_vfgprc; |
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u64 base_vfgptc; |
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u64 base_vfgorc; |
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u64 base_vfgotc; |
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u64 base_vfmprc; |
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u64 last_vfgprc; |
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u64 last_vfgptc; |
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u64 last_vfgorc; |
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u64 last_vfgotc; |
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u64 last_vfmprc; |
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u64 vfgprc; |
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u64 vfgptc; |
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u64 vfgorc; |
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u64 vfgotc; |
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u64 vfmprc; |
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u64 saved_reset_vfgprc; |
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u64 saved_reset_vfgptc; |
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u64 saved_reset_vfgorc; |
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u64 saved_reset_vfgotc; |
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u64 saved_reset_vfmprc; |
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}; |
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struct ixgbevf_info { |
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enum ixgbe_mac_type mac; |
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const struct ixgbe_mac_operations *mac_ops; |
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}; |
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#define IXGBE_FAILED_READ_REG 0xffffffffU |
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#define IXGBE_REMOVED(a) unlikely(!(a)) |
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static inline void ixgbe_write_reg(struct ixgbe_hw *hw, u32 reg, u32 value) |
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{ |
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u8 __iomem *reg_addr = READ_ONCE(hw->hw_addr); |
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if (IXGBE_REMOVED(reg_addr)) |
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return; |
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writel(value, reg_addr + reg); |
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} |
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#define IXGBE_WRITE_REG(h, r, v) ixgbe_write_reg(h, r, v) |
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u32 ixgbevf_read_reg(struct ixgbe_hw *hw, u32 reg); |
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#define IXGBE_READ_REG(h, r) ixgbevf_read_reg(h, r) |
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static inline void ixgbe_write_reg_array(struct ixgbe_hw *hw, u32 reg, |
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u32 offset, u32 value) |
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{ |
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ixgbe_write_reg(hw, reg + (offset << 2), value); |
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} |
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#define IXGBE_WRITE_REG_ARRAY(h, r, o, v) ixgbe_write_reg_array(h, r, o, v) |
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static inline u32 ixgbe_read_reg_array(struct ixgbe_hw *hw, u32 reg, |
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u32 offset) |
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{ |
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return ixgbevf_read_reg(hw, reg + (offset << 2)); |
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} |
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#define IXGBE_READ_REG_ARRAY(h, r, o) ixgbe_read_reg_array(h, r, o) |
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int ixgbevf_get_queues(struct ixgbe_hw *hw, unsigned int *num_tcs, |
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unsigned int *default_tc); |
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int ixgbevf_get_reta_locked(struct ixgbe_hw *hw, u32 *reta, int num_rx_queues); |
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int ixgbevf_get_rss_key_locked(struct ixgbe_hw *hw, u8 *rss_key); |
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#endif /* __IXGBE_VF_H__ */
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