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782 lines
19 KiB
782 lines
19 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* Copyright(c) 2007 - 2018 Intel Corporation. */ |
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#include <linux/if_ether.h> |
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#include <linux/delay.h> |
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#include "e1000_mac.h" |
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#include "e1000_nvm.h" |
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/** |
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* igb_raise_eec_clk - Raise EEPROM clock |
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* @hw: pointer to the HW structure |
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* @eecd: pointer to the EEPROM |
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* |
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* Enable/Raise the EEPROM clock bit. |
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**/ |
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static void igb_raise_eec_clk(struct e1000_hw *hw, u32 *eecd) |
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{ |
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*eecd = *eecd | E1000_EECD_SK; |
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wr32(E1000_EECD, *eecd); |
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wrfl(); |
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udelay(hw->nvm.delay_usec); |
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} |
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/** |
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* igb_lower_eec_clk - Lower EEPROM clock |
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* @hw: pointer to the HW structure |
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* @eecd: pointer to the EEPROM |
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* |
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* Clear/Lower the EEPROM clock bit. |
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**/ |
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static void igb_lower_eec_clk(struct e1000_hw *hw, u32 *eecd) |
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{ |
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*eecd = *eecd & ~E1000_EECD_SK; |
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wr32(E1000_EECD, *eecd); |
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wrfl(); |
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udelay(hw->nvm.delay_usec); |
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} |
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/** |
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* igb_shift_out_eec_bits - Shift data bits our to the EEPROM |
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* @hw: pointer to the HW structure |
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* @data: data to send to the EEPROM |
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* @count: number of bits to shift out |
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* |
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* We need to shift 'count' bits out to the EEPROM. So, the value in the |
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* "data" parameter will be shifted out to the EEPROM one bit at a time. |
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* In order to do this, "data" must be broken down into bits. |
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**/ |
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static void igb_shift_out_eec_bits(struct e1000_hw *hw, u16 data, u16 count) |
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{ |
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struct e1000_nvm_info *nvm = &hw->nvm; |
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u32 eecd = rd32(E1000_EECD); |
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u32 mask; |
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mask = 1u << (count - 1); |
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if (nvm->type == e1000_nvm_eeprom_spi) |
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eecd |= E1000_EECD_DO; |
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do { |
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eecd &= ~E1000_EECD_DI; |
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if (data & mask) |
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eecd |= E1000_EECD_DI; |
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wr32(E1000_EECD, eecd); |
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wrfl(); |
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udelay(nvm->delay_usec); |
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igb_raise_eec_clk(hw, &eecd); |
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igb_lower_eec_clk(hw, &eecd); |
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mask >>= 1; |
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} while (mask); |
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eecd &= ~E1000_EECD_DI; |
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wr32(E1000_EECD, eecd); |
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} |
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/** |
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* igb_shift_in_eec_bits - Shift data bits in from the EEPROM |
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* @hw: pointer to the HW structure |
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* @count: number of bits to shift in |
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* |
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* In order to read a register from the EEPROM, we need to shift 'count' bits |
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* in from the EEPROM. Bits are "shifted in" by raising the clock input to |
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* the EEPROM (setting the SK bit), and then reading the value of the data out |
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* "DO" bit. During this "shifting in" process the data in "DI" bit should |
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* always be clear. |
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**/ |
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static u16 igb_shift_in_eec_bits(struct e1000_hw *hw, u16 count) |
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{ |
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u32 eecd; |
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u32 i; |
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u16 data; |
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eecd = rd32(E1000_EECD); |
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eecd &= ~(E1000_EECD_DO | E1000_EECD_DI); |
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data = 0; |
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for (i = 0; i < count; i++) { |
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data <<= 1; |
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igb_raise_eec_clk(hw, &eecd); |
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eecd = rd32(E1000_EECD); |
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eecd &= ~E1000_EECD_DI; |
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if (eecd & E1000_EECD_DO) |
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data |= 1; |
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igb_lower_eec_clk(hw, &eecd); |
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} |
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return data; |
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} |
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/** |
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* igb_poll_eerd_eewr_done - Poll for EEPROM read/write completion |
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* @hw: pointer to the HW structure |
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* @ee_reg: EEPROM flag for polling |
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* |
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* Polls the EEPROM status bit for either read or write completion based |
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* upon the value of 'ee_reg'. |
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**/ |
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static s32 igb_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg) |
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{ |
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u32 attempts = 100000; |
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u32 i, reg = 0; |
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s32 ret_val = -E1000_ERR_NVM; |
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for (i = 0; i < attempts; i++) { |
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if (ee_reg == E1000_NVM_POLL_READ) |
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reg = rd32(E1000_EERD); |
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else |
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reg = rd32(E1000_EEWR); |
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if (reg & E1000_NVM_RW_REG_DONE) { |
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ret_val = 0; |
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break; |
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} |
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udelay(5); |
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} |
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return ret_val; |
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} |
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/** |
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* igb_acquire_nvm - Generic request for access to EEPROM |
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* @hw: pointer to the HW structure |
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* |
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* Set the EEPROM access request bit and wait for EEPROM access grant bit. |
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* Return successful if access grant bit set, else clear the request for |
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* EEPROM access and return -E1000_ERR_NVM (-1). |
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**/ |
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s32 igb_acquire_nvm(struct e1000_hw *hw) |
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{ |
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u32 eecd = rd32(E1000_EECD); |
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s32 timeout = E1000_NVM_GRANT_ATTEMPTS; |
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s32 ret_val = 0; |
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wr32(E1000_EECD, eecd | E1000_EECD_REQ); |
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eecd = rd32(E1000_EECD); |
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while (timeout) { |
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if (eecd & E1000_EECD_GNT) |
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break; |
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udelay(5); |
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eecd = rd32(E1000_EECD); |
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timeout--; |
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} |
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if (!timeout) { |
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eecd &= ~E1000_EECD_REQ; |
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wr32(E1000_EECD, eecd); |
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hw_dbg("Could not acquire NVM grant\n"); |
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ret_val = -E1000_ERR_NVM; |
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} |
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return ret_val; |
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} |
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/** |
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* igb_standby_nvm - Return EEPROM to standby state |
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* @hw: pointer to the HW structure |
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* |
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* Return the EEPROM to a standby state. |
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**/ |
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static void igb_standby_nvm(struct e1000_hw *hw) |
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{ |
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struct e1000_nvm_info *nvm = &hw->nvm; |
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u32 eecd = rd32(E1000_EECD); |
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if (nvm->type == e1000_nvm_eeprom_spi) { |
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/* Toggle CS to flush commands */ |
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eecd |= E1000_EECD_CS; |
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wr32(E1000_EECD, eecd); |
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wrfl(); |
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udelay(nvm->delay_usec); |
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eecd &= ~E1000_EECD_CS; |
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wr32(E1000_EECD, eecd); |
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wrfl(); |
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udelay(nvm->delay_usec); |
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} |
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} |
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/** |
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* e1000_stop_nvm - Terminate EEPROM command |
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* @hw: pointer to the HW structure |
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* |
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* Terminates the current command by inverting the EEPROM's chip select pin. |
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**/ |
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static void e1000_stop_nvm(struct e1000_hw *hw) |
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{ |
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u32 eecd; |
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eecd = rd32(E1000_EECD); |
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if (hw->nvm.type == e1000_nvm_eeprom_spi) { |
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/* Pull CS high */ |
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eecd |= E1000_EECD_CS; |
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igb_lower_eec_clk(hw, &eecd); |
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} |
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} |
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/** |
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* igb_release_nvm - Release exclusive access to EEPROM |
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* @hw: pointer to the HW structure |
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* |
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* Stop any current commands to the EEPROM and clear the EEPROM request bit. |
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**/ |
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void igb_release_nvm(struct e1000_hw *hw) |
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{ |
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u32 eecd; |
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e1000_stop_nvm(hw); |
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eecd = rd32(E1000_EECD); |
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eecd &= ~E1000_EECD_REQ; |
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wr32(E1000_EECD, eecd); |
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} |
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/** |
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* igb_ready_nvm_eeprom - Prepares EEPROM for read/write |
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* @hw: pointer to the HW structure |
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* |
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* Setups the EEPROM for reading and writing. |
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**/ |
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static s32 igb_ready_nvm_eeprom(struct e1000_hw *hw) |
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{ |
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struct e1000_nvm_info *nvm = &hw->nvm; |
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u32 eecd = rd32(E1000_EECD); |
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s32 ret_val = 0; |
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u16 timeout = 0; |
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u8 spi_stat_reg; |
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if (nvm->type == e1000_nvm_eeprom_spi) { |
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/* Clear SK and CS */ |
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eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); |
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wr32(E1000_EECD, eecd); |
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wrfl(); |
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udelay(1); |
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timeout = NVM_MAX_RETRY_SPI; |
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/* Read "Status Register" repeatedly until the LSB is cleared. |
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* The EEPROM will signal that the command has been completed |
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* by clearing bit 0 of the internal status register. If it's |
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* not cleared within 'timeout', then error out. |
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*/ |
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while (timeout) { |
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igb_shift_out_eec_bits(hw, NVM_RDSR_OPCODE_SPI, |
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hw->nvm.opcode_bits); |
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spi_stat_reg = (u8)igb_shift_in_eec_bits(hw, 8); |
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if (!(spi_stat_reg & NVM_STATUS_RDY_SPI)) |
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break; |
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udelay(5); |
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igb_standby_nvm(hw); |
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timeout--; |
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} |
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if (!timeout) { |
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hw_dbg("SPI NVM Status error\n"); |
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ret_val = -E1000_ERR_NVM; |
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goto out; |
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} |
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} |
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out: |
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return ret_val; |
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} |
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/** |
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* igb_read_nvm_spi - Read EEPROM's using SPI |
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* @hw: pointer to the HW structure |
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* @offset: offset of word in the EEPROM to read |
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* @words: number of words to read |
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* @data: word read from the EEPROM |
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* |
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* Reads a 16 bit word from the EEPROM. |
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**/ |
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s32 igb_read_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) |
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{ |
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struct e1000_nvm_info *nvm = &hw->nvm; |
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u32 i = 0; |
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s32 ret_val; |
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u16 word_in; |
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u8 read_opcode = NVM_READ_OPCODE_SPI; |
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/* A check for invalid values: offset too large, too many words, |
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* and not enough words. |
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*/ |
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if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || |
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(words == 0)) { |
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hw_dbg("nvm parameter(s) out of bounds\n"); |
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ret_val = -E1000_ERR_NVM; |
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goto out; |
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} |
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ret_val = nvm->ops.acquire(hw); |
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if (ret_val) |
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goto out; |
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ret_val = igb_ready_nvm_eeprom(hw); |
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if (ret_val) |
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goto release; |
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igb_standby_nvm(hw); |
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if ((nvm->address_bits == 8) && (offset >= 128)) |
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read_opcode |= NVM_A8_OPCODE_SPI; |
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/* Send the READ command (opcode + addr) */ |
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igb_shift_out_eec_bits(hw, read_opcode, nvm->opcode_bits); |
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igb_shift_out_eec_bits(hw, (u16)(offset*2), nvm->address_bits); |
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/* Read the data. SPI NVMs increment the address with each byte |
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* read and will roll over if reading beyond the end. This allows |
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* us to read the whole NVM from any offset |
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*/ |
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for (i = 0; i < words; i++) { |
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word_in = igb_shift_in_eec_bits(hw, 16); |
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data[i] = (word_in >> 8) | (word_in << 8); |
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} |
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release: |
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nvm->ops.release(hw); |
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out: |
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return ret_val; |
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} |
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/** |
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* igb_read_nvm_eerd - Reads EEPROM using EERD register |
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* @hw: pointer to the HW structure |
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* @offset: offset of word in the EEPROM to read |
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* @words: number of words to read |
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* @data: word read from the EEPROM |
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* |
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* Reads a 16 bit word from the EEPROM using the EERD register. |
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**/ |
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s32 igb_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) |
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{ |
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struct e1000_nvm_info *nvm = &hw->nvm; |
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u32 i, eerd = 0; |
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s32 ret_val = 0; |
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/* A check for invalid values: offset too large, too many words, |
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* and not enough words. |
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*/ |
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if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || |
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(words == 0)) { |
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hw_dbg("nvm parameter(s) out of bounds\n"); |
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ret_val = -E1000_ERR_NVM; |
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goto out; |
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} |
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for (i = 0; i < words; i++) { |
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eerd = ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) + |
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E1000_NVM_RW_REG_START; |
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wr32(E1000_EERD, eerd); |
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ret_val = igb_poll_eerd_eewr_done(hw, E1000_NVM_POLL_READ); |
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if (ret_val) |
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break; |
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data[i] = (rd32(E1000_EERD) >> |
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E1000_NVM_RW_REG_DATA); |
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} |
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out: |
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return ret_val; |
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} |
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/** |
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* igb_write_nvm_spi - Write to EEPROM using SPI |
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* @hw: pointer to the HW structure |
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* @offset: offset within the EEPROM to be written to |
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* @words: number of words to write |
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* @data: 16 bit word(s) to be written to the EEPROM |
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* |
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* Writes data to EEPROM at offset using SPI interface. |
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* |
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* If e1000_update_nvm_checksum is not called after this function , the |
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* EEPROM will most likley contain an invalid checksum. |
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**/ |
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s32 igb_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) |
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{ |
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struct e1000_nvm_info *nvm = &hw->nvm; |
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s32 ret_val = -E1000_ERR_NVM; |
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u16 widx = 0; |
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|
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/* A check for invalid values: offset too large, too many words, |
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* and not enough words. |
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*/ |
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if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || |
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(words == 0)) { |
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hw_dbg("nvm parameter(s) out of bounds\n"); |
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return ret_val; |
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} |
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while (widx < words) { |
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u8 write_opcode = NVM_WRITE_OPCODE_SPI; |
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ret_val = nvm->ops.acquire(hw); |
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if (ret_val) |
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return ret_val; |
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ret_val = igb_ready_nvm_eeprom(hw); |
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if (ret_val) { |
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nvm->ops.release(hw); |
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return ret_val; |
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} |
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igb_standby_nvm(hw); |
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/* Send the WRITE ENABLE command (8 bit opcode) */ |
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igb_shift_out_eec_bits(hw, NVM_WREN_OPCODE_SPI, |
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nvm->opcode_bits); |
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igb_standby_nvm(hw); |
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/* Some SPI eeproms use the 8th address bit embedded in the |
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* opcode |
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*/ |
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if ((nvm->address_bits == 8) && (offset >= 128)) |
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write_opcode |= NVM_A8_OPCODE_SPI; |
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/* Send the Write command (8-bit opcode + addr) */ |
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igb_shift_out_eec_bits(hw, write_opcode, nvm->opcode_bits); |
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igb_shift_out_eec_bits(hw, (u16)((offset + widx) * 2), |
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nvm->address_bits); |
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|
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/* Loop to allow for up to whole page write of eeprom */ |
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while (widx < words) { |
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u16 word_out = data[widx]; |
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word_out = (word_out >> 8) | (word_out << 8); |
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igb_shift_out_eec_bits(hw, word_out, 16); |
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widx++; |
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if ((((offset + widx) * 2) % nvm->page_size) == 0) { |
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igb_standby_nvm(hw); |
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break; |
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} |
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} |
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usleep_range(1000, 2000); |
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nvm->ops.release(hw); |
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} |
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return ret_val; |
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} |
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/** |
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* igb_read_part_string - Read device part number |
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* @hw: pointer to the HW structure |
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* @part_num: pointer to device part number |
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* @part_num_size: size of part number buffer |
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* |
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* Reads the product board assembly (PBA) number from the EEPROM and stores |
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* the value in part_num. |
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**/ |
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s32 igb_read_part_string(struct e1000_hw *hw, u8 *part_num, u32 part_num_size) |
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{ |
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s32 ret_val; |
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u16 nvm_data; |
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u16 pointer; |
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u16 offset; |
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u16 length; |
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if (part_num == NULL) { |
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hw_dbg("PBA string buffer was null\n"); |
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ret_val = E1000_ERR_INVALID_ARGUMENT; |
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goto out; |
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} |
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ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_0, 1, &nvm_data); |
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if (ret_val) { |
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hw_dbg("NVM Read Error\n"); |
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goto out; |
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} |
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ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_1, 1, &pointer); |
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if (ret_val) { |
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hw_dbg("NVM Read Error\n"); |
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goto out; |
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} |
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|
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/* if nvm_data is not ptr guard the PBA must be in legacy format which |
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* means pointer is actually our second data word for the PBA number |
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* and we can decode it into an ascii string |
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*/ |
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if (nvm_data != NVM_PBA_PTR_GUARD) { |
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hw_dbg("NVM PBA number is not stored as string\n"); |
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/* we will need 11 characters to store the PBA */ |
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if (part_num_size < 11) { |
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hw_dbg("PBA string buffer too small\n"); |
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return E1000_ERR_NO_SPACE; |
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} |
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/* extract hex string from data and pointer */ |
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part_num[0] = (nvm_data >> 12) & 0xF; |
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part_num[1] = (nvm_data >> 8) & 0xF; |
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part_num[2] = (nvm_data >> 4) & 0xF; |
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part_num[3] = nvm_data & 0xF; |
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part_num[4] = (pointer >> 12) & 0xF; |
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part_num[5] = (pointer >> 8) & 0xF; |
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part_num[6] = '-'; |
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part_num[7] = 0; |
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part_num[8] = (pointer >> 4) & 0xF; |
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part_num[9] = pointer & 0xF; |
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/* put a null character on the end of our string */ |
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part_num[10] = '\0'; |
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/* switch all the data but the '-' to hex char */ |
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for (offset = 0; offset < 10; offset++) { |
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if (part_num[offset] < 0xA) |
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part_num[offset] += '0'; |
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else if (part_num[offset] < 0x10) |
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part_num[offset] += 'A' - 0xA; |
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} |
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goto out; |
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} |
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ret_val = hw->nvm.ops.read(hw, pointer, 1, &length); |
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if (ret_val) { |
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hw_dbg("NVM Read Error\n"); |
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goto out; |
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} |
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|
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if (length == 0xFFFF || length == 0) { |
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hw_dbg("NVM PBA number section invalid length\n"); |
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ret_val = E1000_ERR_NVM_PBA_SECTION; |
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goto out; |
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} |
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/* check if part_num buffer is big enough */ |
|
if (part_num_size < (((u32)length * 2) - 1)) { |
|
hw_dbg("PBA string buffer too small\n"); |
|
ret_val = E1000_ERR_NO_SPACE; |
|
goto out; |
|
} |
|
|
|
/* trim pba length from start of string */ |
|
pointer++; |
|
length--; |
|
|
|
for (offset = 0; offset < length; offset++) { |
|
ret_val = hw->nvm.ops.read(hw, pointer + offset, 1, &nvm_data); |
|
if (ret_val) { |
|
hw_dbg("NVM Read Error\n"); |
|
goto out; |
|
} |
|
part_num[offset * 2] = (u8)(nvm_data >> 8); |
|
part_num[(offset * 2) + 1] = (u8)(nvm_data & 0xFF); |
|
} |
|
part_num[offset * 2] = '\0'; |
|
|
|
out: |
|
return ret_val; |
|
} |
|
|
|
/** |
|
* igb_read_mac_addr - Read device MAC address |
|
* @hw: pointer to the HW structure |
|
* |
|
* Reads the device MAC address from the EEPROM and stores the value. |
|
* Since devices with two ports use the same EEPROM, we increment the |
|
* last bit in the MAC address for the second port. |
|
**/ |
|
s32 igb_read_mac_addr(struct e1000_hw *hw) |
|
{ |
|
u32 rar_high; |
|
u32 rar_low; |
|
u16 i; |
|
|
|
rar_high = rd32(E1000_RAH(0)); |
|
rar_low = rd32(E1000_RAL(0)); |
|
|
|
for (i = 0; i < E1000_RAL_MAC_ADDR_LEN; i++) |
|
hw->mac.perm_addr[i] = (u8)(rar_low >> (i*8)); |
|
|
|
for (i = 0; i < E1000_RAH_MAC_ADDR_LEN; i++) |
|
hw->mac.perm_addr[i+4] = (u8)(rar_high >> (i*8)); |
|
|
|
for (i = 0; i < ETH_ALEN; i++) |
|
hw->mac.addr[i] = hw->mac.perm_addr[i]; |
|
|
|
return 0; |
|
} |
|
|
|
/** |
|
* igb_validate_nvm_checksum - Validate EEPROM checksum |
|
* @hw: pointer to the HW structure |
|
* |
|
* Calculates the EEPROM checksum by reading/adding each word of the EEPROM |
|
* and then verifies that the sum of the EEPROM is equal to 0xBABA. |
|
**/ |
|
s32 igb_validate_nvm_checksum(struct e1000_hw *hw) |
|
{ |
|
s32 ret_val = 0; |
|
u16 checksum = 0; |
|
u16 i, nvm_data; |
|
|
|
for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) { |
|
ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data); |
|
if (ret_val) { |
|
hw_dbg("NVM Read Error\n"); |
|
goto out; |
|
} |
|
checksum += nvm_data; |
|
} |
|
|
|
if (checksum != (u16) NVM_SUM) { |
|
hw_dbg("NVM Checksum Invalid\n"); |
|
ret_val = -E1000_ERR_NVM; |
|
goto out; |
|
} |
|
|
|
out: |
|
return ret_val; |
|
} |
|
|
|
/** |
|
* igb_update_nvm_checksum - Update EEPROM checksum |
|
* @hw: pointer to the HW structure |
|
* |
|
* Updates the EEPROM checksum by reading/adding each word of the EEPROM |
|
* up to the checksum. Then calculates the EEPROM checksum and writes the |
|
* value to the EEPROM. |
|
**/ |
|
s32 igb_update_nvm_checksum(struct e1000_hw *hw) |
|
{ |
|
s32 ret_val; |
|
u16 checksum = 0; |
|
u16 i, nvm_data; |
|
|
|
for (i = 0; i < NVM_CHECKSUM_REG; i++) { |
|
ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data); |
|
if (ret_val) { |
|
hw_dbg("NVM Read Error while updating checksum.\n"); |
|
goto out; |
|
} |
|
checksum += nvm_data; |
|
} |
|
checksum = (u16) NVM_SUM - checksum; |
|
ret_val = hw->nvm.ops.write(hw, NVM_CHECKSUM_REG, 1, &checksum); |
|
if (ret_val) |
|
hw_dbg("NVM Write Error while updating checksum.\n"); |
|
|
|
out: |
|
return ret_val; |
|
} |
|
|
|
/** |
|
* igb_get_fw_version - Get firmware version information |
|
* @hw: pointer to the HW structure |
|
* @fw_vers: pointer to output structure |
|
* |
|
* unsupported MAC types will return all 0 version structure |
|
**/ |
|
void igb_get_fw_version(struct e1000_hw *hw, struct e1000_fw_version *fw_vers) |
|
{ |
|
u16 eeprom_verh, eeprom_verl, etrack_test, fw_version; |
|
u8 q, hval, rem, result; |
|
u16 comb_verh, comb_verl, comb_offset; |
|
|
|
memset(fw_vers, 0, sizeof(struct e1000_fw_version)); |
|
|
|
/* basic eeprom version numbers and bits used vary by part and by tool |
|
* used to create the nvm images. Check which data format we have. |
|
*/ |
|
hw->nvm.ops.read(hw, NVM_ETRACK_HIWORD, 1, &etrack_test); |
|
switch (hw->mac.type) { |
|
case e1000_i211: |
|
igb_read_invm_version(hw, fw_vers); |
|
return; |
|
case e1000_82575: |
|
case e1000_82576: |
|
case e1000_82580: |
|
/* Use this format, unless EETRACK ID exists, |
|
* then use alternate format |
|
*/ |
|
if ((etrack_test & NVM_MAJOR_MASK) != NVM_ETRACK_VALID) { |
|
hw->nvm.ops.read(hw, NVM_VERSION, 1, &fw_version); |
|
fw_vers->eep_major = (fw_version & NVM_MAJOR_MASK) |
|
>> NVM_MAJOR_SHIFT; |
|
fw_vers->eep_minor = (fw_version & NVM_MINOR_MASK) |
|
>> NVM_MINOR_SHIFT; |
|
fw_vers->eep_build = (fw_version & NVM_IMAGE_ID_MASK); |
|
goto etrack_id; |
|
} |
|
break; |
|
case e1000_i210: |
|
if (!(igb_get_flash_presence_i210(hw))) { |
|
igb_read_invm_version(hw, fw_vers); |
|
return; |
|
} |
|
fallthrough; |
|
case e1000_i350: |
|
/* find combo image version */ |
|
hw->nvm.ops.read(hw, NVM_COMB_VER_PTR, 1, &comb_offset); |
|
if ((comb_offset != 0x0) && |
|
(comb_offset != NVM_VER_INVALID)) { |
|
|
|
hw->nvm.ops.read(hw, (NVM_COMB_VER_OFF + comb_offset |
|
+ 1), 1, &comb_verh); |
|
hw->nvm.ops.read(hw, (NVM_COMB_VER_OFF + comb_offset), |
|
1, &comb_verl); |
|
|
|
/* get Option Rom version if it exists and is valid */ |
|
if ((comb_verh && comb_verl) && |
|
((comb_verh != NVM_VER_INVALID) && |
|
(comb_verl != NVM_VER_INVALID))) { |
|
|
|
fw_vers->or_valid = true; |
|
fw_vers->or_major = |
|
comb_verl >> NVM_COMB_VER_SHFT; |
|
fw_vers->or_build = |
|
(comb_verl << NVM_COMB_VER_SHFT) |
|
| (comb_verh >> NVM_COMB_VER_SHFT); |
|
fw_vers->or_patch = |
|
comb_verh & NVM_COMB_VER_MASK; |
|
} |
|
} |
|
break; |
|
default: |
|
return; |
|
} |
|
hw->nvm.ops.read(hw, NVM_VERSION, 1, &fw_version); |
|
fw_vers->eep_major = (fw_version & NVM_MAJOR_MASK) |
|
>> NVM_MAJOR_SHIFT; |
|
|
|
/* check for old style version format in newer images*/ |
|
if ((fw_version & NVM_NEW_DEC_MASK) == 0x0) { |
|
eeprom_verl = (fw_version & NVM_COMB_VER_MASK); |
|
} else { |
|
eeprom_verl = (fw_version & NVM_MINOR_MASK) |
|
>> NVM_MINOR_SHIFT; |
|
} |
|
/* Convert minor value to hex before assigning to output struct |
|
* Val to be converted will not be higher than 99, per tool output |
|
*/ |
|
q = eeprom_verl / NVM_HEX_CONV; |
|
hval = q * NVM_HEX_TENS; |
|
rem = eeprom_verl % NVM_HEX_CONV; |
|
result = hval + rem; |
|
fw_vers->eep_minor = result; |
|
|
|
etrack_id: |
|
if ((etrack_test & NVM_MAJOR_MASK) == NVM_ETRACK_VALID) { |
|
hw->nvm.ops.read(hw, NVM_ETRACK_WORD, 1, &eeprom_verl); |
|
hw->nvm.ops.read(hw, (NVM_ETRACK_WORD + 1), 1, &eeprom_verh); |
|
fw_vers->etrack_id = (eeprom_verh << NVM_ETRACK_SHIFT) |
|
| eeprom_verl; |
|
} |
|
}
|
|
|