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651 lines
18 KiB
651 lines
18 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* Copyright (C) 2021, Intel Corporation. */ |
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|
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#include "ice_common.h" |
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#include "ice_ptp_hw.h" |
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|
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/* Low level functions for interacting with and managing the device clock used |
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* for the Precision Time Protocol. |
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* |
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* The ice hardware represents the current time using three registers: |
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* |
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* GLTSYN_TIME_H GLTSYN_TIME_L GLTSYN_TIME_R |
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* +---------------+ +---------------+ +---------------+ |
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* | 32 bits | | 32 bits | | 32 bits | |
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* +---------------+ +---------------+ +---------------+ |
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* |
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* The registers are incremented every clock tick using a 40bit increment |
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* value defined over two registers: |
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* |
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* GLTSYN_INCVAL_H GLTSYN_INCVAL_L |
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* +---------------+ +---------------+ |
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* | 8 bit s | | 32 bits | |
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* +---------------+ +---------------+ |
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* |
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* The increment value is added to the GLSTYN_TIME_R and GLSTYN_TIME_L |
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* registers every clock source tick. Depending on the specific device |
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* configuration, the clock source frequency could be one of a number of |
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* values. |
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* |
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* For E810 devices, the increment frequency is 812.5 MHz |
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* |
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* The hardware captures timestamps in the PHY for incoming packets, and for |
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* outgoing packets on request. To support this, the PHY maintains a timer |
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* that matches the lower 64 bits of the global source timer. |
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* |
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* In order to ensure that the PHY timers and the source timer are equivalent, |
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* shadow registers are used to prepare the desired initial values. A special |
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* sync command is issued to trigger copying from the shadow registers into |
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* the appropriate source and PHY registers simultaneously. |
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*/ |
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/** |
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* ice_get_ptp_src_clock_index - determine source clock index |
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* @hw: pointer to HW struct |
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* |
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* Determine the source clock index currently in use, based on device |
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* capabilities reported during initialization. |
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*/ |
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u8 ice_get_ptp_src_clock_index(struct ice_hw *hw) |
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{ |
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return hw->func_caps.ts_func_info.tmr_index_assoc; |
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} |
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|
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/* E810 functions |
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* |
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* The following functions operate on the E810 series devices which use |
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* a separate external PHY. |
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*/ |
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/** |
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* ice_read_phy_reg_e810 - Read register from external PHY on E810 |
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* @hw: pointer to the HW struct |
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* @addr: the address to read from |
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* @val: On return, the value read from the PHY |
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* |
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* Read a register from the external PHY on the E810 device. |
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*/ |
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static int ice_read_phy_reg_e810(struct ice_hw *hw, u32 addr, u32 *val) |
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{ |
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struct ice_sbq_msg_input msg = {0}; |
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int status; |
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msg.msg_addr_low = lower_16_bits(addr); |
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msg.msg_addr_high = upper_16_bits(addr); |
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msg.opcode = ice_sbq_msg_rd; |
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msg.dest_dev = rmn_0; |
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status = ice_sbq_rw_reg(hw, &msg); |
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if (status) { |
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ice_debug(hw, ICE_DBG_PTP, "Failed to send message to PHY, status %d\n", |
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status); |
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return status; |
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} |
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*val = msg.data; |
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return 0; |
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} |
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/** |
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* ice_write_phy_reg_e810 - Write register on external PHY on E810 |
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* @hw: pointer to the HW struct |
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* @addr: the address to writem to |
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* @val: the value to write to the PHY |
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* |
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* Write a value to a register of the external PHY on the E810 device. |
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*/ |
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static int ice_write_phy_reg_e810(struct ice_hw *hw, u32 addr, u32 val) |
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{ |
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struct ice_sbq_msg_input msg = {0}; |
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int status; |
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msg.msg_addr_low = lower_16_bits(addr); |
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msg.msg_addr_high = upper_16_bits(addr); |
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msg.opcode = ice_sbq_msg_wr; |
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msg.dest_dev = rmn_0; |
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msg.data = val; |
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status = ice_sbq_rw_reg(hw, &msg); |
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if (status) { |
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ice_debug(hw, ICE_DBG_PTP, "Failed to send message to PHY, status %d\n", |
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status); |
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return status; |
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} |
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return 0; |
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} |
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/** |
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* ice_read_phy_tstamp_e810 - Read a PHY timestamp out of the external PHY |
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* @hw: pointer to the HW struct |
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* @lport: the lport to read from |
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* @idx: the timestamp index to read |
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* @tstamp: on return, the 40bit timestamp value |
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* |
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* Read a 40bit timestamp value out of the timestamp block of the external PHY |
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* on the E810 device. |
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*/ |
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static int |
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ice_read_phy_tstamp_e810(struct ice_hw *hw, u8 lport, u8 idx, u64 *tstamp) |
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{ |
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u32 lo_addr, hi_addr, lo, hi; |
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int status; |
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lo_addr = TS_EXT(LOW_TX_MEMORY_BANK_START, lport, idx); |
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hi_addr = TS_EXT(HIGH_TX_MEMORY_BANK_START, lport, idx); |
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status = ice_read_phy_reg_e810(hw, lo_addr, &lo); |
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if (status) { |
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ice_debug(hw, ICE_DBG_PTP, "Failed to read low PTP timestamp register, status %d\n", |
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status); |
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return status; |
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} |
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status = ice_read_phy_reg_e810(hw, hi_addr, &hi); |
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if (status) { |
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ice_debug(hw, ICE_DBG_PTP, "Failed to read high PTP timestamp register, status %d\n", |
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status); |
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return status; |
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} |
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/* For E810 devices, the timestamp is reported with the lower 32 bits |
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* in the low register, and the upper 8 bits in the high register. |
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*/ |
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*tstamp = ((u64)hi) << TS_HIGH_S | ((u64)lo & TS_LOW_M); |
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return 0; |
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} |
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/** |
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* ice_clear_phy_tstamp_e810 - Clear a timestamp from the external PHY |
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* @hw: pointer to the HW struct |
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* @lport: the lport to read from |
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* @idx: the timestamp index to reset |
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* |
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* Clear a timestamp, resetting its valid bit, from the timestamp block of the |
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* external PHY on the E810 device. |
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*/ |
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static int ice_clear_phy_tstamp_e810(struct ice_hw *hw, u8 lport, u8 idx) |
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{ |
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u32 lo_addr, hi_addr; |
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int status; |
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lo_addr = TS_EXT(LOW_TX_MEMORY_BANK_START, lport, idx); |
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hi_addr = TS_EXT(HIGH_TX_MEMORY_BANK_START, lport, idx); |
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status = ice_write_phy_reg_e810(hw, lo_addr, 0); |
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if (status) { |
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ice_debug(hw, ICE_DBG_PTP, "Failed to clear low PTP timestamp register, status %d\n", |
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status); |
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return status; |
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} |
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status = ice_write_phy_reg_e810(hw, hi_addr, 0); |
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if (status) { |
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ice_debug(hw, ICE_DBG_PTP, "Failed to clear high PTP timestamp register, status %d\n", |
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status); |
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return status; |
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} |
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return 0; |
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} |
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/** |
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* ice_ptp_init_phy_e810 - Enable PTP function on the external PHY |
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* @hw: pointer to HW struct |
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* |
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* Enable the timesync PTP functionality for the external PHY connected to |
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* this function. |
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*/ |
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int ice_ptp_init_phy_e810(struct ice_hw *hw) |
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{ |
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int status; |
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u8 tmr_idx; |
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tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned; |
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status = ice_write_phy_reg_e810(hw, ETH_GLTSYN_ENA(tmr_idx), |
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GLTSYN_ENA_TSYN_ENA_M); |
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if (status) |
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ice_debug(hw, ICE_DBG_PTP, "PTP failed in ena_phy_time_syn %d\n", |
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status); |
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return status; |
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} |
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/** |
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* ice_ptp_prep_phy_time_e810 - Prepare PHY port with initial time |
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* @hw: Board private structure |
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* @time: Time to initialize the PHY port clock to |
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* |
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* Program the PHY port ETH_GLTSYN_SHTIME registers in preparation setting the |
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* initial clock time. The time will not actually be programmed until the |
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* driver issues an INIT_TIME command. |
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* |
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* The time value is the upper 32 bits of the PHY timer, usually in units of |
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* nominal nanoseconds. |
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*/ |
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static int ice_ptp_prep_phy_time_e810(struct ice_hw *hw, u32 time) |
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{ |
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int status; |
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u8 tmr_idx; |
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tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned; |
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status = ice_write_phy_reg_e810(hw, ETH_GLTSYN_SHTIME_0(tmr_idx), 0); |
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if (status) { |
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ice_debug(hw, ICE_DBG_PTP, "Failed to write SHTIME_0, status %d\n", |
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status); |
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return status; |
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} |
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status = ice_write_phy_reg_e810(hw, ETH_GLTSYN_SHTIME_L(tmr_idx), time); |
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if (status) { |
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ice_debug(hw, ICE_DBG_PTP, "Failed to write SHTIME_L, status %d\n", |
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status); |
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return status; |
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} |
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return 0; |
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} |
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/** |
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* ice_ptp_prep_phy_adj_e810 - Prep PHY port for a time adjustment |
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* @hw: pointer to HW struct |
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* @adj: adjustment value to program |
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* |
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* Prepare the PHY port for an atomic adjustment by programming the PHY |
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* ETH_GLTSYN_SHADJ_L and ETH_GLTSYN_SHADJ_H registers. The actual adjustment |
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* is completed by issuing an ADJ_TIME sync command. |
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* |
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* The adjustment value only contains the portion used for the upper 32bits of |
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* the PHY timer, usually in units of nominal nanoseconds. Negative |
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* adjustments are supported using 2s complement arithmetic. |
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*/ |
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static int ice_ptp_prep_phy_adj_e810(struct ice_hw *hw, s32 adj) |
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{ |
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int status; |
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u8 tmr_idx; |
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tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned; |
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/* Adjustments are represented as signed 2's complement values in |
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* nanoseconds. Sub-nanosecond adjustment is not supported. |
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*/ |
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status = ice_write_phy_reg_e810(hw, ETH_GLTSYN_SHADJ_L(tmr_idx), 0); |
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if (status) { |
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ice_debug(hw, ICE_DBG_PTP, "Failed to write adj to PHY SHADJ_L, status %d\n", |
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status); |
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return status; |
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} |
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status = ice_write_phy_reg_e810(hw, ETH_GLTSYN_SHADJ_H(tmr_idx), adj); |
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if (status) { |
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ice_debug(hw, ICE_DBG_PTP, "Failed to write adj to PHY SHADJ_H, status %d\n", |
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status); |
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return status; |
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} |
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return 0; |
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} |
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/** |
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* ice_ptp_prep_phy_incval_e810 - Prep PHY port increment value change |
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* @hw: pointer to HW struct |
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* @incval: The new 40bit increment value to prepare |
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* |
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* Prepare the PHY port for a new increment value by programming the PHY |
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* ETH_GLTSYN_SHADJ_L and ETH_GLTSYN_SHADJ_H registers. The actual change is |
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* completed by issuing an INIT_INCVAL command. |
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*/ |
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static int ice_ptp_prep_phy_incval_e810(struct ice_hw *hw, u64 incval) |
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{ |
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u32 high, low; |
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int status; |
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u8 tmr_idx; |
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tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned; |
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low = lower_32_bits(incval); |
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high = upper_32_bits(incval); |
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status = ice_write_phy_reg_e810(hw, ETH_GLTSYN_SHADJ_L(tmr_idx), low); |
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if (status) { |
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ice_debug(hw, ICE_DBG_PTP, "Failed to write incval to PHY SHADJ_L, status %d\n", |
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status); |
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return status; |
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} |
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status = ice_write_phy_reg_e810(hw, ETH_GLTSYN_SHADJ_H(tmr_idx), high); |
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if (status) { |
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ice_debug(hw, ICE_DBG_PTP, "Failed to write incval PHY SHADJ_H, status %d\n", |
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status); |
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return status; |
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} |
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return 0; |
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} |
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/** |
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* ice_ptp_port_cmd_e810 - Prepare all external PHYs for a timer command |
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* @hw: pointer to HW struct |
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* @cmd: Command to be sent to the port |
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* |
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* Prepare the external PHYs connected to this device for a timer sync |
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* command. |
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*/ |
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static int ice_ptp_port_cmd_e810(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd) |
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{ |
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u32 cmd_val, val; |
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int status; |
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switch (cmd) { |
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case INIT_TIME: |
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cmd_val = GLTSYN_CMD_INIT_TIME; |
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break; |
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case INIT_INCVAL: |
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cmd_val = GLTSYN_CMD_INIT_INCVAL; |
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break; |
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case ADJ_TIME: |
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cmd_val = GLTSYN_CMD_ADJ_TIME; |
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break; |
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case READ_TIME: |
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cmd_val = GLTSYN_CMD_READ_TIME; |
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break; |
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case ADJ_TIME_AT_TIME: |
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cmd_val = GLTSYN_CMD_ADJ_INIT_TIME; |
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break; |
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} |
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/* Read, modify, write */ |
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status = ice_read_phy_reg_e810(hw, ETH_GLTSYN_CMD, &val); |
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if (status) { |
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ice_debug(hw, ICE_DBG_PTP, "Failed to read GLTSYN_CMD, status %d\n", status); |
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return status; |
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} |
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/* Modify necessary bits only and perform write */ |
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val &= ~TS_CMD_MASK_E810; |
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val |= cmd_val; |
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status = ice_write_phy_reg_e810(hw, ETH_GLTSYN_CMD, val); |
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if (status) { |
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ice_debug(hw, ICE_DBG_PTP, "Failed to write back GLTSYN_CMD, status %d\n", status); |
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return status; |
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} |
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return 0; |
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} |
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/* Device agnostic functions |
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* |
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* The following functions implement useful behavior to hide the differences |
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* between E810 and other devices. They call the device-specific |
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* implementations where necessary. |
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* |
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* Currently, the driver only supports E810, but future work will enable |
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* support for E822-based devices. |
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*/ |
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/** |
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* ice_ptp_lock - Acquire PTP global semaphore register lock |
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* @hw: pointer to the HW struct |
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* |
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* Acquire the global PTP hardware semaphore lock. Returns true if the lock |
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* was acquired, false otherwise. |
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* |
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* The PFTSYN_SEM register sets the busy bit on read, returning the previous |
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* value. If software sees the busy bit cleared, this means that this function |
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* acquired the lock (and the busy bit is now set). If software sees the busy |
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* bit set, it means that another function acquired the lock. |
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* |
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* Software must clear the busy bit with a write to release the lock for other |
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* functions when done. |
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*/ |
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bool ice_ptp_lock(struct ice_hw *hw) |
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{ |
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u32 hw_lock; |
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int i; |
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#define MAX_TRIES 5 |
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for (i = 0; i < MAX_TRIES; i++) { |
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hw_lock = rd32(hw, PFTSYN_SEM + (PFTSYN_SEM_BYTES * hw->pf_id)); |
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hw_lock = hw_lock & PFTSYN_SEM_BUSY_M; |
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if (!hw_lock) |
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break; |
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/* Somebody is holding the lock */ |
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usleep_range(10000, 20000); |
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} |
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return !hw_lock; |
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} |
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/** |
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* ice_ptp_unlock - Release PTP global semaphore register lock |
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* @hw: pointer to the HW struct |
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* |
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* Release the global PTP hardware semaphore lock. This is done by writing to |
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* the PFTSYN_SEM register. |
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*/ |
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void ice_ptp_unlock(struct ice_hw *hw) |
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{ |
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wr32(hw, PFTSYN_SEM + (PFTSYN_SEM_BYTES * hw->pf_id), 0); |
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} |
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/** |
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* ice_ptp_src_cmd - Prepare source timer for a timer command |
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* @hw: pointer to HW structure |
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* @cmd: Timer command |
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* |
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* Prepare the source timer for an upcoming timer sync command. |
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*/ |
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static void ice_ptp_src_cmd(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd) |
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{ |
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u32 cmd_val; |
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u8 tmr_idx; |
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tmr_idx = ice_get_ptp_src_clock_index(hw); |
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cmd_val = tmr_idx << SEL_CPK_SRC; |
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switch (cmd) { |
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case INIT_TIME: |
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cmd_val |= GLTSYN_CMD_INIT_TIME; |
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break; |
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case INIT_INCVAL: |
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cmd_val |= GLTSYN_CMD_INIT_INCVAL; |
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break; |
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case ADJ_TIME: |
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cmd_val |= GLTSYN_CMD_ADJ_TIME; |
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break; |
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case ADJ_TIME_AT_TIME: |
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cmd_val |= GLTSYN_CMD_ADJ_INIT_TIME; |
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break; |
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case READ_TIME: |
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cmd_val |= GLTSYN_CMD_READ_TIME; |
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break; |
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} |
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wr32(hw, GLTSYN_CMD, cmd_val); |
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} |
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/** |
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* ice_ptp_tmr_cmd - Prepare and trigger a timer sync command |
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* @hw: pointer to HW struct |
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* @cmd: the command to issue |
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* |
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* Prepare the source timer and PHY timers and then trigger the requested |
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* command. This causes the shadow registers previously written in preparation |
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* for the command to be synchronously applied to both the source and PHY |
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* timers. |
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*/ |
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static int ice_ptp_tmr_cmd(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd) |
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{ |
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int status; |
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|
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/* First, prepare the source timer */ |
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ice_ptp_src_cmd(hw, cmd); |
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|
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/* Next, prepare the ports */ |
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status = ice_ptp_port_cmd_e810(hw, cmd); |
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if (status) { |
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ice_debug(hw, ICE_DBG_PTP, "Failed to prepare PHY ports for timer command %u, status %d\n", |
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cmd, status); |
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return status; |
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} |
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|
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/* Write the sync command register to drive both source and PHY timer commands |
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* synchronously |
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*/ |
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wr32(hw, GLTSYN_CMD_SYNC, SYNC_EXEC_CMD); |
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|
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return 0; |
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} |
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|
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/** |
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* ice_ptp_init_time - Initialize device time to provided value |
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* @hw: pointer to HW struct |
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* @time: 64bits of time (GLTSYN_TIME_L and GLTSYN_TIME_H) |
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* |
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* Initialize the device to the specified time provided. This requires a three |
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* step process: |
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* |
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* 1) write the new init time to the source timer shadow registers |
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* 2) write the new init time to the PHY timer shadow registers |
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* 3) issue an init_time timer command to synchronously switch both the source |
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* and port timers to the new init time value at the next clock cycle. |
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*/ |
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int ice_ptp_init_time(struct ice_hw *hw, u64 time) |
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{ |
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int status; |
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u8 tmr_idx; |
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tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned; |
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/* Source timers */ |
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wr32(hw, GLTSYN_SHTIME_L(tmr_idx), lower_32_bits(time)); |
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wr32(hw, GLTSYN_SHTIME_H(tmr_idx), upper_32_bits(time)); |
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wr32(hw, GLTSYN_SHTIME_0(tmr_idx), 0); |
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/* PHY timers */ |
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/* Fill Rx and Tx ports and send msg to PHY */ |
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status = ice_ptp_prep_phy_time_e810(hw, time & 0xFFFFFFFF); |
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if (status) |
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return status; |
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return ice_ptp_tmr_cmd(hw, INIT_TIME); |
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} |
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|
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/** |
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* ice_ptp_write_incval - Program PHC with new increment value |
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* @hw: pointer to HW struct |
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* @incval: Source timer increment value per clock cycle |
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* |
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* Program the PHC with a new increment value. This requires a three-step |
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* process: |
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* |
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* 1) Write the increment value to the source timer shadow registers |
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* 2) Write the increment value to the PHY timer shadow registers |
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* 3) Issue an INIT_INCVAL timer command to synchronously switch both the |
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* source and port timers to the new increment value at the next clock |
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* cycle. |
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*/ |
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int ice_ptp_write_incval(struct ice_hw *hw, u64 incval) |
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{ |
|
int status; |
|
u8 tmr_idx; |
|
|
|
tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned; |
|
|
|
/* Shadow Adjust */ |
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wr32(hw, GLTSYN_SHADJ_L(tmr_idx), lower_32_bits(incval)); |
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wr32(hw, GLTSYN_SHADJ_H(tmr_idx), upper_32_bits(incval)); |
|
|
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status = ice_ptp_prep_phy_incval_e810(hw, incval); |
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if (status) |
|
return status; |
|
|
|
return ice_ptp_tmr_cmd(hw, INIT_INCVAL); |
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} |
|
|
|
/** |
|
* ice_ptp_write_incval_locked - Program new incval while holding semaphore |
|
* @hw: pointer to HW struct |
|
* @incval: Source timer increment value per clock cycle |
|
* |
|
* Program a new PHC incval while holding the PTP semaphore. |
|
*/ |
|
int ice_ptp_write_incval_locked(struct ice_hw *hw, u64 incval) |
|
{ |
|
int status; |
|
|
|
if (!ice_ptp_lock(hw)) |
|
return -EBUSY; |
|
|
|
status = ice_ptp_write_incval(hw, incval); |
|
|
|
ice_ptp_unlock(hw); |
|
|
|
return status; |
|
} |
|
|
|
/** |
|
* ice_ptp_adj_clock - Adjust PHC clock time atomically |
|
* @hw: pointer to HW struct |
|
* @adj: Adjustment in nanoseconds |
|
* |
|
* Perform an atomic adjustment of the PHC time by the specified number of |
|
* nanoseconds. This requires a three-step process: |
|
* |
|
* 1) Write the adjustment to the source timer shadow registers |
|
* 2) Write the adjustment to the PHY timer shadow registers |
|
* 3) Issue an ADJ_TIME timer command to synchronously apply the adjustment to |
|
* both the source and port timers at the next clock cycle. |
|
*/ |
|
int ice_ptp_adj_clock(struct ice_hw *hw, s32 adj) |
|
{ |
|
int status; |
|
u8 tmr_idx; |
|
|
|
tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned; |
|
|
|
/* Write the desired clock adjustment into the GLTSYN_SHADJ register. |
|
* For an ADJ_TIME command, this set of registers represents the value |
|
* to add to the clock time. It supports subtraction by interpreting |
|
* the value as a 2's complement integer. |
|
*/ |
|
wr32(hw, GLTSYN_SHADJ_L(tmr_idx), 0); |
|
wr32(hw, GLTSYN_SHADJ_H(tmr_idx), adj); |
|
|
|
status = ice_ptp_prep_phy_adj_e810(hw, adj); |
|
if (status) |
|
return status; |
|
|
|
return ice_ptp_tmr_cmd(hw, ADJ_TIME); |
|
} |
|
|
|
/** |
|
* ice_read_phy_tstamp - Read a PHY timestamp from the timestamo block |
|
* @hw: pointer to the HW struct |
|
* @block: the block to read from |
|
* @idx: the timestamp index to read |
|
* @tstamp: on return, the 40bit timestamp value |
|
* |
|
* Read a 40bit timestamp value out of the timestamp block. |
|
*/ |
|
int ice_read_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx, u64 *tstamp) |
|
{ |
|
return ice_read_phy_tstamp_e810(hw, block, idx, tstamp); |
|
} |
|
|
|
/** |
|
* ice_clear_phy_tstamp - Clear a timestamp from the timestamp block |
|
* @hw: pointer to the HW struct |
|
* @block: the block to read from |
|
* @idx: the timestamp index to reset |
|
* |
|
* Clear a timestamp, resetting its valid bit, from the timestamp block. |
|
*/ |
|
int ice_clear_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx) |
|
{ |
|
return ice_clear_phy_tstamp_e810(hw, block, idx); |
|
}
|
|
|