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100 lines
2.7 KiB
100 lines
2.7 KiB
/* SPDX-License-Identifier: GPL-2.0 */ |
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/* Copyright (c) 2018, Intel Corporation. */ |
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#ifndef _ICE_CONTROLQ_H_ |
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#define _ICE_CONTROLQ_H_ |
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#include "ice_adminq_cmd.h" |
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/* Maximum buffer lengths for all control queue types */ |
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#define ICE_AQ_MAX_BUF_LEN 4096 |
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#define ICE_MBXQ_MAX_BUF_LEN 4096 |
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#define ICE_SBQ_MAX_BUF_LEN 512 |
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#define ICE_CTL_Q_DESC(R, i) \ |
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(&(((struct ice_aq_desc *)((R).desc_buf.va))[i])) |
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#define ICE_CTL_Q_DESC_UNUSED(R) \ |
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((u16)((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \ |
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(R)->next_to_clean - (R)->next_to_use - 1)) |
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/* Defines that help manage the driver vs FW API checks. |
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* Take a look at ice_aq_ver_check in ice_controlq.c for actual usage. |
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*/ |
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#define EXP_FW_API_VER_BRANCH 0x00 |
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#define EXP_FW_API_VER_MAJOR 0x01 |
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#define EXP_FW_API_VER_MINOR 0x05 |
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/* Different control queue types: These are mainly for SW consumption. */ |
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enum ice_ctl_q { |
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ICE_CTL_Q_UNKNOWN = 0, |
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ICE_CTL_Q_ADMIN, |
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ICE_CTL_Q_MAILBOX, |
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ICE_CTL_Q_SB, |
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}; |
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/* Control Queue timeout settings - max delay 1s */ |
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#define ICE_CTL_Q_SQ_CMD_TIMEOUT 10000 /* Count 10000 times */ |
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#define ICE_CTL_Q_SQ_CMD_USEC 100 /* Check every 100usec */ |
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#define ICE_CTL_Q_ADMIN_INIT_TIMEOUT 10 /* Count 10 times */ |
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#define ICE_CTL_Q_ADMIN_INIT_MSEC 100 /* Check every 100msec */ |
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struct ice_ctl_q_ring { |
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void *dma_head; /* Virtual address to DMA head */ |
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struct ice_dma_mem desc_buf; /* descriptor ring memory */ |
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void *cmd_buf; /* command buffer memory */ |
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union { |
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struct ice_dma_mem *sq_bi; |
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struct ice_dma_mem *rq_bi; |
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} r; |
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u16 count; /* Number of descriptors */ |
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/* used for interrupt processing */ |
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u16 next_to_use; |
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u16 next_to_clean; |
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/* used for queue tracking */ |
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u32 head; |
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u32 tail; |
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u32 len; |
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u32 bah; |
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u32 bal; |
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u32 len_mask; |
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u32 len_ena_mask; |
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u32 len_crit_mask; |
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u32 head_mask; |
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}; |
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/* sq transaction details */ |
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struct ice_sq_cd { |
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struct ice_aq_desc *wb_desc; |
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}; |
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#define ICE_CTL_Q_DETAILS(R, i) (&(((struct ice_sq_cd *)((R).cmd_buf))[i])) |
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/* rq event information */ |
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struct ice_rq_event_info { |
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struct ice_aq_desc desc; |
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u16 msg_len; |
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u16 buf_len; |
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u8 *msg_buf; |
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}; |
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/* Control Queue information */ |
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struct ice_ctl_q_info { |
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enum ice_ctl_q qtype; |
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struct ice_ctl_q_ring rq; /* receive queue */ |
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struct ice_ctl_q_ring sq; /* send queue */ |
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u32 sq_cmd_timeout; /* send queue cmd write back timeout */ |
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u16 num_rq_entries; /* receive queue depth */ |
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u16 num_sq_entries; /* send queue depth */ |
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u16 rq_buf_size; /* receive queue buffer size */ |
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u16 sq_buf_size; /* send queue buffer size */ |
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enum ice_aq_err sq_last_status; /* last status on send queue */ |
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struct mutex sq_lock; /* Send queue lock */ |
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struct mutex rq_lock; /* Receive queue lock */ |
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}; |
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#endif /* _ICE_CONTROLQ_H_ */
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