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875 lines
27 KiB
875 lines
27 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* Copyright(c) 2013 - 2018 Intel Corporation. */ |
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|
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#include "i40e.h" |
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#include <linux/ptp_classify.h> |
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|
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/* The XL710 timesync is very much like Intel's 82599 design when it comes to |
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* the fundamental clock design. However, the clock operations are much simpler |
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* in the XL710 because the device supports a full 64 bits of nanoseconds. |
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* Because the field is so wide, we can forgo the cycle counter and just |
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* operate with the nanosecond field directly without fear of overflow. |
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* |
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* Much like the 82599, the update period is dependent upon the link speed: |
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* At 40Gb, 25Gb, or no link, the period is 1.6ns. |
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* At 10Gb or 5Gb link, the period is multiplied by 2. (3.2ns) |
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* At 1Gb link, the period is multiplied by 20. (32ns) |
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* 1588 functionality is not supported at 100Mbps. |
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*/ |
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#define I40E_PTP_40GB_INCVAL 0x0199999999ULL |
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#define I40E_PTP_10GB_INCVAL_MULT 2 |
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#define I40E_PTP_5GB_INCVAL_MULT 2 |
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#define I40E_PTP_1GB_INCVAL_MULT 20 |
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#define I40E_PRTTSYN_CTL1_TSYNTYPE_V1 BIT(I40E_PRTTSYN_CTL1_TSYNTYPE_SHIFT) |
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#define I40E_PRTTSYN_CTL1_TSYNTYPE_V2 (2 << \ |
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I40E_PRTTSYN_CTL1_TSYNTYPE_SHIFT) |
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|
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/** |
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* i40e_ptp_read - Read the PHC time from the device |
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* @pf: Board private structure |
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* @ts: timespec structure to hold the current time value |
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* @sts: structure to hold the system time before and after reading the PHC |
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* |
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* This function reads the PRTTSYN_TIME registers and stores them in a |
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* timespec. However, since the registers are 64 bits of nanoseconds, we must |
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* convert the result to a timespec before we can return. |
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**/ |
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static void i40e_ptp_read(struct i40e_pf *pf, struct timespec64 *ts, |
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struct ptp_system_timestamp *sts) |
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{ |
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struct i40e_hw *hw = &pf->hw; |
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u32 hi, lo; |
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u64 ns; |
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/* The timer latches on the lowest register read. */ |
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ptp_read_system_prets(sts); |
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lo = rd32(hw, I40E_PRTTSYN_TIME_L); |
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ptp_read_system_postts(sts); |
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hi = rd32(hw, I40E_PRTTSYN_TIME_H); |
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ns = (((u64)hi) << 32) | lo; |
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*ts = ns_to_timespec64(ns); |
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} |
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/** |
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* i40e_ptp_write - Write the PHC time to the device |
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* @pf: Board private structure |
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* @ts: timespec structure that holds the new time value |
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* |
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* This function writes the PRTTSYN_TIME registers with the user value. Since |
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* we receive a timespec from the stack, we must convert that timespec into |
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* nanoseconds before programming the registers. |
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**/ |
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static void i40e_ptp_write(struct i40e_pf *pf, const struct timespec64 *ts) |
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{ |
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struct i40e_hw *hw = &pf->hw; |
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u64 ns = timespec64_to_ns(ts); |
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/* The timer will not update until the high register is written, so |
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* write the low register first. |
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*/ |
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wr32(hw, I40E_PRTTSYN_TIME_L, ns & 0xFFFFFFFF); |
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wr32(hw, I40E_PRTTSYN_TIME_H, ns >> 32); |
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} |
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/** |
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* i40e_ptp_convert_to_hwtstamp - Convert device clock to system time |
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* @hwtstamps: Timestamp structure to update |
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* @timestamp: Timestamp from the hardware |
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* |
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* We need to convert the NIC clock value into a hwtstamp which can be used by |
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* the upper level timestamping functions. Since the timestamp is simply a 64- |
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* bit nanosecond value, we can call ns_to_ktime directly to handle this. |
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**/ |
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static void i40e_ptp_convert_to_hwtstamp(struct skb_shared_hwtstamps *hwtstamps, |
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u64 timestamp) |
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{ |
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memset(hwtstamps, 0, sizeof(*hwtstamps)); |
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hwtstamps->hwtstamp = ns_to_ktime(timestamp); |
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} |
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/** |
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* i40e_ptp_adjfreq - Adjust the PHC frequency |
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* @ptp: The PTP clock structure |
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* @ppb: Parts per billion adjustment from the base |
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* |
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* Adjust the frequency of the PHC by the indicated parts per billion from the |
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* base frequency. |
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**/ |
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static int i40e_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb) |
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{ |
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struct i40e_pf *pf = container_of(ptp, struct i40e_pf, ptp_caps); |
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struct i40e_hw *hw = &pf->hw; |
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u64 adj, freq, diff; |
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int neg_adj = 0; |
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if (ppb < 0) { |
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neg_adj = 1; |
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ppb = -ppb; |
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} |
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freq = I40E_PTP_40GB_INCVAL; |
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freq *= ppb; |
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diff = div_u64(freq, 1000000000ULL); |
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if (neg_adj) |
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adj = I40E_PTP_40GB_INCVAL - diff; |
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else |
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adj = I40E_PTP_40GB_INCVAL + diff; |
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/* At some link speeds, the base incval is so large that directly |
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* multiplying by ppb would result in arithmetic overflow even when |
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* using a u64. Avoid this by instead calculating the new incval |
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* always in terms of the 40GbE clock rate and then multiplying by the |
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* link speed factor afterwards. This does result in slightly lower |
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* precision at lower link speeds, but it is fairly minor. |
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*/ |
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smp_mb(); /* Force any pending update before accessing. */ |
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adj *= READ_ONCE(pf->ptp_adj_mult); |
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wr32(hw, I40E_PRTTSYN_INC_L, adj & 0xFFFFFFFF); |
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wr32(hw, I40E_PRTTSYN_INC_H, adj >> 32); |
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return 0; |
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} |
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/** |
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* i40e_ptp_adjtime - Adjust the PHC time |
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* @ptp: The PTP clock structure |
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* @delta: Offset in nanoseconds to adjust the PHC time by |
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* |
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* Adjust the current clock time by a delta specified in nanoseconds. |
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**/ |
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static int i40e_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta) |
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{ |
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struct i40e_pf *pf = container_of(ptp, struct i40e_pf, ptp_caps); |
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struct timespec64 now, then; |
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then = ns_to_timespec64(delta); |
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mutex_lock(&pf->tmreg_lock); |
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i40e_ptp_read(pf, &now, NULL); |
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now = timespec64_add(now, then); |
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i40e_ptp_write(pf, (const struct timespec64 *)&now); |
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mutex_unlock(&pf->tmreg_lock); |
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return 0; |
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} |
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/** |
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* i40e_ptp_gettimex - Get the time of the PHC |
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* @ptp: The PTP clock structure |
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* @ts: timespec structure to hold the current time value |
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* @sts: structure to hold the system time before and after reading the PHC |
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* |
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* Read the device clock and return the correct value on ns, after converting it |
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* into a timespec struct. |
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**/ |
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static int i40e_ptp_gettimex(struct ptp_clock_info *ptp, struct timespec64 *ts, |
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struct ptp_system_timestamp *sts) |
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{ |
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struct i40e_pf *pf = container_of(ptp, struct i40e_pf, ptp_caps); |
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mutex_lock(&pf->tmreg_lock); |
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i40e_ptp_read(pf, ts, sts); |
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mutex_unlock(&pf->tmreg_lock); |
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return 0; |
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} |
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/** |
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* i40e_ptp_settime - Set the time of the PHC |
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* @ptp: The PTP clock structure |
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* @ts: timespec structure that holds the new time value |
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* |
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* Set the device clock to the user input value. The conversion from timespec |
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* to ns happens in the write function. |
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**/ |
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static int i40e_ptp_settime(struct ptp_clock_info *ptp, |
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const struct timespec64 *ts) |
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{ |
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struct i40e_pf *pf = container_of(ptp, struct i40e_pf, ptp_caps); |
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mutex_lock(&pf->tmreg_lock); |
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i40e_ptp_write(pf, ts); |
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mutex_unlock(&pf->tmreg_lock); |
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return 0; |
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} |
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/** |
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* i40e_ptp_feature_enable - Enable/disable ancillary features of the PHC subsystem |
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* @ptp: The PTP clock structure |
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* @rq: The requested feature to change |
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* @on: Enable/disable flag |
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* |
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* The XL710 does not support any of the ancillary features of the PHC |
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* subsystem, so this function may just return. |
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**/ |
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static int i40e_ptp_feature_enable(struct ptp_clock_info *ptp, |
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struct ptp_clock_request *rq, int on) |
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{ |
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return -EOPNOTSUPP; |
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} |
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/** |
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* i40e_ptp_get_rx_events - Read I40E_PRTTSYN_STAT_1 and latch events |
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* @pf: the PF data structure |
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* |
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* This function reads I40E_PRTTSYN_STAT_1 and updates the corresponding timers |
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* for noticed latch events. This allows the driver to keep track of the first |
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* time a latch event was noticed which will be used to help clear out Rx |
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* timestamps for packets that got dropped or lost. |
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* |
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* This function will return the current value of I40E_PRTTSYN_STAT_1 and is |
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* expected to be called only while under the ptp_rx_lock. |
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**/ |
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static u32 i40e_ptp_get_rx_events(struct i40e_pf *pf) |
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{ |
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struct i40e_hw *hw = &pf->hw; |
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u32 prttsyn_stat, new_latch_events; |
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int i; |
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prttsyn_stat = rd32(hw, I40E_PRTTSYN_STAT_1); |
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new_latch_events = prttsyn_stat & ~pf->latch_event_flags; |
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/* Update the jiffies time for any newly latched timestamp. This |
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* ensures that we store the time that we first discovered a timestamp |
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* was latched by the hardware. The service task will later determine |
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* if we should free the latch and drop that timestamp should too much |
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* time pass. This flow ensures that we only update jiffies for new |
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* events latched since the last time we checked, and not all events |
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* currently latched, so that the service task accounting remains |
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* accurate. |
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*/ |
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for (i = 0; i < 4; i++) { |
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if (new_latch_events & BIT(i)) |
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pf->latch_events[i] = jiffies; |
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} |
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/* Finally, we store the current status of the Rx timestamp latches */ |
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pf->latch_event_flags = prttsyn_stat; |
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return prttsyn_stat; |
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} |
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/** |
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* i40e_ptp_rx_hang - Detect error case when Rx timestamp registers are hung |
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* @pf: The PF private data structure |
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* |
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* This watchdog task is scheduled to detect error case where hardware has |
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* dropped an Rx packet that was timestamped when the ring is full. The |
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* particular error is rare but leaves the device in a state unable to timestamp |
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* any future packets. |
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**/ |
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void i40e_ptp_rx_hang(struct i40e_pf *pf) |
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{ |
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struct i40e_hw *hw = &pf->hw; |
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unsigned int i, cleared = 0; |
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/* Since we cannot turn off the Rx timestamp logic if the device is |
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* configured for Tx timestamping, we check if Rx timestamping is |
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* configured. We don't want to spuriously warn about Rx timestamp |
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* hangs if we don't care about the timestamps. |
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*/ |
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if (!(pf->flags & I40E_FLAG_PTP) || !pf->ptp_rx) |
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return; |
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spin_lock_bh(&pf->ptp_rx_lock); |
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/* Update current latch times for Rx events */ |
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i40e_ptp_get_rx_events(pf); |
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/* Check all the currently latched Rx events and see whether they have |
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* been latched for over a second. It is assumed that any timestamp |
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* should have been cleared within this time, or else it was captured |
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* for a dropped frame that the driver never received. Thus, we will |
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* clear any timestamp that has been latched for over 1 second. |
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*/ |
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for (i = 0; i < 4; i++) { |
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if ((pf->latch_event_flags & BIT(i)) && |
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time_is_before_jiffies(pf->latch_events[i] + HZ)) { |
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rd32(hw, I40E_PRTTSYN_RXTIME_H(i)); |
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pf->latch_event_flags &= ~BIT(i); |
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cleared++; |
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} |
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} |
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spin_unlock_bh(&pf->ptp_rx_lock); |
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/* Log a warning if more than 2 timestamps got dropped in the same |
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* check. We don't want to warn about all drops because it can occur |
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* in normal scenarios such as PTP frames on multicast addresses we |
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* aren't listening to. However, administrator should know if this is |
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* the reason packets aren't receiving timestamps. |
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*/ |
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if (cleared > 2) |
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dev_dbg(&pf->pdev->dev, |
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"Dropped %d missed RXTIME timestamp events\n", |
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cleared); |
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/* Finally, update the rx_hwtstamp_cleared counter */ |
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pf->rx_hwtstamp_cleared += cleared; |
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} |
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/** |
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* i40e_ptp_tx_hang - Detect error case when Tx timestamp register is hung |
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* @pf: The PF private data structure |
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* |
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* This watchdog task is run periodically to make sure that we clear the Tx |
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* timestamp logic if we don't obtain a timestamp in a reasonable amount of |
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* time. It is unexpected in the normal case but if it occurs it results in |
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* permanently preventing timestamps of future packets. |
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**/ |
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void i40e_ptp_tx_hang(struct i40e_pf *pf) |
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{ |
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struct sk_buff *skb; |
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if (!(pf->flags & I40E_FLAG_PTP) || !pf->ptp_tx) |
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return; |
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/* Nothing to do if we're not already waiting for a timestamp */ |
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if (!test_bit(__I40E_PTP_TX_IN_PROGRESS, pf->state)) |
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return; |
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/* We already have a handler routine which is run when we are notified |
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* of a Tx timestamp in the hardware. If we don't get an interrupt |
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* within a second it is reasonable to assume that we never will. |
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*/ |
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if (time_is_before_jiffies(pf->ptp_tx_start + HZ)) { |
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skb = pf->ptp_tx_skb; |
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pf->ptp_tx_skb = NULL; |
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clear_bit_unlock(__I40E_PTP_TX_IN_PROGRESS, pf->state); |
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/* Free the skb after we clear the bitlock */ |
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dev_kfree_skb_any(skb); |
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pf->tx_hwtstamp_timeouts++; |
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} |
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} |
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/** |
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* i40e_ptp_tx_hwtstamp - Utility function which returns the Tx timestamp |
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* @pf: Board private structure |
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* |
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* Read the value of the Tx timestamp from the registers, convert it into a |
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* value consumable by the stack, and store that result into the shhwtstamps |
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* struct before returning it up the stack. |
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**/ |
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void i40e_ptp_tx_hwtstamp(struct i40e_pf *pf) |
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{ |
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struct skb_shared_hwtstamps shhwtstamps; |
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struct sk_buff *skb = pf->ptp_tx_skb; |
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struct i40e_hw *hw = &pf->hw; |
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u32 hi, lo; |
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u64 ns; |
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if (!(pf->flags & I40E_FLAG_PTP) || !pf->ptp_tx) |
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return; |
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/* don't attempt to timestamp if we don't have an skb */ |
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if (!pf->ptp_tx_skb) |
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return; |
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lo = rd32(hw, I40E_PRTTSYN_TXTIME_L); |
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hi = rd32(hw, I40E_PRTTSYN_TXTIME_H); |
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ns = (((u64)hi) << 32) | lo; |
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i40e_ptp_convert_to_hwtstamp(&shhwtstamps, ns); |
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/* Clear the bit lock as soon as possible after reading the register, |
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* and prior to notifying the stack via skb_tstamp_tx(). Otherwise |
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* applications might wake up and attempt to request another transmit |
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* timestamp prior to the bit lock being cleared. |
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*/ |
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pf->ptp_tx_skb = NULL; |
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clear_bit_unlock(__I40E_PTP_TX_IN_PROGRESS, pf->state); |
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/* Notify the stack and free the skb after we've unlocked */ |
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skb_tstamp_tx(skb, &shhwtstamps); |
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dev_kfree_skb_any(skb); |
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} |
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/** |
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* i40e_ptp_rx_hwtstamp - Utility function which checks for an Rx timestamp |
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* @pf: Board private structure |
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* @skb: Particular skb to send timestamp with |
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* @index: Index into the receive timestamp registers for the timestamp |
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* |
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* The XL710 receives a notification in the receive descriptor with an offset |
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* into the set of RXTIME registers where the timestamp is for that skb. This |
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* function goes and fetches the receive timestamp from that offset, if a valid |
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* one exists. The RXTIME registers are in ns, so we must convert the result |
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* first. |
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**/ |
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void i40e_ptp_rx_hwtstamp(struct i40e_pf *pf, struct sk_buff *skb, u8 index) |
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{ |
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u32 prttsyn_stat, hi, lo; |
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struct i40e_hw *hw; |
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u64 ns; |
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/* Since we cannot turn off the Rx timestamp logic if the device is |
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* doing Tx timestamping, check if Rx timestamping is configured. |
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*/ |
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if (!(pf->flags & I40E_FLAG_PTP) || !pf->ptp_rx) |
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return; |
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hw = &pf->hw; |
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spin_lock_bh(&pf->ptp_rx_lock); |
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/* Get current Rx events and update latch times */ |
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prttsyn_stat = i40e_ptp_get_rx_events(pf); |
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/* TODO: Should we warn about missing Rx timestamp event? */ |
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if (!(prttsyn_stat & BIT(index))) { |
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spin_unlock_bh(&pf->ptp_rx_lock); |
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return; |
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} |
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/* Clear the latched event since we're about to read its register */ |
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pf->latch_event_flags &= ~BIT(index); |
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lo = rd32(hw, I40E_PRTTSYN_RXTIME_L(index)); |
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hi = rd32(hw, I40E_PRTTSYN_RXTIME_H(index)); |
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spin_unlock_bh(&pf->ptp_rx_lock); |
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ns = (((u64)hi) << 32) | lo; |
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i40e_ptp_convert_to_hwtstamp(skb_hwtstamps(skb), ns); |
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} |
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/** |
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* i40e_ptp_set_increment - Utility function to update clock increment rate |
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* @pf: Board private structure |
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* |
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* During a link change, the DMA frequency that drives the 1588 logic will |
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* change. In order to keep the PRTTSYN_TIME registers in units of nanoseconds, |
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* we must update the increment value per clock tick. |
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**/ |
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void i40e_ptp_set_increment(struct i40e_pf *pf) |
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{ |
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struct i40e_link_status *hw_link_info; |
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struct i40e_hw *hw = &pf->hw; |
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u64 incval; |
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u32 mult; |
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hw_link_info = &hw->phy.link_info; |
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i40e_aq_get_link_info(&pf->hw, true, NULL, NULL); |
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switch (hw_link_info->link_speed) { |
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case I40E_LINK_SPEED_10GB: |
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mult = I40E_PTP_10GB_INCVAL_MULT; |
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break; |
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case I40E_LINK_SPEED_5GB: |
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mult = I40E_PTP_5GB_INCVAL_MULT; |
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break; |
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case I40E_LINK_SPEED_1GB: |
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mult = I40E_PTP_1GB_INCVAL_MULT; |
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break; |
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case I40E_LINK_SPEED_100MB: |
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{ |
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static int warn_once; |
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if (!warn_once) { |
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dev_warn(&pf->pdev->dev, |
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"1588 functionality is not supported at 100 Mbps. Stopping the PHC.\n"); |
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warn_once++; |
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} |
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mult = 0; |
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break; |
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} |
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case I40E_LINK_SPEED_40GB: |
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default: |
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mult = 1; |
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break; |
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} |
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|
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/* The increment value is calculated by taking the base 40GbE incvalue |
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* and multiplying it by a factor based on the link speed. |
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*/ |
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incval = I40E_PTP_40GB_INCVAL * mult; |
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|
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/* Write the new increment value into the increment register. The |
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* hardware will not update the clock until both registers have been |
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* written. |
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*/ |
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wr32(hw, I40E_PRTTSYN_INC_L, incval & 0xFFFFFFFF); |
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wr32(hw, I40E_PRTTSYN_INC_H, incval >> 32); |
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|
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/* Update the base adjustement value. */ |
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WRITE_ONCE(pf->ptp_adj_mult, mult); |
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smp_mb(); /* Force the above update. */ |
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} |
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|
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/** |
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* i40e_ptp_get_ts_config - ioctl interface to read the HW timestamping |
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* @pf: Board private structure |
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* @ifr: ioctl data |
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* |
|
* Obtain the current hardware timestamping settigs as requested. To do this, |
|
* keep a shadow copy of the timestamp settings rather than attempting to |
|
* deconstruct it from the registers. |
|
**/ |
|
int i40e_ptp_get_ts_config(struct i40e_pf *pf, struct ifreq *ifr) |
|
{ |
|
struct hwtstamp_config *config = &pf->tstamp_config; |
|
|
|
if (!(pf->flags & I40E_FLAG_PTP)) |
|
return -EOPNOTSUPP; |
|
|
|
return copy_to_user(ifr->ifr_data, config, sizeof(*config)) ? |
|
-EFAULT : 0; |
|
} |
|
|
|
/** |
|
* i40e_ptp_set_timestamp_mode - setup hardware for requested timestamp mode |
|
* @pf: Board private structure |
|
* @config: hwtstamp settings requested or saved |
|
* |
|
* Control hardware registers to enter the specific mode requested by the |
|
* user. Also used during reset path to ensure that timestamp settings are |
|
* maintained. |
|
* |
|
* Note: modifies config in place, and may update the requested mode to be |
|
* more broad if the specific filter is not directly supported. |
|
**/ |
|
static int i40e_ptp_set_timestamp_mode(struct i40e_pf *pf, |
|
struct hwtstamp_config *config) |
|
{ |
|
struct i40e_hw *hw = &pf->hw; |
|
u32 tsyntype, regval; |
|
|
|
/* Reserved for future extensions. */ |
|
if (config->flags) |
|
return -EINVAL; |
|
|
|
switch (config->tx_type) { |
|
case HWTSTAMP_TX_OFF: |
|
pf->ptp_tx = false; |
|
break; |
|
case HWTSTAMP_TX_ON: |
|
pf->ptp_tx = true; |
|
break; |
|
default: |
|
return -ERANGE; |
|
} |
|
|
|
switch (config->rx_filter) { |
|
case HWTSTAMP_FILTER_NONE: |
|
pf->ptp_rx = false; |
|
/* We set the type to V1, but do not enable UDP packet |
|
* recognition. In this way, we should be as close to |
|
* disabling PTP Rx timestamps as possible since V1 packets |
|
* are always UDP, since L2 packets are a V2 feature. |
|
*/ |
|
tsyntype = I40E_PRTTSYN_CTL1_TSYNTYPE_V1; |
|
break; |
|
case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: |
|
case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: |
|
case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: |
|
if (!(pf->hw_features & I40E_HW_PTP_L4_CAPABLE)) |
|
return -ERANGE; |
|
pf->ptp_rx = true; |
|
tsyntype = I40E_PRTTSYN_CTL1_V1MESSTYPE0_MASK | |
|
I40E_PRTTSYN_CTL1_TSYNTYPE_V1 | |
|
I40E_PRTTSYN_CTL1_UDP_ENA_MASK; |
|
config->rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT; |
|
break; |
|
case HWTSTAMP_FILTER_PTP_V2_EVENT: |
|
case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: |
|
case HWTSTAMP_FILTER_PTP_V2_SYNC: |
|
case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: |
|
case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: |
|
case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: |
|
if (!(pf->hw_features & I40E_HW_PTP_L4_CAPABLE)) |
|
return -ERANGE; |
|
fallthrough; |
|
case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: |
|
case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: |
|
case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: |
|
pf->ptp_rx = true; |
|
tsyntype = I40E_PRTTSYN_CTL1_V2MESSTYPE0_MASK | |
|
I40E_PRTTSYN_CTL1_TSYNTYPE_V2; |
|
if (pf->hw_features & I40E_HW_PTP_L4_CAPABLE) { |
|
tsyntype |= I40E_PRTTSYN_CTL1_UDP_ENA_MASK; |
|
config->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; |
|
} else { |
|
config->rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT; |
|
} |
|
break; |
|
case HWTSTAMP_FILTER_NTP_ALL: |
|
case HWTSTAMP_FILTER_ALL: |
|
default: |
|
return -ERANGE; |
|
} |
|
|
|
/* Clear out all 1588-related registers to clear and unlatch them. */ |
|
spin_lock_bh(&pf->ptp_rx_lock); |
|
rd32(hw, I40E_PRTTSYN_STAT_0); |
|
rd32(hw, I40E_PRTTSYN_TXTIME_H); |
|
rd32(hw, I40E_PRTTSYN_RXTIME_H(0)); |
|
rd32(hw, I40E_PRTTSYN_RXTIME_H(1)); |
|
rd32(hw, I40E_PRTTSYN_RXTIME_H(2)); |
|
rd32(hw, I40E_PRTTSYN_RXTIME_H(3)); |
|
pf->latch_event_flags = 0; |
|
spin_unlock_bh(&pf->ptp_rx_lock); |
|
|
|
/* Enable/disable the Tx timestamp interrupt based on user input. */ |
|
regval = rd32(hw, I40E_PRTTSYN_CTL0); |
|
if (pf->ptp_tx) |
|
regval |= I40E_PRTTSYN_CTL0_TXTIME_INT_ENA_MASK; |
|
else |
|
regval &= ~I40E_PRTTSYN_CTL0_TXTIME_INT_ENA_MASK; |
|
wr32(hw, I40E_PRTTSYN_CTL0, regval); |
|
|
|
regval = rd32(hw, I40E_PFINT_ICR0_ENA); |
|
if (pf->ptp_tx) |
|
regval |= I40E_PFINT_ICR0_ENA_TIMESYNC_MASK; |
|
else |
|
regval &= ~I40E_PFINT_ICR0_ENA_TIMESYNC_MASK; |
|
wr32(hw, I40E_PFINT_ICR0_ENA, regval); |
|
|
|
/* Although there is no simple on/off switch for Rx, we "disable" Rx |
|
* timestamps by setting to V1 only mode and clear the UDP |
|
* recognition. This ought to disable all PTP Rx timestamps as V1 |
|
* packets are always over UDP. Note that software is configured to |
|
* ignore Rx timestamps via the pf->ptp_rx flag. |
|
*/ |
|
regval = rd32(hw, I40E_PRTTSYN_CTL1); |
|
/* clear everything but the enable bit */ |
|
regval &= I40E_PRTTSYN_CTL1_TSYNENA_MASK; |
|
/* now enable bits for desired Rx timestamps */ |
|
regval |= tsyntype; |
|
wr32(hw, I40E_PRTTSYN_CTL1, regval); |
|
|
|
return 0; |
|
} |
|
|
|
/** |
|
* i40e_ptp_set_ts_config - ioctl interface to control the HW timestamping |
|
* @pf: Board private structure |
|
* @ifr: ioctl data |
|
* |
|
* Respond to the user filter requests and make the appropriate hardware |
|
* changes here. The XL710 cannot support splitting of the Tx/Rx timestamping |
|
* logic, so keep track in software of whether to indicate these timestamps |
|
* or not. |
|
* |
|
* It is permissible to "upgrade" the user request to a broader filter, as long |
|
* as the user receives the timestamps they care about and the user is notified |
|
* the filter has been broadened. |
|
**/ |
|
int i40e_ptp_set_ts_config(struct i40e_pf *pf, struct ifreq *ifr) |
|
{ |
|
struct hwtstamp_config config; |
|
int err; |
|
|
|
if (!(pf->flags & I40E_FLAG_PTP)) |
|
return -EOPNOTSUPP; |
|
|
|
if (copy_from_user(&config, ifr->ifr_data, sizeof(config))) |
|
return -EFAULT; |
|
|
|
err = i40e_ptp_set_timestamp_mode(pf, &config); |
|
if (err) |
|
return err; |
|
|
|
/* save these settings for future reference */ |
|
pf->tstamp_config = config; |
|
|
|
return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ? |
|
-EFAULT : 0; |
|
} |
|
|
|
/** |
|
* i40e_ptp_create_clock - Create PTP clock device for userspace |
|
* @pf: Board private structure |
|
* |
|
* This function creates a new PTP clock device. It only creates one if we |
|
* don't already have one, so it is safe to call. Will return error if it |
|
* can't create one, but success if we already have a device. Should be used |
|
* by i40e_ptp_init to create clock initially, and prevent global resets from |
|
* creating new clock devices. |
|
**/ |
|
static long i40e_ptp_create_clock(struct i40e_pf *pf) |
|
{ |
|
/* no need to create a clock device if we already have one */ |
|
if (!IS_ERR_OR_NULL(pf->ptp_clock)) |
|
return 0; |
|
|
|
strlcpy(pf->ptp_caps.name, i40e_driver_name, |
|
sizeof(pf->ptp_caps.name) - 1); |
|
pf->ptp_caps.owner = THIS_MODULE; |
|
pf->ptp_caps.max_adj = 999999999; |
|
pf->ptp_caps.n_ext_ts = 0; |
|
pf->ptp_caps.pps = 0; |
|
pf->ptp_caps.adjfreq = i40e_ptp_adjfreq; |
|
pf->ptp_caps.adjtime = i40e_ptp_adjtime; |
|
pf->ptp_caps.gettimex64 = i40e_ptp_gettimex; |
|
pf->ptp_caps.settime64 = i40e_ptp_settime; |
|
pf->ptp_caps.enable = i40e_ptp_feature_enable; |
|
|
|
/* Attempt to register the clock before enabling the hardware. */ |
|
pf->ptp_clock = ptp_clock_register(&pf->ptp_caps, &pf->pdev->dev); |
|
if (IS_ERR(pf->ptp_clock)) |
|
return PTR_ERR(pf->ptp_clock); |
|
|
|
/* clear the hwtstamp settings here during clock create, instead of |
|
* during regular init, so that we can maintain settings across a |
|
* reset or suspend. |
|
*/ |
|
pf->tstamp_config.rx_filter = HWTSTAMP_FILTER_NONE; |
|
pf->tstamp_config.tx_type = HWTSTAMP_TX_OFF; |
|
|
|
/* Set the previous "reset" time to the current Kernel clock time */ |
|
ktime_get_real_ts64(&pf->ptp_prev_hw_time); |
|
pf->ptp_reset_start = ktime_get(); |
|
|
|
return 0; |
|
} |
|
|
|
/** |
|
* i40e_ptp_save_hw_time - Save the current PTP time as ptp_prev_hw_time |
|
* @pf: Board private structure |
|
* |
|
* Read the current PTP time and save it into pf->ptp_prev_hw_time. This should |
|
* be called at the end of preparing to reset, just before hardware reset |
|
* occurs, in order to preserve the PTP time as close as possible across |
|
* resets. |
|
*/ |
|
void i40e_ptp_save_hw_time(struct i40e_pf *pf) |
|
{ |
|
/* don't try to access the PTP clock if it's not enabled */ |
|
if (!(pf->flags & I40E_FLAG_PTP)) |
|
return; |
|
|
|
i40e_ptp_gettimex(&pf->ptp_caps, &pf->ptp_prev_hw_time, NULL); |
|
/* Get a monotonic starting time for this reset */ |
|
pf->ptp_reset_start = ktime_get(); |
|
} |
|
|
|
/** |
|
* i40e_ptp_restore_hw_time - Restore the ptp_prev_hw_time + delta to PTP regs |
|
* @pf: Board private structure |
|
* |
|
* Restore the PTP hardware clock registers. We previously cached the PTP |
|
* hardware time as pf->ptp_prev_hw_time. To be as accurate as possible, |
|
* update this value based on the time delta since the time was saved, using |
|
* CLOCK_MONOTONIC (via ktime_get()) to calculate the time difference. |
|
* |
|
* This ensures that the hardware clock is restored to nearly what it should |
|
* have been if a reset had not occurred. |
|
*/ |
|
void i40e_ptp_restore_hw_time(struct i40e_pf *pf) |
|
{ |
|
ktime_t delta = ktime_sub(ktime_get(), pf->ptp_reset_start); |
|
|
|
/* Update the previous HW time with the ktime delta */ |
|
timespec64_add_ns(&pf->ptp_prev_hw_time, ktime_to_ns(delta)); |
|
|
|
/* Restore the hardware clock registers */ |
|
i40e_ptp_settime(&pf->ptp_caps, &pf->ptp_prev_hw_time); |
|
} |
|
|
|
/** |
|
* i40e_ptp_init - Initialize the 1588 support after device probe or reset |
|
* @pf: Board private structure |
|
* |
|
* This function sets device up for 1588 support. The first time it is run, it |
|
* will create a PHC clock device. It does not create a clock device if one |
|
* already exists. It also reconfigures the device after a reset. |
|
* |
|
* The first time a clock is created, i40e_ptp_create_clock will set |
|
* pf->ptp_prev_hw_time to the current system time. During resets, it is |
|
* expected that this timespec will be set to the last known PTP clock time, |
|
* in order to preserve the clock time as close as possible across a reset. |
|
**/ |
|
void i40e_ptp_init(struct i40e_pf *pf) |
|
{ |
|
struct net_device *netdev = pf->vsi[pf->lan_vsi]->netdev; |
|
struct i40e_hw *hw = &pf->hw; |
|
u32 pf_id; |
|
long err; |
|
|
|
/* Only one PF is assigned to control 1588 logic per port. Do not |
|
* enable any support for PFs not assigned via PRTTSYN_CTL0.PF_ID |
|
*/ |
|
pf_id = (rd32(hw, I40E_PRTTSYN_CTL0) & I40E_PRTTSYN_CTL0_PF_ID_MASK) >> |
|
I40E_PRTTSYN_CTL0_PF_ID_SHIFT; |
|
if (hw->pf_id != pf_id) { |
|
pf->flags &= ~I40E_FLAG_PTP; |
|
dev_info(&pf->pdev->dev, "%s: PTP not supported on %s\n", |
|
__func__, |
|
netdev->name); |
|
return; |
|
} |
|
|
|
mutex_init(&pf->tmreg_lock); |
|
spin_lock_init(&pf->ptp_rx_lock); |
|
|
|
/* ensure we have a clock device */ |
|
err = i40e_ptp_create_clock(pf); |
|
if (err) { |
|
pf->ptp_clock = NULL; |
|
dev_err(&pf->pdev->dev, "%s: ptp_clock_register failed\n", |
|
__func__); |
|
} else if (pf->ptp_clock) { |
|
u32 regval; |
|
|
|
if (pf->hw.debug_mask & I40E_DEBUG_LAN) |
|
dev_info(&pf->pdev->dev, "PHC enabled\n"); |
|
pf->flags |= I40E_FLAG_PTP; |
|
|
|
/* Ensure the clocks are running. */ |
|
regval = rd32(hw, I40E_PRTTSYN_CTL0); |
|
regval |= I40E_PRTTSYN_CTL0_TSYNENA_MASK; |
|
wr32(hw, I40E_PRTTSYN_CTL0, regval); |
|
regval = rd32(hw, I40E_PRTTSYN_CTL1); |
|
regval |= I40E_PRTTSYN_CTL1_TSYNENA_MASK; |
|
wr32(hw, I40E_PRTTSYN_CTL1, regval); |
|
|
|
/* Set the increment value per clock tick. */ |
|
i40e_ptp_set_increment(pf); |
|
|
|
/* reset timestamping mode */ |
|
i40e_ptp_set_timestamp_mode(pf, &pf->tstamp_config); |
|
|
|
/* Restore the clock time based on last known value */ |
|
i40e_ptp_restore_hw_time(pf); |
|
} |
|
} |
|
|
|
/** |
|
* i40e_ptp_stop - Disable the driver/hardware support and unregister the PHC |
|
* @pf: Board private structure |
|
* |
|
* This function handles the cleanup work required from the initialization by |
|
* clearing out the important information and unregistering the PHC. |
|
**/ |
|
void i40e_ptp_stop(struct i40e_pf *pf) |
|
{ |
|
pf->flags &= ~I40E_FLAG_PTP; |
|
pf->ptp_tx = false; |
|
pf->ptp_rx = false; |
|
|
|
if (pf->ptp_tx_skb) { |
|
struct sk_buff *skb = pf->ptp_tx_skb; |
|
|
|
pf->ptp_tx_skb = NULL; |
|
clear_bit_unlock(__I40E_PTP_TX_IN_PROGRESS, pf->state); |
|
dev_kfree_skb_any(skb); |
|
} |
|
|
|
if (pf->ptp_clock) { |
|
ptp_clock_unregister(pf->ptp_clock); |
|
pf->ptp_clock = NULL; |
|
dev_info(&pf->pdev->dev, "%s: removed PHC on %s\n", __func__, |
|
pf->vsi[pf->lan_vsi]->netdev->name); |
|
} |
|
}
|
|
|