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259 lines
8.5 KiB
259 lines
8.5 KiB
/***************************************************************************** |
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* * |
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* File: mv88x201x.c * |
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* $Revision: 1.12 $ * |
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* $Date: 2005/04/15 19:27:14 $ * |
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* Description: * |
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* Marvell PHY (mv88x201x) functionality. * |
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* part of the Chelsio 10Gb Ethernet Driver. * |
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* * |
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* This program is free software; you can redistribute it and/or modify * |
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* it under the terms of the GNU General Public License, version 2, as * |
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* published by the Free Software Foundation. * |
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* * |
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* You should have received a copy of the GNU General Public License along * |
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* with this program; if not, see <http://www.gnu.org/licenses/>. * |
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* * |
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* THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED * |
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* WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF * |
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. * |
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* * |
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* http://www.chelsio.com * |
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* * |
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* Copyright (c) 2003 - 2005 Chelsio Communications, Inc. * |
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* All rights reserved. * |
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* * |
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* Maintainers: [email protected] * |
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* * |
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* Authors: Dimitrios Michailidis <[email protected]> * |
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* Tina Yang <[email protected]> * |
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* Felix Marti <[email protected]> * |
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* Scott Bardone <[email protected]> * |
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* Kurt Ottaway <[email protected]> * |
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* Frank DiMambro <[email protected]> * |
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* * |
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* History: * |
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* * |
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****************************************************************************/ |
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#include "cphy.h" |
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#include "elmer0.h" |
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/* |
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* The 88x2010 Rev C. requires some link status registers * to be read |
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* twice in order to get the right values. Future * revisions will fix |
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* this problem and then this macro * can disappear. |
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*/ |
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#define MV88x2010_LINK_STATUS_BUGS 1 |
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static int led_init(struct cphy *cphy) |
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{ |
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/* Setup the LED registers so we can turn on/off. |
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* Writing these bits maps control to another |
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* register. mmd(0x1) addr(0x7) |
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*/ |
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cphy_mdio_write(cphy, MDIO_MMD_PCS, 0x8304, 0xdddd); |
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return 0; |
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} |
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static int led_link(struct cphy *cphy, u32 do_enable) |
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{ |
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u32 led = 0; |
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#define LINK_ENABLE_BIT 0x1 |
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cphy_mdio_read(cphy, MDIO_MMD_PMAPMD, MDIO_CTRL2, &led); |
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if (do_enable & LINK_ENABLE_BIT) { |
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led |= LINK_ENABLE_BIT; |
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cphy_mdio_write(cphy, MDIO_MMD_PMAPMD, MDIO_CTRL2, led); |
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} else { |
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led &= ~LINK_ENABLE_BIT; |
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cphy_mdio_write(cphy, MDIO_MMD_PMAPMD, MDIO_CTRL2, led); |
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} |
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return 0; |
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} |
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/* Port Reset */ |
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static int mv88x201x_reset(struct cphy *cphy, int wait) |
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{ |
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/* This can be done through registers. It is not required since |
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* a full chip reset is used. |
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*/ |
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return 0; |
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} |
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static int mv88x201x_interrupt_enable(struct cphy *cphy) |
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{ |
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/* Enable PHY LASI interrupts. */ |
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cphy_mdio_write(cphy, MDIO_MMD_PMAPMD, MDIO_PMA_LASI_CTRL, |
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MDIO_PMA_LASI_LSALARM); |
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/* Enable Marvell interrupts through Elmer0. */ |
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if (t1_is_asic(cphy->adapter)) { |
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u32 elmer; |
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t1_tpi_read(cphy->adapter, A_ELMER0_INT_ENABLE, &elmer); |
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elmer |= ELMER0_GP_BIT6; |
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t1_tpi_write(cphy->adapter, A_ELMER0_INT_ENABLE, elmer); |
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} |
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return 0; |
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} |
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static int mv88x201x_interrupt_disable(struct cphy *cphy) |
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{ |
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/* Disable PHY LASI interrupts. */ |
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cphy_mdio_write(cphy, MDIO_MMD_PMAPMD, MDIO_PMA_LASI_CTRL, 0x0); |
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/* Disable Marvell interrupts through Elmer0. */ |
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if (t1_is_asic(cphy->adapter)) { |
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u32 elmer; |
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t1_tpi_read(cphy->adapter, A_ELMER0_INT_ENABLE, &elmer); |
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elmer &= ~ELMER0_GP_BIT6; |
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t1_tpi_write(cphy->adapter, A_ELMER0_INT_ENABLE, elmer); |
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} |
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return 0; |
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} |
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static int mv88x201x_interrupt_clear(struct cphy *cphy) |
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{ |
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u32 elmer; |
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u32 val; |
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#ifdef MV88x2010_LINK_STATUS_BUGS |
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/* Required to read twice before clear takes affect. */ |
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cphy_mdio_read(cphy, MDIO_MMD_PMAPMD, MDIO_PMA_LASI_RXSTAT, &val); |
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cphy_mdio_read(cphy, MDIO_MMD_PMAPMD, MDIO_PMA_LASI_TXSTAT, &val); |
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cphy_mdio_read(cphy, MDIO_MMD_PMAPMD, MDIO_PMA_LASI_STAT, &val); |
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/* Read this register after the others above it else |
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* the register doesn't clear correctly. |
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*/ |
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cphy_mdio_read(cphy, MDIO_MMD_PMAPMD, MDIO_STAT1, &val); |
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#endif |
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/* Clear link status. */ |
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cphy_mdio_read(cphy, MDIO_MMD_PMAPMD, MDIO_STAT1, &val); |
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/* Clear PHY LASI interrupts. */ |
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cphy_mdio_read(cphy, MDIO_MMD_PMAPMD, MDIO_PMA_LASI_STAT, &val); |
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#ifdef MV88x2010_LINK_STATUS_BUGS |
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/* Do it again. */ |
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cphy_mdio_read(cphy, MDIO_MMD_PMAPMD, MDIO_PMA_LASI_RXSTAT, &val); |
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cphy_mdio_read(cphy, MDIO_MMD_PMAPMD, MDIO_PMA_LASI_TXSTAT, &val); |
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#endif |
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/* Clear Marvell interrupts through Elmer0. */ |
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if (t1_is_asic(cphy->adapter)) { |
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t1_tpi_read(cphy->adapter, A_ELMER0_INT_CAUSE, &elmer); |
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elmer |= ELMER0_GP_BIT6; |
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t1_tpi_write(cphy->adapter, A_ELMER0_INT_CAUSE, elmer); |
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} |
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return 0; |
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} |
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static int mv88x201x_interrupt_handler(struct cphy *cphy) |
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{ |
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/* Clear interrupts */ |
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mv88x201x_interrupt_clear(cphy); |
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/* We have only enabled link change interrupts and so |
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* cphy_cause must be a link change interrupt. |
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*/ |
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return cphy_cause_link_change; |
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} |
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static int mv88x201x_set_loopback(struct cphy *cphy, int on) |
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{ |
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return 0; |
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} |
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static int mv88x201x_get_link_status(struct cphy *cphy, int *link_ok, |
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int *speed, int *duplex, int *fc) |
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{ |
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u32 val = 0; |
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if (link_ok) { |
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/* Read link status. */ |
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cphy_mdio_read(cphy, MDIO_MMD_PMAPMD, MDIO_STAT1, &val); |
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val &= MDIO_STAT1_LSTATUS; |
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*link_ok = (val == MDIO_STAT1_LSTATUS); |
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/* Turn on/off Link LED */ |
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led_link(cphy, *link_ok); |
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} |
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if (speed) |
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*speed = SPEED_10000; |
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if (duplex) |
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*duplex = DUPLEX_FULL; |
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if (fc) |
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*fc = PAUSE_RX | PAUSE_TX; |
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return 0; |
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} |
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static void mv88x201x_destroy(struct cphy *cphy) |
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{ |
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kfree(cphy); |
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} |
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static const struct cphy_ops mv88x201x_ops = { |
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.destroy = mv88x201x_destroy, |
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.reset = mv88x201x_reset, |
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.interrupt_enable = mv88x201x_interrupt_enable, |
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.interrupt_disable = mv88x201x_interrupt_disable, |
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.interrupt_clear = mv88x201x_interrupt_clear, |
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.interrupt_handler = mv88x201x_interrupt_handler, |
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.get_link_status = mv88x201x_get_link_status, |
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.set_loopback = mv88x201x_set_loopback, |
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.mmds = (MDIO_DEVS_PMAPMD | MDIO_DEVS_PCS | |
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MDIO_DEVS_PHYXS | MDIO_DEVS_WIS), |
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}; |
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static struct cphy *mv88x201x_phy_create(struct net_device *dev, int phy_addr, |
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const struct mdio_ops *mdio_ops) |
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{ |
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u32 val; |
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struct cphy *cphy = kzalloc(sizeof(*cphy), GFP_KERNEL); |
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if (!cphy) |
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return NULL; |
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cphy_init(cphy, dev, phy_addr, &mv88x201x_ops, mdio_ops); |
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/* Commands the PHY to enable XFP's clock. */ |
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cphy_mdio_read(cphy, MDIO_MMD_PCS, 0x8300, &val); |
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cphy_mdio_write(cphy, MDIO_MMD_PCS, 0x8300, val | 1); |
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/* Clear link status. Required because of a bug in the PHY. */ |
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cphy_mdio_read(cphy, MDIO_MMD_PMAPMD, MDIO_STAT2, &val); |
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cphy_mdio_read(cphy, MDIO_MMD_PCS, MDIO_STAT2, &val); |
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/* Allows for Link,Ack LED turn on/off */ |
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led_init(cphy); |
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return cphy; |
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} |
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/* Chip Reset */ |
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static int mv88x201x_phy_reset(adapter_t *adapter) |
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{ |
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u32 val; |
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t1_tpi_read(adapter, A_ELMER0_GPO, &val); |
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val &= ~4; |
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t1_tpi_write(adapter, A_ELMER0_GPO, val); |
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msleep(100); |
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t1_tpi_write(adapter, A_ELMER0_GPO, val | 4); |
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msleep(1000); |
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/* Now lets enable the Laser. Delay 100us */ |
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t1_tpi_read(adapter, A_ELMER0_GPO, &val); |
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val |= 0x8000; |
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t1_tpi_write(adapter, A_ELMER0_GPO, val); |
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udelay(100); |
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return 0; |
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} |
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const struct gphy t1_mv88x201x_ops = { |
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.create = mv88x201x_phy_create, |
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.reset = mv88x201x_phy_reset |
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};
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