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257 lines
6.8 KiB
257 lines
6.8 KiB
/* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */ |
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/* |
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* Copyright 2015-2020 Amazon.com, Inc. or its affiliates. All rights reserved. |
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*/ |
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#ifndef ENA_ETH_COM_H_ |
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#define ENA_ETH_COM_H_ |
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#include "ena_com.h" |
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/* head update threshold in units of (queue size / ENA_COMP_HEAD_THRESH) */ |
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#define ENA_COMP_HEAD_THRESH 4 |
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struct ena_com_tx_ctx { |
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struct ena_com_tx_meta ena_meta; |
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struct ena_com_buf *ena_bufs; |
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/* For LLQ, header buffer - pushed to the device mem space */ |
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void *push_header; |
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enum ena_eth_io_l3_proto_index l3_proto; |
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enum ena_eth_io_l4_proto_index l4_proto; |
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u16 num_bufs; |
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u16 req_id; |
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/* For regular queue, indicate the size of the header |
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* For LLQ, indicate the size of the pushed buffer |
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*/ |
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u16 header_len; |
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u8 meta_valid; |
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u8 tso_enable; |
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u8 l3_csum_enable; |
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u8 l4_csum_enable; |
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u8 l4_csum_partial; |
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u8 df; /* Don't fragment */ |
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}; |
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struct ena_com_rx_ctx { |
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struct ena_com_rx_buf_info *ena_bufs; |
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enum ena_eth_io_l3_proto_index l3_proto; |
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enum ena_eth_io_l4_proto_index l4_proto; |
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bool l3_csum_err; |
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bool l4_csum_err; |
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u8 l4_csum_checked; |
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/* fragmented packet */ |
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bool frag; |
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u32 hash; |
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u16 descs; |
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int max_bufs; |
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u8 pkt_offset; |
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}; |
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int ena_com_prepare_tx(struct ena_com_io_sq *io_sq, |
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struct ena_com_tx_ctx *ena_tx_ctx, |
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int *nb_hw_desc); |
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int ena_com_rx_pkt(struct ena_com_io_cq *io_cq, |
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struct ena_com_io_sq *io_sq, |
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struct ena_com_rx_ctx *ena_rx_ctx); |
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int ena_com_add_single_rx_desc(struct ena_com_io_sq *io_sq, |
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struct ena_com_buf *ena_buf, |
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u16 req_id); |
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bool ena_com_cq_empty(struct ena_com_io_cq *io_cq); |
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static inline void ena_com_unmask_intr(struct ena_com_io_cq *io_cq, |
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struct ena_eth_io_intr_reg *intr_reg) |
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{ |
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writel(intr_reg->intr_control, io_cq->unmask_reg); |
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} |
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static inline int ena_com_free_q_entries(struct ena_com_io_sq *io_sq) |
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{ |
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u16 tail, next_to_comp, cnt; |
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next_to_comp = io_sq->next_to_comp; |
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tail = io_sq->tail; |
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cnt = tail - next_to_comp; |
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return io_sq->q_depth - 1 - cnt; |
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} |
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/* Check if the submission queue has enough space to hold required_buffers */ |
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static inline bool ena_com_sq_have_enough_space(struct ena_com_io_sq *io_sq, |
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u16 required_buffers) |
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{ |
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int temp; |
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if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST) |
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return ena_com_free_q_entries(io_sq) >= required_buffers; |
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/* This calculation doesn't need to be 100% accurate. So to reduce |
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* the calculation overhead just Subtract 2 lines from the free descs |
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* (one for the header line and one to compensate the devision |
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* down calculation. |
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*/ |
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temp = required_buffers / io_sq->llq_info.descs_per_entry + 2; |
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return ena_com_free_q_entries(io_sq) > temp; |
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} |
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static inline bool ena_com_meta_desc_changed(struct ena_com_io_sq *io_sq, |
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struct ena_com_tx_ctx *ena_tx_ctx) |
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{ |
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if (!ena_tx_ctx->meta_valid) |
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return false; |
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return !!memcmp(&io_sq->cached_tx_meta, |
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&ena_tx_ctx->ena_meta, |
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sizeof(struct ena_com_tx_meta)); |
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} |
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static inline bool is_llq_max_tx_burst_exists(struct ena_com_io_sq *io_sq) |
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{ |
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return (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) && |
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io_sq->llq_info.max_entries_in_tx_burst > 0; |
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} |
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static inline bool ena_com_is_doorbell_needed(struct ena_com_io_sq *io_sq, |
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struct ena_com_tx_ctx *ena_tx_ctx) |
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{ |
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struct ena_com_llq_info *llq_info; |
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int descs_after_first_entry; |
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int num_entries_needed = 1; |
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u16 num_descs; |
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if (!is_llq_max_tx_burst_exists(io_sq)) |
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return false; |
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llq_info = &io_sq->llq_info; |
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num_descs = ena_tx_ctx->num_bufs; |
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if (llq_info->disable_meta_caching || |
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unlikely(ena_com_meta_desc_changed(io_sq, ena_tx_ctx))) |
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++num_descs; |
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if (num_descs > llq_info->descs_num_before_header) { |
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descs_after_first_entry = num_descs - llq_info->descs_num_before_header; |
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num_entries_needed += DIV_ROUND_UP(descs_after_first_entry, |
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llq_info->descs_per_entry); |
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} |
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netdev_dbg(ena_com_io_sq_to_ena_dev(io_sq)->net_device, |
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"Queue: %d num_descs: %d num_entries_needed: %d\n", |
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io_sq->qid, num_descs, num_entries_needed); |
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return num_entries_needed > io_sq->entries_in_tx_burst_left; |
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} |
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static inline int ena_com_write_sq_doorbell(struct ena_com_io_sq *io_sq) |
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{ |
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u16 max_entries_in_tx_burst = io_sq->llq_info.max_entries_in_tx_burst; |
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u16 tail = io_sq->tail; |
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netdev_dbg(ena_com_io_sq_to_ena_dev(io_sq)->net_device, |
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"Write submission queue doorbell for queue: %d tail: %d\n", |
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io_sq->qid, tail); |
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writel(tail, io_sq->db_addr); |
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if (is_llq_max_tx_burst_exists(io_sq)) { |
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netdev_dbg(ena_com_io_sq_to_ena_dev(io_sq)->net_device, |
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"Reset available entries in tx burst for queue %d to %d\n", |
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io_sq->qid, max_entries_in_tx_burst); |
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io_sq->entries_in_tx_burst_left = max_entries_in_tx_burst; |
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} |
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return 0; |
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} |
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static inline int ena_com_update_dev_comp_head(struct ena_com_io_cq *io_cq) |
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{ |
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u16 unreported_comp, head; |
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bool need_update; |
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if (unlikely(io_cq->cq_head_db_reg)) { |
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head = io_cq->head; |
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unreported_comp = head - io_cq->last_head_update; |
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need_update = unreported_comp > (io_cq->q_depth / ENA_COMP_HEAD_THRESH); |
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if (unlikely(need_update)) { |
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netdev_dbg(ena_com_io_cq_to_ena_dev(io_cq)->net_device, |
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"Write completion queue doorbell for queue %d: head: %d\n", |
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io_cq->qid, head); |
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writel(head, io_cq->cq_head_db_reg); |
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io_cq->last_head_update = head; |
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} |
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} |
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return 0; |
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} |
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static inline void ena_com_update_numa_node(struct ena_com_io_cq *io_cq, |
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u8 numa_node) |
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{ |
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struct ena_eth_io_numa_node_cfg_reg numa_cfg; |
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if (!io_cq->numa_node_cfg_reg) |
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return; |
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numa_cfg.numa_cfg = (numa_node & ENA_ETH_IO_NUMA_NODE_CFG_REG_NUMA_MASK) |
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| ENA_ETH_IO_NUMA_NODE_CFG_REG_ENABLED_MASK; |
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writel(numa_cfg.numa_cfg, io_cq->numa_node_cfg_reg); |
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} |
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static inline void ena_com_comp_ack(struct ena_com_io_sq *io_sq, u16 elem) |
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{ |
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io_sq->next_to_comp += elem; |
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} |
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static inline void ena_com_cq_inc_head(struct ena_com_io_cq *io_cq) |
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{ |
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io_cq->head++; |
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/* Switch phase bit in case of wrap around */ |
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if (unlikely((io_cq->head & (io_cq->q_depth - 1)) == 0)) |
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io_cq->phase ^= 1; |
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} |
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static inline int ena_com_tx_comp_req_id_get(struct ena_com_io_cq *io_cq, |
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u16 *req_id) |
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{ |
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u8 expected_phase, cdesc_phase; |
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struct ena_eth_io_tx_cdesc *cdesc; |
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u16 masked_head; |
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masked_head = io_cq->head & (io_cq->q_depth - 1); |
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expected_phase = io_cq->phase; |
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cdesc = (struct ena_eth_io_tx_cdesc *) |
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((uintptr_t)io_cq->cdesc_addr.virt_addr + |
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(masked_head * io_cq->cdesc_entry_size_in_bytes)); |
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/* When the current completion descriptor phase isn't the same as the |
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* expected, it mean that the device still didn't update |
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* this completion. |
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*/ |
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cdesc_phase = READ_ONCE(cdesc->flags) & ENA_ETH_IO_TX_CDESC_PHASE_MASK; |
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if (cdesc_phase != expected_phase) |
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return -EAGAIN; |
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dma_rmb(); |
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*req_id = READ_ONCE(cdesc->req_id); |
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if (unlikely(*req_id >= io_cq->q_depth)) { |
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netdev_err(ena_com_io_cq_to_ena_dev(io_cq)->net_device, |
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"Invalid req id %d\n", cdesc->req_id); |
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return -EINVAL; |
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} |
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ena_com_cq_inc_head(io_cq); |
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return 0; |
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} |
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#endif /* ENA_ETH_COM_H_ */
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