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1186 lines
31 KiB
1186 lines
31 KiB
/* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */ |
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/* |
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* Copyright 2015-2020 Amazon.com, Inc. or its affiliates. All rights reserved. |
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*/ |
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#ifndef _ENA_ADMIN_H_ |
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#define _ENA_ADMIN_H_ |
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|
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#define ENA_ADMIN_RSS_KEY_PARTS 10 |
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enum ena_admin_aq_opcode { |
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ENA_ADMIN_CREATE_SQ = 1, |
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ENA_ADMIN_DESTROY_SQ = 2, |
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ENA_ADMIN_CREATE_CQ = 3, |
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ENA_ADMIN_DESTROY_CQ = 4, |
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ENA_ADMIN_GET_FEATURE = 8, |
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ENA_ADMIN_SET_FEATURE = 9, |
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ENA_ADMIN_GET_STATS = 11, |
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}; |
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enum ena_admin_aq_completion_status { |
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ENA_ADMIN_SUCCESS = 0, |
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ENA_ADMIN_RESOURCE_ALLOCATION_FAILURE = 1, |
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ENA_ADMIN_BAD_OPCODE = 2, |
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ENA_ADMIN_UNSUPPORTED_OPCODE = 3, |
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ENA_ADMIN_MALFORMED_REQUEST = 4, |
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/* Additional status is provided in ACQ entry extended_status */ |
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ENA_ADMIN_ILLEGAL_PARAMETER = 5, |
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ENA_ADMIN_UNKNOWN_ERROR = 6, |
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ENA_ADMIN_RESOURCE_BUSY = 7, |
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}; |
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/* subcommands for the set/get feature admin commands */ |
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enum ena_admin_aq_feature_id { |
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ENA_ADMIN_DEVICE_ATTRIBUTES = 1, |
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ENA_ADMIN_MAX_QUEUES_NUM = 2, |
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ENA_ADMIN_HW_HINTS = 3, |
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ENA_ADMIN_LLQ = 4, |
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ENA_ADMIN_MAX_QUEUES_EXT = 7, |
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ENA_ADMIN_RSS_HASH_FUNCTION = 10, |
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ENA_ADMIN_STATELESS_OFFLOAD_CONFIG = 11, |
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ENA_ADMIN_RSS_INDIRECTION_TABLE_CONFIG = 12, |
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ENA_ADMIN_MTU = 14, |
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ENA_ADMIN_RSS_HASH_INPUT = 18, |
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ENA_ADMIN_INTERRUPT_MODERATION = 20, |
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ENA_ADMIN_AENQ_CONFIG = 26, |
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ENA_ADMIN_LINK_CONFIG = 27, |
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ENA_ADMIN_HOST_ATTR_CONFIG = 28, |
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ENA_ADMIN_FEATURES_OPCODE_NUM = 32, |
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}; |
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enum ena_admin_placement_policy_type { |
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/* descriptors and headers are in host memory */ |
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ENA_ADMIN_PLACEMENT_POLICY_HOST = 1, |
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/* descriptors and headers are in device memory (a.k.a Low Latency |
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* Queue) |
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*/ |
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ENA_ADMIN_PLACEMENT_POLICY_DEV = 3, |
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}; |
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enum ena_admin_link_types { |
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ENA_ADMIN_LINK_SPEED_1G = 0x1, |
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ENA_ADMIN_LINK_SPEED_2_HALF_G = 0x2, |
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ENA_ADMIN_LINK_SPEED_5G = 0x4, |
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ENA_ADMIN_LINK_SPEED_10G = 0x8, |
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ENA_ADMIN_LINK_SPEED_25G = 0x10, |
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ENA_ADMIN_LINK_SPEED_40G = 0x20, |
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ENA_ADMIN_LINK_SPEED_50G = 0x40, |
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ENA_ADMIN_LINK_SPEED_100G = 0x80, |
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ENA_ADMIN_LINK_SPEED_200G = 0x100, |
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ENA_ADMIN_LINK_SPEED_400G = 0x200, |
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}; |
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enum ena_admin_completion_policy_type { |
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/* completion queue entry for each sq descriptor */ |
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ENA_ADMIN_COMPLETION_POLICY_DESC = 0, |
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/* completion queue entry upon request in sq descriptor */ |
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ENA_ADMIN_COMPLETION_POLICY_DESC_ON_DEMAND = 1, |
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/* current queue head pointer is updated in OS memory upon sq |
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* descriptor request |
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*/ |
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ENA_ADMIN_COMPLETION_POLICY_HEAD_ON_DEMAND = 2, |
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/* current queue head pointer is updated in OS memory for each sq |
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* descriptor |
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*/ |
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ENA_ADMIN_COMPLETION_POLICY_HEAD = 3, |
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}; |
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/* basic stats return ena_admin_basic_stats while extanded stats return a |
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* buffer (string format) with additional statistics per queue and per |
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* device id |
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*/ |
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enum ena_admin_get_stats_type { |
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ENA_ADMIN_GET_STATS_TYPE_BASIC = 0, |
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ENA_ADMIN_GET_STATS_TYPE_EXTENDED = 1, |
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/* extra HW stats for specific network interface */ |
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ENA_ADMIN_GET_STATS_TYPE_ENI = 2, |
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}; |
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enum ena_admin_get_stats_scope { |
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ENA_ADMIN_SPECIFIC_QUEUE = 0, |
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ENA_ADMIN_ETH_TRAFFIC = 1, |
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}; |
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struct ena_admin_aq_common_desc { |
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/* 11:0 : command_id |
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* 15:12 : reserved12 |
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*/ |
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u16 command_id; |
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/* as appears in ena_admin_aq_opcode */ |
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u8 opcode; |
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/* 0 : phase |
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* 1 : ctrl_data - control buffer address valid |
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* 2 : ctrl_data_indirect - control buffer address |
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* points to list of pages with addresses of control |
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* buffers |
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* 7:3 : reserved3 |
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*/ |
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u8 flags; |
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}; |
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/* used in ena_admin_aq_entry. Can point directly to control data, or to a |
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* page list chunk. Used also at the end of indirect mode page list chunks, |
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* for chaining. |
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*/ |
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struct ena_admin_ctrl_buff_info { |
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u32 length; |
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struct ena_common_mem_addr address; |
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}; |
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struct ena_admin_sq { |
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u16 sq_idx; |
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/* 4:0 : reserved |
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* 7:5 : sq_direction - 0x1 - Tx; 0x2 - Rx |
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*/ |
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u8 sq_identity; |
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u8 reserved1; |
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}; |
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struct ena_admin_aq_entry { |
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struct ena_admin_aq_common_desc aq_common_descriptor; |
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union { |
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u32 inline_data_w1[3]; |
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struct ena_admin_ctrl_buff_info control_buffer; |
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} u; |
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u32 inline_data_w4[12]; |
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}; |
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struct ena_admin_acq_common_desc { |
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/* command identifier to associate it with the aq descriptor |
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* 11:0 : command_id |
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* 15:12 : reserved12 |
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*/ |
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u16 command; |
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u8 status; |
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/* 0 : phase |
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* 7:1 : reserved1 |
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*/ |
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u8 flags; |
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u16 extended_status; |
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/* indicates to the driver which AQ entry has been consumed by the |
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* device and could be reused |
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*/ |
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u16 sq_head_indx; |
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}; |
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struct ena_admin_acq_entry { |
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struct ena_admin_acq_common_desc acq_common_descriptor; |
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u32 response_specific_data[14]; |
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}; |
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struct ena_admin_aq_create_sq_cmd { |
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struct ena_admin_aq_common_desc aq_common_descriptor; |
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/* 4:0 : reserved0_w1 |
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* 7:5 : sq_direction - 0x1 - Tx, 0x2 - Rx |
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*/ |
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u8 sq_identity; |
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u8 reserved8_w1; |
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/* 3:0 : placement_policy - Describing where the SQ |
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* descriptor ring and the SQ packet headers reside: |
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* 0x1 - descriptors and headers are in OS memory, |
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* 0x3 - descriptors and headers in device memory |
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* (a.k.a Low Latency Queue) |
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* 6:4 : completion_policy - Describing what policy |
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* to use for generation completion entry (cqe) in |
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* the CQ associated with this SQ: 0x0 - cqe for each |
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* sq descriptor, 0x1 - cqe upon request in sq |
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* descriptor, 0x2 - current queue head pointer is |
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* updated in OS memory upon sq descriptor request |
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* 0x3 - current queue head pointer is updated in OS |
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* memory for each sq descriptor |
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* 7 : reserved15_w1 |
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*/ |
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u8 sq_caps_2; |
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/* 0 : is_physically_contiguous - Described if the |
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* queue ring memory is allocated in physical |
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* contiguous pages or split. |
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* 7:1 : reserved17_w1 |
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*/ |
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u8 sq_caps_3; |
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/* associated completion queue id. This CQ must be created prior to SQ |
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* creation |
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*/ |
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u16 cq_idx; |
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/* submission queue depth in entries */ |
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u16 sq_depth; |
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/* SQ physical base address in OS memory. This field should not be |
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* used for Low Latency queues. Has to be page aligned. |
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*/ |
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struct ena_common_mem_addr sq_ba; |
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/* specifies queue head writeback location in OS memory. Valid if |
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* completion_policy is set to completion_policy_head_on_demand or |
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* completion_policy_head. Has to be cache aligned |
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*/ |
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struct ena_common_mem_addr sq_head_writeback; |
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u32 reserved0_w7; |
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u32 reserved0_w8; |
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}; |
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enum ena_admin_sq_direction { |
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ENA_ADMIN_SQ_DIRECTION_TX = 1, |
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ENA_ADMIN_SQ_DIRECTION_RX = 2, |
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}; |
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struct ena_admin_acq_create_sq_resp_desc { |
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struct ena_admin_acq_common_desc acq_common_desc; |
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u16 sq_idx; |
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u16 reserved; |
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/* queue doorbell address as an offset to PCIe MMIO REG BAR */ |
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u32 sq_doorbell_offset; |
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/* low latency queue ring base address as an offset to PCIe MMIO |
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* LLQ_MEM BAR |
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*/ |
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u32 llq_descriptors_offset; |
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/* low latency queue headers' memory as an offset to PCIe MMIO |
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* LLQ_MEM BAR |
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*/ |
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u32 llq_headers_offset; |
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}; |
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struct ena_admin_aq_destroy_sq_cmd { |
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struct ena_admin_aq_common_desc aq_common_descriptor; |
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struct ena_admin_sq sq; |
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}; |
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struct ena_admin_acq_destroy_sq_resp_desc { |
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struct ena_admin_acq_common_desc acq_common_desc; |
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}; |
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struct ena_admin_aq_create_cq_cmd { |
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struct ena_admin_aq_common_desc aq_common_descriptor; |
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/* 4:0 : reserved5 |
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* 5 : interrupt_mode_enabled - if set, cq operates |
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* in interrupt mode, otherwise - polling |
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* 7:6 : reserved6 |
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*/ |
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u8 cq_caps_1; |
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/* 4:0 : cq_entry_size_words - size of CQ entry in |
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* 32-bit words, valid values: 4, 8. |
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* 7:5 : reserved7 |
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*/ |
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u8 cq_caps_2; |
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/* completion queue depth in # of entries. must be power of 2 */ |
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u16 cq_depth; |
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/* msix vector assigned to this cq */ |
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u32 msix_vector; |
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/* cq physical base address in OS memory. CQ must be physically |
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* contiguous |
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*/ |
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struct ena_common_mem_addr cq_ba; |
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}; |
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struct ena_admin_acq_create_cq_resp_desc { |
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struct ena_admin_acq_common_desc acq_common_desc; |
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u16 cq_idx; |
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/* actual cq depth in number of entries */ |
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u16 cq_actual_depth; |
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u32 numa_node_register_offset; |
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u32 cq_head_db_register_offset; |
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u32 cq_interrupt_unmask_register_offset; |
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}; |
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struct ena_admin_aq_destroy_cq_cmd { |
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struct ena_admin_aq_common_desc aq_common_descriptor; |
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u16 cq_idx; |
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u16 reserved1; |
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}; |
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struct ena_admin_acq_destroy_cq_resp_desc { |
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struct ena_admin_acq_common_desc acq_common_desc; |
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}; |
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/* ENA AQ Get Statistics command. Extended statistics are placed in control |
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* buffer pointed by AQ entry |
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*/ |
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struct ena_admin_aq_get_stats_cmd { |
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struct ena_admin_aq_common_desc aq_common_descriptor; |
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union { |
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/* command specific inline data */ |
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u32 inline_data_w1[3]; |
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struct ena_admin_ctrl_buff_info control_buffer; |
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} u; |
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/* stats type as defined in enum ena_admin_get_stats_type */ |
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u8 type; |
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/* stats scope defined in enum ena_admin_get_stats_scope */ |
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u8 scope; |
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u16 reserved3; |
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/* queue id. used when scope is specific_queue */ |
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u16 queue_idx; |
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/* device id, value 0xFFFF means mine. only privileged device can get |
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* stats of other device |
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*/ |
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u16 device_id; |
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}; |
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/* Basic Statistics Command. */ |
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struct ena_admin_basic_stats { |
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u32 tx_bytes_low; |
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u32 tx_bytes_high; |
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u32 tx_pkts_low; |
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u32 tx_pkts_high; |
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u32 rx_bytes_low; |
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u32 rx_bytes_high; |
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u32 rx_pkts_low; |
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u32 rx_pkts_high; |
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u32 rx_drops_low; |
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u32 rx_drops_high; |
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u32 tx_drops_low; |
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u32 tx_drops_high; |
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}; |
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/* ENI Statistics Command. */ |
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struct ena_admin_eni_stats { |
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/* The number of packets shaped due to inbound aggregate BW |
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* allowance being exceeded |
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*/ |
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u64 bw_in_allowance_exceeded; |
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/* The number of packets shaped due to outbound aggregate BW |
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* allowance being exceeded |
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*/ |
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u64 bw_out_allowance_exceeded; |
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/* The number of packets shaped due to PPS allowance being exceeded */ |
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u64 pps_allowance_exceeded; |
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/* The number of packets shaped due to connection tracking |
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* allowance being exceeded and leading to failure in establishment |
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* of new connections |
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*/ |
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u64 conntrack_allowance_exceeded; |
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/* The number of packets shaped due to linklocal packet rate |
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* allowance being exceeded |
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*/ |
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u64 linklocal_allowance_exceeded; |
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}; |
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struct ena_admin_acq_get_stats_resp { |
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struct ena_admin_acq_common_desc acq_common_desc; |
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union { |
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u64 raw[7]; |
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struct ena_admin_basic_stats basic_stats; |
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struct ena_admin_eni_stats eni_stats; |
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} u; |
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}; |
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struct ena_admin_get_set_feature_common_desc { |
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/* 1:0 : select - 0x1 - current value; 0x3 - default |
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* value |
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* 7:3 : reserved3 |
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*/ |
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u8 flags; |
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/* as appears in ena_admin_aq_feature_id */ |
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u8 feature_id; |
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/* The driver specifies the max feature version it supports and the |
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* device responds with the currently supported feature version. The |
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* field is zero based |
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*/ |
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u8 feature_version; |
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u8 reserved8; |
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}; |
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struct ena_admin_device_attr_feature_desc { |
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u32 impl_id; |
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u32 device_version; |
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/* bitmap of ena_admin_aq_feature_id, which represents supported |
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* subcommands for the set/get feature admin commands. |
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*/ |
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u32 supported_features; |
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u32 reserved3; |
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/* Indicates how many bits are used physical address access. */ |
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u32 phys_addr_width; |
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/* Indicates how many bits are used virtual address access. */ |
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u32 virt_addr_width; |
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/* unicast MAC address (in Network byte order) */ |
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u8 mac_addr[6]; |
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u8 reserved7[2]; |
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u32 max_mtu; |
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}; |
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enum ena_admin_llq_header_location { |
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/* header is in descriptor list */ |
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ENA_ADMIN_INLINE_HEADER = 1, |
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/* header in a separate ring, implies 16B descriptor list entry */ |
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ENA_ADMIN_HEADER_RING = 2, |
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}; |
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enum ena_admin_llq_ring_entry_size { |
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ENA_ADMIN_LIST_ENTRY_SIZE_128B = 1, |
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ENA_ADMIN_LIST_ENTRY_SIZE_192B = 2, |
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ENA_ADMIN_LIST_ENTRY_SIZE_256B = 4, |
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}; |
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enum ena_admin_llq_num_descs_before_header { |
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ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_0 = 0, |
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ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_1 = 1, |
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ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_2 = 2, |
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ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_4 = 4, |
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ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_8 = 8, |
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}; |
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|
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/* packet descriptor list entry always starts with one or more descriptors, |
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* followed by a header. The rest of the descriptors are located in the |
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* beginning of the subsequent entry. Stride refers to how the rest of the |
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* descriptors are placed. This field is relevant only for inline header |
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* mode |
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*/ |
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enum ena_admin_llq_stride_ctrl { |
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ENA_ADMIN_SINGLE_DESC_PER_ENTRY = 1, |
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ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY = 2, |
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}; |
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enum ena_admin_accel_mode_feat { |
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ENA_ADMIN_DISABLE_META_CACHING = 0, |
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ENA_ADMIN_LIMIT_TX_BURST = 1, |
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}; |
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struct ena_admin_accel_mode_get { |
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/* bit field of enum ena_admin_accel_mode_feat */ |
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u16 supported_flags; |
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|
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/* maximum burst size between two doorbells. The size is in bytes */ |
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u16 max_tx_burst_size; |
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}; |
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struct ena_admin_accel_mode_set { |
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/* bit field of enum ena_admin_accel_mode_feat */ |
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u16 enabled_flags; |
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u16 reserved; |
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}; |
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struct ena_admin_accel_mode_req { |
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union { |
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u32 raw[2]; |
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struct ena_admin_accel_mode_get get; |
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struct ena_admin_accel_mode_set set; |
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} u; |
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}; |
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struct ena_admin_feature_llq_desc { |
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u32 max_llq_num; |
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u32 max_llq_depth; |
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|
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/* specify the header locations the device supports. bitfield of enum |
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* ena_admin_llq_header_location. |
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*/ |
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u16 header_location_ctrl_supported; |
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|
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/* the header location the driver selected to use. */ |
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u16 header_location_ctrl_enabled; |
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|
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/* if inline header is specified - this is the size of descriptor list |
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* entry. If header in a separate ring is specified - this is the size |
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* of header ring entry. bitfield of enum ena_admin_llq_ring_entry_size. |
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* specify the entry sizes the device supports |
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*/ |
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u16 entry_size_ctrl_supported; |
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|
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/* the entry size the driver selected to use. */ |
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u16 entry_size_ctrl_enabled; |
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|
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/* valid only if inline header is specified. First entry associated with |
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* the packet includes descriptors and header. Rest of the entries |
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* occupied by descriptors. This parameter defines the max number of |
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* descriptors precedding the header in the first entry. The field is |
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* bitfield of enum ena_admin_llq_num_descs_before_header and specify |
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* the values the device supports |
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*/ |
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u16 desc_num_before_header_supported; |
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|
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/* the desire field the driver selected to use */ |
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u16 desc_num_before_header_enabled; |
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|
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/* valid only if inline was chosen. bitfield of enum |
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* ena_admin_llq_stride_ctrl |
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*/ |
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u16 descriptors_stride_ctrl_supported; |
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|
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/* the stride control the driver selected to use */ |
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u16 descriptors_stride_ctrl_enabled; |
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|
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/* reserved */ |
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u32 reserved1; |
|
|
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/* accelerated low latency queues requirement. driver needs to |
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* support those requirements in order to use accelerated llq |
|
*/ |
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struct ena_admin_accel_mode_req accel_mode; |
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}; |
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|
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struct ena_admin_queue_ext_feature_fields { |
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u32 max_tx_sq_num; |
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|
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u32 max_tx_cq_num; |
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|
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u32 max_rx_sq_num; |
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|
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u32 max_rx_cq_num; |
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|
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u32 max_tx_sq_depth; |
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|
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u32 max_tx_cq_depth; |
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|
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u32 max_rx_sq_depth; |
|
|
|
u32 max_rx_cq_depth; |
|
|
|
u32 max_tx_header_size; |
|
|
|
/* Maximum Descriptors number, including meta descriptor, allowed for a |
|
* single Tx packet |
|
*/ |
|
u16 max_per_packet_tx_descs; |
|
|
|
/* Maximum Descriptors number allowed for a single Rx packet */ |
|
u16 max_per_packet_rx_descs; |
|
}; |
|
|
|
struct ena_admin_queue_feature_desc { |
|
u32 max_sq_num; |
|
|
|
u32 max_sq_depth; |
|
|
|
u32 max_cq_num; |
|
|
|
u32 max_cq_depth; |
|
|
|
u32 max_legacy_llq_num; |
|
|
|
u32 max_legacy_llq_depth; |
|
|
|
u32 max_header_size; |
|
|
|
/* Maximum Descriptors number, including meta descriptor, allowed for a |
|
* single Tx packet |
|
*/ |
|
u16 max_packet_tx_descs; |
|
|
|
/* Maximum Descriptors number allowed for a single Rx packet */ |
|
u16 max_packet_rx_descs; |
|
}; |
|
|
|
struct ena_admin_set_feature_mtu_desc { |
|
/* exclude L2 */ |
|
u32 mtu; |
|
}; |
|
|
|
struct ena_admin_set_feature_host_attr_desc { |
|
/* host OS info base address in OS memory. host info is 4KB of |
|
* physically contiguous |
|
*/ |
|
struct ena_common_mem_addr os_info_ba; |
|
|
|
/* host debug area base address in OS memory. debug area must be |
|
* physically contiguous |
|
*/ |
|
struct ena_common_mem_addr debug_ba; |
|
|
|
/* debug area size */ |
|
u32 debug_area_size; |
|
}; |
|
|
|
struct ena_admin_feature_intr_moder_desc { |
|
/* interrupt delay granularity in usec */ |
|
u16 intr_delay_resolution; |
|
|
|
u16 reserved; |
|
}; |
|
|
|
struct ena_admin_get_feature_link_desc { |
|
/* Link speed in Mb */ |
|
u32 speed; |
|
|
|
/* bit field of enum ena_admin_link types */ |
|
u32 supported; |
|
|
|
/* 0 : autoneg |
|
* 1 : duplex - Full Duplex |
|
* 31:2 : reserved2 |
|
*/ |
|
u32 flags; |
|
}; |
|
|
|
struct ena_admin_feature_aenq_desc { |
|
/* bitmask for AENQ groups the device can report */ |
|
u32 supported_groups; |
|
|
|
/* bitmask for AENQ groups to report */ |
|
u32 enabled_groups; |
|
}; |
|
|
|
struct ena_admin_feature_offload_desc { |
|
/* 0 : TX_L3_csum_ipv4 |
|
* 1 : TX_L4_ipv4_csum_part - The checksum field |
|
* should be initialized with pseudo header checksum |
|
* 2 : TX_L4_ipv4_csum_full |
|
* 3 : TX_L4_ipv6_csum_part - The checksum field |
|
* should be initialized with pseudo header checksum |
|
* 4 : TX_L4_ipv6_csum_full |
|
* 5 : tso_ipv4 |
|
* 6 : tso_ipv6 |
|
* 7 : tso_ecn |
|
*/ |
|
u32 tx; |
|
|
|
/* Receive side supported stateless offload |
|
* 0 : RX_L3_csum_ipv4 - IPv4 checksum |
|
* 1 : RX_L4_ipv4_csum - TCP/UDP/IPv4 checksum |
|
* 2 : RX_L4_ipv6_csum - TCP/UDP/IPv6 checksum |
|
* 3 : RX_hash - Hash calculation |
|
*/ |
|
u32 rx_supported; |
|
|
|
u32 rx_enabled; |
|
}; |
|
|
|
enum ena_admin_hash_functions { |
|
ENA_ADMIN_TOEPLITZ = 1, |
|
ENA_ADMIN_CRC32 = 2, |
|
}; |
|
|
|
struct ena_admin_feature_rss_flow_hash_control { |
|
u32 key_parts; |
|
|
|
u32 reserved; |
|
|
|
u32 key[ENA_ADMIN_RSS_KEY_PARTS]; |
|
}; |
|
|
|
struct ena_admin_feature_rss_flow_hash_function { |
|
/* 7:0 : funcs - bitmask of ena_admin_hash_functions */ |
|
u32 supported_func; |
|
|
|
/* 7:0 : selected_func - bitmask of |
|
* ena_admin_hash_functions |
|
*/ |
|
u32 selected_func; |
|
|
|
/* initial value */ |
|
u32 init_val; |
|
}; |
|
|
|
/* RSS flow hash protocols */ |
|
enum ena_admin_flow_hash_proto { |
|
ENA_ADMIN_RSS_TCP4 = 0, |
|
ENA_ADMIN_RSS_UDP4 = 1, |
|
ENA_ADMIN_RSS_TCP6 = 2, |
|
ENA_ADMIN_RSS_UDP6 = 3, |
|
ENA_ADMIN_RSS_IP4 = 4, |
|
ENA_ADMIN_RSS_IP6 = 5, |
|
ENA_ADMIN_RSS_IP4_FRAG = 6, |
|
ENA_ADMIN_RSS_NOT_IP = 7, |
|
/* TCPv6 with extension header */ |
|
ENA_ADMIN_RSS_TCP6_EX = 8, |
|
/* IPv6 with extension header */ |
|
ENA_ADMIN_RSS_IP6_EX = 9, |
|
ENA_ADMIN_RSS_PROTO_NUM = 16, |
|
}; |
|
|
|
/* RSS flow hash fields */ |
|
enum ena_admin_flow_hash_fields { |
|
/* Ethernet Dest Addr */ |
|
ENA_ADMIN_RSS_L2_DA = BIT(0), |
|
/* Ethernet Src Addr */ |
|
ENA_ADMIN_RSS_L2_SA = BIT(1), |
|
/* ipv4/6 Dest Addr */ |
|
ENA_ADMIN_RSS_L3_DA = BIT(2), |
|
/* ipv4/6 Src Addr */ |
|
ENA_ADMIN_RSS_L3_SA = BIT(3), |
|
/* tcp/udp Dest Port */ |
|
ENA_ADMIN_RSS_L4_DP = BIT(4), |
|
/* tcp/udp Src Port */ |
|
ENA_ADMIN_RSS_L4_SP = BIT(5), |
|
}; |
|
|
|
struct ena_admin_proto_input { |
|
/* flow hash fields (bitwise according to ena_admin_flow_hash_fields) */ |
|
u16 fields; |
|
|
|
u16 reserved2; |
|
}; |
|
|
|
struct ena_admin_feature_rss_hash_control { |
|
struct ena_admin_proto_input supported_fields[ENA_ADMIN_RSS_PROTO_NUM]; |
|
|
|
struct ena_admin_proto_input selected_fields[ENA_ADMIN_RSS_PROTO_NUM]; |
|
|
|
struct ena_admin_proto_input reserved2[ENA_ADMIN_RSS_PROTO_NUM]; |
|
|
|
struct ena_admin_proto_input reserved3[ENA_ADMIN_RSS_PROTO_NUM]; |
|
}; |
|
|
|
struct ena_admin_feature_rss_flow_hash_input { |
|
/* supported hash input sorting |
|
* 1 : L3_sort - support swap L3 addresses if DA is |
|
* smaller than SA |
|
* 2 : L4_sort - support swap L4 ports if DP smaller |
|
* SP |
|
*/ |
|
u16 supported_input_sort; |
|
|
|
/* enabled hash input sorting |
|
* 1 : enable_L3_sort - enable swap L3 addresses if |
|
* DA smaller than SA |
|
* 2 : enable_L4_sort - enable swap L4 ports if DP |
|
* smaller than SP |
|
*/ |
|
u16 enabled_input_sort; |
|
}; |
|
|
|
enum ena_admin_os_type { |
|
ENA_ADMIN_OS_LINUX = 1, |
|
ENA_ADMIN_OS_WIN = 2, |
|
ENA_ADMIN_OS_DPDK = 3, |
|
ENA_ADMIN_OS_FREEBSD = 4, |
|
ENA_ADMIN_OS_IPXE = 5, |
|
ENA_ADMIN_OS_ESXI = 6, |
|
ENA_ADMIN_OS_GROUPS_NUM = 6, |
|
}; |
|
|
|
struct ena_admin_host_info { |
|
/* defined in enum ena_admin_os_type */ |
|
u32 os_type; |
|
|
|
/* os distribution string format */ |
|
u8 os_dist_str[128]; |
|
|
|
/* OS distribution numeric format */ |
|
u32 os_dist; |
|
|
|
/* kernel version string format */ |
|
u8 kernel_ver_str[32]; |
|
|
|
/* Kernel version numeric format */ |
|
u32 kernel_ver; |
|
|
|
/* 7:0 : major |
|
* 15:8 : minor |
|
* 23:16 : sub_minor |
|
* 31:24 : module_type |
|
*/ |
|
u32 driver_version; |
|
|
|
/* features bitmap */ |
|
u32 supported_network_features[2]; |
|
|
|
/* ENA spec version of driver */ |
|
u16 ena_spec_version; |
|
|
|
/* ENA device's Bus, Device and Function |
|
* 2:0 : function |
|
* 7:3 : device |
|
* 15:8 : bus |
|
*/ |
|
u16 bdf; |
|
|
|
/* Number of CPUs */ |
|
u16 num_cpus; |
|
|
|
u16 reserved; |
|
|
|
/* 0 : reserved |
|
* 1 : rx_offset |
|
* 2 : interrupt_moderation |
|
* 3 : rx_buf_mirroring |
|
* 4 : rss_configurable_function_key |
|
* 31:5 : reserved |
|
*/ |
|
u32 driver_supported_features; |
|
}; |
|
|
|
struct ena_admin_rss_ind_table_entry { |
|
u16 cq_idx; |
|
|
|
u16 reserved; |
|
}; |
|
|
|
struct ena_admin_feature_rss_ind_table { |
|
/* min supported table size (2^min_size) */ |
|
u16 min_size; |
|
|
|
/* max supported table size (2^max_size) */ |
|
u16 max_size; |
|
|
|
/* table size (2^size) */ |
|
u16 size; |
|
|
|
u16 reserved; |
|
|
|
/* index of the inline entry. 0xFFFFFFFF means invalid */ |
|
u32 inline_index; |
|
|
|
/* used for updating single entry, ignored when setting the entire |
|
* table through the control buffer. |
|
*/ |
|
struct ena_admin_rss_ind_table_entry inline_entry; |
|
}; |
|
|
|
/* When hint value is 0, driver should use it's own predefined value */ |
|
struct ena_admin_ena_hw_hints { |
|
/* value in ms */ |
|
u16 mmio_read_timeout; |
|
|
|
/* value in ms */ |
|
u16 driver_watchdog_timeout; |
|
|
|
/* Per packet tx completion timeout. value in ms */ |
|
u16 missing_tx_completion_timeout; |
|
|
|
u16 missed_tx_completion_count_threshold_to_reset; |
|
|
|
/* value in ms */ |
|
u16 admin_completion_tx_timeout; |
|
|
|
u16 netdev_wd_timeout; |
|
|
|
u16 max_tx_sgl_size; |
|
|
|
u16 max_rx_sgl_size; |
|
|
|
u16 reserved[8]; |
|
}; |
|
|
|
struct ena_admin_get_feat_cmd { |
|
struct ena_admin_aq_common_desc aq_common_descriptor; |
|
|
|
struct ena_admin_ctrl_buff_info control_buffer; |
|
|
|
struct ena_admin_get_set_feature_common_desc feat_common; |
|
|
|
u32 raw[11]; |
|
}; |
|
|
|
struct ena_admin_queue_ext_feature_desc { |
|
/* version */ |
|
u8 version; |
|
|
|
u8 reserved1[3]; |
|
|
|
union { |
|
struct ena_admin_queue_ext_feature_fields max_queue_ext; |
|
|
|
u32 raw[10]; |
|
}; |
|
}; |
|
|
|
struct ena_admin_get_feat_resp { |
|
struct ena_admin_acq_common_desc acq_common_desc; |
|
|
|
union { |
|
u32 raw[14]; |
|
|
|
struct ena_admin_device_attr_feature_desc dev_attr; |
|
|
|
struct ena_admin_feature_llq_desc llq; |
|
|
|
struct ena_admin_queue_feature_desc max_queue; |
|
|
|
struct ena_admin_queue_ext_feature_desc max_queue_ext; |
|
|
|
struct ena_admin_feature_aenq_desc aenq; |
|
|
|
struct ena_admin_get_feature_link_desc link; |
|
|
|
struct ena_admin_feature_offload_desc offload; |
|
|
|
struct ena_admin_feature_rss_flow_hash_function flow_hash_func; |
|
|
|
struct ena_admin_feature_rss_flow_hash_input flow_hash_input; |
|
|
|
struct ena_admin_feature_rss_ind_table ind_table; |
|
|
|
struct ena_admin_feature_intr_moder_desc intr_moderation; |
|
|
|
struct ena_admin_ena_hw_hints hw_hints; |
|
} u; |
|
}; |
|
|
|
struct ena_admin_set_feat_cmd { |
|
struct ena_admin_aq_common_desc aq_common_descriptor; |
|
|
|
struct ena_admin_ctrl_buff_info control_buffer; |
|
|
|
struct ena_admin_get_set_feature_common_desc feat_common; |
|
|
|
union { |
|
u32 raw[11]; |
|
|
|
/* mtu size */ |
|
struct ena_admin_set_feature_mtu_desc mtu; |
|
|
|
/* host attributes */ |
|
struct ena_admin_set_feature_host_attr_desc host_attr; |
|
|
|
/* AENQ configuration */ |
|
struct ena_admin_feature_aenq_desc aenq; |
|
|
|
/* rss flow hash function */ |
|
struct ena_admin_feature_rss_flow_hash_function flow_hash_func; |
|
|
|
/* rss flow hash input */ |
|
struct ena_admin_feature_rss_flow_hash_input flow_hash_input; |
|
|
|
/* rss indirection table */ |
|
struct ena_admin_feature_rss_ind_table ind_table; |
|
|
|
/* LLQ configuration */ |
|
struct ena_admin_feature_llq_desc llq; |
|
} u; |
|
}; |
|
|
|
struct ena_admin_set_feat_resp { |
|
struct ena_admin_acq_common_desc acq_common_desc; |
|
|
|
union { |
|
u32 raw[14]; |
|
} u; |
|
}; |
|
|
|
struct ena_admin_aenq_common_desc { |
|
u16 group; |
|
|
|
u16 syndrome; |
|
|
|
/* 0 : phase |
|
* 7:1 : reserved - MBZ |
|
*/ |
|
u8 flags; |
|
|
|
u8 reserved1[3]; |
|
|
|
u32 timestamp_low; |
|
|
|
u32 timestamp_high; |
|
}; |
|
|
|
/* asynchronous event notification groups */ |
|
enum ena_admin_aenq_group { |
|
ENA_ADMIN_LINK_CHANGE = 0, |
|
ENA_ADMIN_FATAL_ERROR = 1, |
|
ENA_ADMIN_WARNING = 2, |
|
ENA_ADMIN_NOTIFICATION = 3, |
|
ENA_ADMIN_KEEP_ALIVE = 4, |
|
ENA_ADMIN_AENQ_GROUPS_NUM = 5, |
|
}; |
|
|
|
enum ena_admin_aenq_notification_syndrome { |
|
ENA_ADMIN_UPDATE_HINTS = 2, |
|
}; |
|
|
|
struct ena_admin_aenq_entry { |
|
struct ena_admin_aenq_common_desc aenq_common_desc; |
|
|
|
/* command specific inline data */ |
|
u32 inline_data_w4[12]; |
|
}; |
|
|
|
struct ena_admin_aenq_link_change_desc { |
|
struct ena_admin_aenq_common_desc aenq_common_desc; |
|
|
|
/* 0 : link_status */ |
|
u32 flags; |
|
}; |
|
|
|
struct ena_admin_aenq_keep_alive_desc { |
|
struct ena_admin_aenq_common_desc aenq_common_desc; |
|
|
|
u32 rx_drops_low; |
|
|
|
u32 rx_drops_high; |
|
|
|
u32 tx_drops_low; |
|
|
|
u32 tx_drops_high; |
|
}; |
|
|
|
struct ena_admin_ena_mmio_req_read_less_resp { |
|
u16 req_id; |
|
|
|
u16 reg_off; |
|
|
|
/* value is valid when poll is cleared */ |
|
u32 reg_val; |
|
}; |
|
|
|
/* aq_common_desc */ |
|
#define ENA_ADMIN_AQ_COMMON_DESC_COMMAND_ID_MASK GENMASK(11, 0) |
|
#define ENA_ADMIN_AQ_COMMON_DESC_PHASE_MASK BIT(0) |
|
#define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_SHIFT 1 |
|
#define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_MASK BIT(1) |
|
#define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_SHIFT 2 |
|
#define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK BIT(2) |
|
|
|
/* sq */ |
|
#define ENA_ADMIN_SQ_SQ_DIRECTION_SHIFT 5 |
|
#define ENA_ADMIN_SQ_SQ_DIRECTION_MASK GENMASK(7, 5) |
|
|
|
/* acq_common_desc */ |
|
#define ENA_ADMIN_ACQ_COMMON_DESC_COMMAND_ID_MASK GENMASK(11, 0) |
|
#define ENA_ADMIN_ACQ_COMMON_DESC_PHASE_MASK BIT(0) |
|
|
|
/* aq_create_sq_cmd */ |
|
#define ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_SHIFT 5 |
|
#define ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_MASK GENMASK(7, 5) |
|
#define ENA_ADMIN_AQ_CREATE_SQ_CMD_PLACEMENT_POLICY_MASK GENMASK(3, 0) |
|
#define ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_SHIFT 4 |
|
#define ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_MASK GENMASK(6, 4) |
|
#define ENA_ADMIN_AQ_CREATE_SQ_CMD_IS_PHYSICALLY_CONTIGUOUS_MASK BIT(0) |
|
|
|
/* aq_create_cq_cmd */ |
|
#define ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_SHIFT 5 |
|
#define ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_MASK BIT(5) |
|
#define ENA_ADMIN_AQ_CREATE_CQ_CMD_CQ_ENTRY_SIZE_WORDS_MASK GENMASK(4, 0) |
|
|
|
/* get_set_feature_common_desc */ |
|
#define ENA_ADMIN_GET_SET_FEATURE_COMMON_DESC_SELECT_MASK GENMASK(1, 0) |
|
|
|
/* get_feature_link_desc */ |
|
#define ENA_ADMIN_GET_FEATURE_LINK_DESC_AUTONEG_MASK BIT(0) |
|
#define ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_SHIFT 1 |
|
#define ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_MASK BIT(1) |
|
|
|
/* feature_offload_desc */ |
|
#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L3_CSUM_IPV4_MASK BIT(0) |
|
#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_SHIFT 1 |
|
#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK BIT(1) |
|
#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_SHIFT 2 |
|
#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_MASK BIT(2) |
|
#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_SHIFT 3 |
|
#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_MASK BIT(3) |
|
#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_SHIFT 4 |
|
#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_MASK BIT(4) |
|
#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_SHIFT 5 |
|
#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK BIT(5) |
|
#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_SHIFT 6 |
|
#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_MASK BIT(6) |
|
#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_SHIFT 7 |
|
#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_MASK BIT(7) |
|
#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L3_CSUM_IPV4_MASK BIT(0) |
|
#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_SHIFT 1 |
|
#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK BIT(1) |
|
#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_SHIFT 2 |
|
#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_MASK BIT(2) |
|
#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_SHIFT 3 |
|
#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_MASK BIT(3) |
|
|
|
/* feature_rss_flow_hash_function */ |
|
#define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_FUNCS_MASK GENMASK(7, 0) |
|
#define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_SELECTED_FUNC_MASK GENMASK(7, 0) |
|
|
|
/* feature_rss_flow_hash_input */ |
|
#define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_SHIFT 1 |
|
#define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_MASK BIT(1) |
|
#define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_SHIFT 2 |
|
#define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_MASK BIT(2) |
|
#define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_SHIFT 1 |
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#define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_MASK BIT(1) |
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#define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_SHIFT 2 |
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#define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_MASK BIT(2) |
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/* host_info */ |
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#define ENA_ADMIN_HOST_INFO_MAJOR_MASK GENMASK(7, 0) |
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#define ENA_ADMIN_HOST_INFO_MINOR_SHIFT 8 |
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#define ENA_ADMIN_HOST_INFO_MINOR_MASK GENMASK(15, 8) |
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#define ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT 16 |
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#define ENA_ADMIN_HOST_INFO_SUB_MINOR_MASK GENMASK(23, 16) |
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#define ENA_ADMIN_HOST_INFO_MODULE_TYPE_SHIFT 24 |
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#define ENA_ADMIN_HOST_INFO_MODULE_TYPE_MASK GENMASK(31, 24) |
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#define ENA_ADMIN_HOST_INFO_FUNCTION_MASK GENMASK(2, 0) |
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#define ENA_ADMIN_HOST_INFO_DEVICE_SHIFT 3 |
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#define ENA_ADMIN_HOST_INFO_DEVICE_MASK GENMASK(7, 3) |
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#define ENA_ADMIN_HOST_INFO_BUS_SHIFT 8 |
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#define ENA_ADMIN_HOST_INFO_BUS_MASK GENMASK(15, 8) |
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#define ENA_ADMIN_HOST_INFO_RX_OFFSET_SHIFT 1 |
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#define ENA_ADMIN_HOST_INFO_RX_OFFSET_MASK BIT(1) |
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#define ENA_ADMIN_HOST_INFO_INTERRUPT_MODERATION_SHIFT 2 |
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#define ENA_ADMIN_HOST_INFO_INTERRUPT_MODERATION_MASK BIT(2) |
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#define ENA_ADMIN_HOST_INFO_RX_BUF_MIRRORING_SHIFT 3 |
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#define ENA_ADMIN_HOST_INFO_RX_BUF_MIRRORING_MASK BIT(3) |
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#define ENA_ADMIN_HOST_INFO_RSS_CONFIGURABLE_FUNCTION_KEY_SHIFT 4 |
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#define ENA_ADMIN_HOST_INFO_RSS_CONFIGURABLE_FUNCTION_KEY_MASK BIT(4) |
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/* aenq_common_desc */ |
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#define ENA_ADMIN_AENQ_COMMON_DESC_PHASE_MASK BIT(0) |
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/* aenq_link_change_desc */ |
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#define ENA_ADMIN_AENQ_LINK_CHANGE_DESC_LINK_STATUS_MASK BIT(0) |
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#endif /* _ENA_ADMIN_H_ */
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