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147 lines
4.9 KiB
147 lines
4.9 KiB
/* SPDX-License-Identifier: GPL-2.0-only */ |
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/* Altera TSE SGDMA and MSGDMA Linux driver |
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* Copyright (C) 2014 Altera Corporation. All rights reserved |
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*/ |
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#ifndef __ALTERA_MSGDMAHW_H__ |
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#define __ALTERA_MSGDMAHW_H__ |
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/* mSGDMA extended descriptor format |
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*/ |
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struct msgdma_extended_desc { |
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u32 read_addr_lo; /* data buffer source address low bits */ |
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u32 write_addr_lo; /* data buffer destination address low bits */ |
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u32 len; /* the number of bytes to transfer |
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* per descriptor |
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*/ |
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u32 burst_seq_num; /* bit 31:24 write burst |
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* bit 23:16 read burst |
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* bit 15:0 sequence number |
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*/ |
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u32 stride; /* bit 31:16 write stride |
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* bit 15:0 read stride |
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*/ |
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u32 read_addr_hi; /* data buffer source address high bits */ |
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u32 write_addr_hi; /* data buffer destination address high bits */ |
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u32 control; /* characteristics of the transfer */ |
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}; |
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/* mSGDMA descriptor control field bit definitions |
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*/ |
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#define MSGDMA_DESC_CTL_SET_CH(x) ((x) & 0xff) |
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#define MSGDMA_DESC_CTL_GEN_SOP BIT(8) |
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#define MSGDMA_DESC_CTL_GEN_EOP BIT(9) |
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#define MSGDMA_DESC_CTL_PARK_READS BIT(10) |
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#define MSGDMA_DESC_CTL_PARK_WRITES BIT(11) |
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#define MSGDMA_DESC_CTL_END_ON_EOP BIT(12) |
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#define MSGDMA_DESC_CTL_END_ON_LEN BIT(13) |
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#define MSGDMA_DESC_CTL_TR_COMP_IRQ BIT(14) |
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#define MSGDMA_DESC_CTL_EARLY_IRQ BIT(15) |
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#define MSGDMA_DESC_CTL_TR_ERR_IRQ (0xff << 16) |
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#define MSGDMA_DESC_CTL_EARLY_DONE BIT(24) |
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/* Writing ‘1’ to the ‘go’ bit commits the entire descriptor into the |
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* descriptor FIFO(s) |
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*/ |
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#define MSGDMA_DESC_CTL_GO BIT(31) |
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/* Tx buffer control flags |
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*/ |
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#define MSGDMA_DESC_CTL_TX_FIRST (MSGDMA_DESC_CTL_GEN_SOP | \ |
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MSGDMA_DESC_CTL_GO) |
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#define MSGDMA_DESC_CTL_TX_MIDDLE (MSGDMA_DESC_CTL_GO) |
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#define MSGDMA_DESC_CTL_TX_LAST (MSGDMA_DESC_CTL_GEN_EOP | \ |
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MSGDMA_DESC_CTL_TR_COMP_IRQ | \ |
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MSGDMA_DESC_CTL_GO) |
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#define MSGDMA_DESC_CTL_TX_SINGLE (MSGDMA_DESC_CTL_GEN_SOP | \ |
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MSGDMA_DESC_CTL_GEN_EOP | \ |
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MSGDMA_DESC_CTL_TR_COMP_IRQ | \ |
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MSGDMA_DESC_CTL_GO) |
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#define MSGDMA_DESC_CTL_RX_SINGLE (MSGDMA_DESC_CTL_END_ON_EOP | \ |
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MSGDMA_DESC_CTL_END_ON_LEN | \ |
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MSGDMA_DESC_CTL_TR_COMP_IRQ | \ |
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MSGDMA_DESC_CTL_EARLY_IRQ | \ |
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MSGDMA_DESC_CTL_TR_ERR_IRQ | \ |
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MSGDMA_DESC_CTL_GO) |
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/* mSGDMA extended descriptor stride definitions |
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*/ |
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#define MSGDMA_DESC_TX_STRIDE (0x00010001) |
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#define MSGDMA_DESC_RX_STRIDE (0x00010001) |
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/* mSGDMA dispatcher control and status register map |
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*/ |
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struct msgdma_csr { |
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u32 status; /* Read/Clear */ |
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u32 control; /* Read/Write */ |
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u32 rw_fill_level; /* bit 31:16 - write fill level |
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* bit 15:0 - read fill level |
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*/ |
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u32 resp_fill_level; /* bit 15:0 */ |
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u32 rw_seq_num; /* bit 31:16 - write sequence number |
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* bit 15:0 - read sequence number |
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*/ |
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u32 pad[3]; /* reserved */ |
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}; |
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/* mSGDMA CSR status register bit definitions |
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*/ |
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#define MSGDMA_CSR_STAT_BUSY BIT(0) |
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#define MSGDMA_CSR_STAT_DESC_BUF_EMPTY BIT(1) |
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#define MSGDMA_CSR_STAT_DESC_BUF_FULL BIT(2) |
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#define MSGDMA_CSR_STAT_RESP_BUF_EMPTY BIT(3) |
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#define MSGDMA_CSR_STAT_RESP_BUF_FULL BIT(4) |
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#define MSGDMA_CSR_STAT_STOPPED BIT(5) |
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#define MSGDMA_CSR_STAT_RESETTING BIT(6) |
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#define MSGDMA_CSR_STAT_STOPPED_ON_ERR BIT(7) |
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#define MSGDMA_CSR_STAT_STOPPED_ON_EARLY BIT(8) |
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#define MSGDMA_CSR_STAT_IRQ BIT(9) |
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#define MSGDMA_CSR_STAT_MASK 0x3FF |
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#define MSGDMA_CSR_STAT_MASK_WITHOUT_IRQ 0x1FF |
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#define MSGDMA_CSR_STAT_BUSY_GET(v) GET_BIT_VALUE(v, 0) |
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#define MSGDMA_CSR_STAT_DESC_BUF_EMPTY_GET(v) GET_BIT_VALUE(v, 1) |
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#define MSGDMA_CSR_STAT_DESC_BUF_FULL_GET(v) GET_BIT_VALUE(v, 2) |
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#define MSGDMA_CSR_STAT_RESP_BUF_EMPTY_GET(v) GET_BIT_VALUE(v, 3) |
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#define MSGDMA_CSR_STAT_RESP_BUF_FULL_GET(v) GET_BIT_VALUE(v, 4) |
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#define MSGDMA_CSR_STAT_STOPPED_GET(v) GET_BIT_VALUE(v, 5) |
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#define MSGDMA_CSR_STAT_RESETTING_GET(v) GET_BIT_VALUE(v, 6) |
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#define MSGDMA_CSR_STAT_STOPPED_ON_ERR_GET(v) GET_BIT_VALUE(v, 7) |
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#define MSGDMA_CSR_STAT_STOPPED_ON_EARLY_GET(v) GET_BIT_VALUE(v, 8) |
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#define MSGDMA_CSR_STAT_IRQ_GET(v) GET_BIT_VALUE(v, 9) |
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/* mSGDMA CSR control register bit definitions |
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*/ |
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#define MSGDMA_CSR_CTL_STOP BIT(0) |
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#define MSGDMA_CSR_CTL_RESET BIT(1) |
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#define MSGDMA_CSR_CTL_STOP_ON_ERR BIT(2) |
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#define MSGDMA_CSR_CTL_STOP_ON_EARLY BIT(3) |
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#define MSGDMA_CSR_CTL_GLOBAL_INTR BIT(4) |
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#define MSGDMA_CSR_CTL_STOP_DESCS BIT(5) |
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/* mSGDMA CSR fill level bits |
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*/ |
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#define MSGDMA_CSR_WR_FILL_LEVEL_GET(v) (((v) & 0xffff0000) >> 16) |
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#define MSGDMA_CSR_RD_FILL_LEVEL_GET(v) ((v) & 0x0000ffff) |
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#define MSGDMA_CSR_RESP_FILL_LEVEL_GET(v) ((v) & 0x0000ffff) |
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/* mSGDMA response register map |
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*/ |
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struct msgdma_response { |
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u32 bytes_transferred; |
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u32 status; |
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}; |
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#define msgdma_respoffs(a) (offsetof(struct msgdma_response, a)) |
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#define msgdma_csroffs(a) (offsetof(struct msgdma_csr, a)) |
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#define msgdma_descroffs(a) (offsetof(struct msgdma_extended_desc, a)) |
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/* mSGDMA response register bit definitions |
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*/ |
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#define MSGDMA_RESP_EARLY_TERM BIT(8) |
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#define MSGDMA_RESP_ERR_MASK 0xFF |
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#endif /* __ALTERA_MSGDMA_H__*/
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