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210 lines
5.6 KiB
210 lines
5.6 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* sun6i_hwspinlock.c - hardware spinlock driver for sun6i compatible Allwinner SoCs |
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* Copyright (C) 2020 Wilken Gottwalt <[email protected]> |
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*/ |
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#include <linux/clk.h> |
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#include <linux/debugfs.h> |
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#include <linux/errno.h> |
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#include <linux/hwspinlock.h> |
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#include <linux/io.h> |
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#include <linux/module.h> |
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#include <linux/of.h> |
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#include <linux/platform_device.h> |
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#include <linux/reset.h> |
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#include <linux/slab.h> |
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#include <linux/spinlock.h> |
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#include <linux/types.h> |
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#include "hwspinlock_internal.h" |
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#define DRIVER_NAME "sun6i_hwspinlock" |
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#define SPINLOCK_BASE_ID 0 /* there is only one hwspinlock device per SoC */ |
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#define SPINLOCK_SYSSTATUS_REG 0x0000 |
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#define SPINLOCK_LOCK_REGN 0x0100 |
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#define SPINLOCK_NOTTAKEN 0 |
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struct sun6i_hwspinlock_data { |
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struct hwspinlock_device *bank; |
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struct reset_control *reset; |
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struct clk *ahb_clk; |
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struct dentry *debugfs; |
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int nlocks; |
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}; |
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#ifdef CONFIG_DEBUG_FS |
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static int hwlocks_supported_show(struct seq_file *seqf, void *unused) |
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{ |
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struct sun6i_hwspinlock_data *priv = seqf->private; |
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seq_printf(seqf, "%d\n", priv->nlocks); |
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return 0; |
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} |
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DEFINE_SHOW_ATTRIBUTE(hwlocks_supported); |
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static void sun6i_hwspinlock_debugfs_init(struct sun6i_hwspinlock_data *priv) |
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{ |
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priv->debugfs = debugfs_create_dir(DRIVER_NAME, NULL); |
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debugfs_create_file("supported", 0444, priv->debugfs, priv, &hwlocks_supported_fops); |
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} |
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#else |
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static void sun6i_hwspinlock_debugfs_init(struct sun6i_hwspinlock_data *priv) |
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{ |
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} |
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#endif |
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static int sun6i_hwspinlock_trylock(struct hwspinlock *lock) |
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{ |
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void __iomem *lock_addr = lock->priv; |
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return (readl(lock_addr) == SPINLOCK_NOTTAKEN); |
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} |
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static void sun6i_hwspinlock_unlock(struct hwspinlock *lock) |
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{ |
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void __iomem *lock_addr = lock->priv; |
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writel(SPINLOCK_NOTTAKEN, lock_addr); |
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} |
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static const struct hwspinlock_ops sun6i_hwspinlock_ops = { |
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.trylock = sun6i_hwspinlock_trylock, |
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.unlock = sun6i_hwspinlock_unlock, |
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}; |
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static void sun6i_hwspinlock_disable(void *data) |
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{ |
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struct sun6i_hwspinlock_data *priv = data; |
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debugfs_remove_recursive(priv->debugfs); |
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clk_disable_unprepare(priv->ahb_clk); |
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reset_control_assert(priv->reset); |
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} |
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static int sun6i_hwspinlock_probe(struct platform_device *pdev) |
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{ |
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struct sun6i_hwspinlock_data *priv; |
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struct hwspinlock *hwlock; |
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void __iomem *io_base; |
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u32 num_banks; |
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int err, i; |
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io_base = devm_platform_ioremap_resource(pdev, SPINLOCK_BASE_ID); |
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if (IS_ERR(io_base)) |
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return PTR_ERR(io_base); |
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priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); |
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if (!priv) |
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return -ENOMEM; |
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priv->ahb_clk = devm_clk_get(&pdev->dev, "ahb"); |
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if (IS_ERR(priv->ahb_clk)) { |
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err = PTR_ERR(priv->ahb_clk); |
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dev_err(&pdev->dev, "unable to get AHB clock (%d)\n", err); |
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return err; |
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} |
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priv->reset = devm_reset_control_get(&pdev->dev, "ahb"); |
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if (IS_ERR(priv->reset)) |
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return dev_err_probe(&pdev->dev, PTR_ERR(priv->reset), |
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"unable to get reset control\n"); |
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err = reset_control_deassert(priv->reset); |
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if (err) { |
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dev_err(&pdev->dev, "deassert reset control failure (%d)\n", err); |
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return err; |
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} |
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err = clk_prepare_enable(priv->ahb_clk); |
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if (err) { |
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dev_err(&pdev->dev, "unable to prepare AHB clk (%d)\n", err); |
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goto clk_fail; |
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} |
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/* |
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* bit 28 and 29 represents the hwspinlock setup |
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* |
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* every datasheet (A64, A80, A83T, H3, H5, H6 ...) says the default value is 0x1 and 0x1 |
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* to 0x4 represent 32, 64, 128 and 256 locks |
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* but later datasheets (H5, H6) say 00, 01, 10, 11 represent 32, 64, 128 and 256 locks, |
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* but that would mean H5 and H6 have 64 locks, while their datasheets talk about 32 locks |
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* all the time, not a single mentioning of 64 locks |
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* the 0x4 value is also not representable by 2 bits alone, so some datasheets are not |
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* correct |
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* one thing have all in common, default value of the sysstatus register is 0x10000000, |
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* which results in bit 28 being set |
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* this is the reason 0x1 is considered being 32 locks and bit 30 is taken into account |
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* verified on H2+ (datasheet 0x1 = 32 locks) and H5 (datasheet 01 = 64 locks) |
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*/ |
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num_banks = readl(io_base + SPINLOCK_SYSSTATUS_REG) >> 28; |
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switch (num_banks) { |
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case 1 ... 4: |
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priv->nlocks = 1 << (4 + num_banks); |
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break; |
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default: |
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err = -EINVAL; |
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dev_err(&pdev->dev, "unsupported hwspinlock setup (%d)\n", num_banks); |
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goto bank_fail; |
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} |
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priv->bank = devm_kzalloc(&pdev->dev, struct_size(priv->bank, lock, priv->nlocks), |
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GFP_KERNEL); |
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if (!priv->bank) { |
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err = -ENOMEM; |
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goto bank_fail; |
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} |
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for (i = 0; i < priv->nlocks; ++i) { |
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hwlock = &priv->bank->lock[i]; |
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hwlock->priv = io_base + SPINLOCK_LOCK_REGN + sizeof(u32) * i; |
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} |
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/* failure of debugfs is considered non-fatal */ |
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sun6i_hwspinlock_debugfs_init(priv); |
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if (IS_ERR(priv->debugfs)) |
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priv->debugfs = NULL; |
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err = devm_add_action_or_reset(&pdev->dev, sun6i_hwspinlock_disable, priv); |
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if (err) { |
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dev_err(&pdev->dev, "failed to add hwspinlock disable action\n"); |
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goto bank_fail; |
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} |
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platform_set_drvdata(pdev, priv); |
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return devm_hwspin_lock_register(&pdev->dev, priv->bank, &sun6i_hwspinlock_ops, |
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SPINLOCK_BASE_ID, priv->nlocks); |
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bank_fail: |
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clk_disable_unprepare(priv->ahb_clk); |
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clk_fail: |
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reset_control_assert(priv->reset); |
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return err; |
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} |
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static const struct of_device_id sun6i_hwspinlock_ids[] = { |
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{ .compatible = "allwinner,sun6i-a31-hwspinlock", }, |
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{}, |
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}; |
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MODULE_DEVICE_TABLE(of, sun6i_hwspinlock_ids); |
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static struct platform_driver sun6i_hwspinlock_driver = { |
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.probe = sun6i_hwspinlock_probe, |
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.driver = { |
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.name = DRIVER_NAME, |
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.of_match_table = sun6i_hwspinlock_ids, |
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}, |
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}; |
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module_platform_driver(sun6i_hwspinlock_driver); |
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MODULE_LICENSE("GPL"); |
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MODULE_DESCRIPTION("SUN6I hardware spinlock driver"); |
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MODULE_AUTHOR("Wilken Gottwalt <[email protected]>");
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