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302 lines
6.4 KiB
302 lines
6.4 KiB
/* SPDX-License-Identifier: GPL-2.0 */ |
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#ifndef __NITROX_DEV_H |
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#define __NITROX_DEV_H |
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#include <linux/dma-mapping.h> |
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#include <linux/interrupt.h> |
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#include <linux/pci.h> |
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#include <linux/if.h> |
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#define VERSION_LEN 32 |
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/* Maximum queues in PF mode */ |
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#define MAX_PF_QUEUES 64 |
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/* Maximum device queues */ |
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#define MAX_DEV_QUEUES (MAX_PF_QUEUES) |
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/* Maximum UCD Blocks */ |
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#define CNN55XX_MAX_UCD_BLOCKS 8 |
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/** |
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* struct nitrox_cmdq - NITROX command queue |
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* @cmd_qlock: command queue lock |
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* @resp_qlock: response queue lock |
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* @backlog_qlock: backlog queue lock |
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* @ndev: NITROX device |
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* @response_head: submitted request list |
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* @backlog_head: backlog queue |
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* @dbell_csr_addr: doorbell register address for this queue |
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* @compl_cnt_csr_addr: completion count register address of the slc port |
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* @base: command queue base address |
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* @dma: dma address of the base |
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* @pending_count: request pending at device |
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* @backlog_count: backlog request count |
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* @write_idx: next write index for the command |
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* @instr_size: command size |
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* @qno: command queue number |
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* @qsize: command queue size |
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* @unalign_base: unaligned base address |
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* @unalign_dma: unaligned dma address |
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*/ |
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struct nitrox_cmdq { |
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spinlock_t cmd_qlock; |
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spinlock_t resp_qlock; |
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spinlock_t backlog_qlock; |
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struct nitrox_device *ndev; |
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struct list_head response_head; |
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struct list_head backlog_head; |
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u8 __iomem *dbell_csr_addr; |
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u8 __iomem *compl_cnt_csr_addr; |
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u8 *base; |
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dma_addr_t dma; |
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struct work_struct backlog_qflush; |
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atomic_t pending_count; |
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atomic_t backlog_count; |
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int write_idx; |
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u8 instr_size; |
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u8 qno; |
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u32 qsize; |
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u8 *unalign_base; |
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dma_addr_t unalign_dma; |
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}; |
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/** |
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* struct nitrox_hw - NITROX hardware information |
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* @partname: partname ex: CNN55xxx-xxx |
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* @fw_name: firmware version |
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* @freq: NITROX frequency |
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* @vendor_id: vendor ID |
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* @device_id: device ID |
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* @revision_id: revision ID |
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* @se_cores: number of symmetric cores |
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* @ae_cores: number of asymmetric cores |
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* @zip_cores: number of zip cores |
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*/ |
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struct nitrox_hw { |
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char partname[IFNAMSIZ * 2]; |
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char fw_name[CNN55XX_MAX_UCD_BLOCKS][VERSION_LEN]; |
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int freq; |
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u16 vendor_id; |
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u16 device_id; |
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u8 revision_id; |
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u8 se_cores; |
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u8 ae_cores; |
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u8 zip_cores; |
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}; |
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struct nitrox_stats { |
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atomic64_t posted; |
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atomic64_t completed; |
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atomic64_t dropped; |
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}; |
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#define IRQ_NAMESZ 32 |
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struct nitrox_q_vector { |
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char name[IRQ_NAMESZ]; |
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bool valid; |
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int ring; |
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struct tasklet_struct resp_tasklet; |
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union { |
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struct nitrox_cmdq *cmdq; |
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struct nitrox_device *ndev; |
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}; |
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}; |
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enum mcode_type { |
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MCODE_TYPE_INVALID, |
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MCODE_TYPE_AE, |
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MCODE_TYPE_SE_SSL, |
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MCODE_TYPE_SE_IPSEC, |
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}; |
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/** |
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* mbox_msg - Mailbox message data |
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* @type: message type |
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* @opcode: message opcode |
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* @data: message data |
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*/ |
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union mbox_msg { |
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u64 value; |
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struct { |
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u64 type: 2; |
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u64 opcode: 6; |
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u64 data: 58; |
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}; |
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struct { |
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u64 type: 2; |
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u64 opcode: 6; |
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u64 chipid: 8; |
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u64 vfid: 8; |
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} id; |
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struct { |
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u64 type: 2; |
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u64 opcode: 6; |
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u64 count: 4; |
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u64 info: 40; |
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u64 next_se_grp: 3; |
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u64 next_ae_grp: 3; |
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} mcode_info; |
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}; |
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/** |
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* nitrox_vfdev - NITROX VF device instance in PF |
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* @state: VF device state |
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* @vfno: VF number |
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* @nr_queues: number of queues enabled in VF |
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* @ring: ring to communicate with VF |
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* @msg: Mailbox message data from VF |
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* @mbx_resp: Mailbox counters |
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*/ |
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struct nitrox_vfdev { |
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atomic_t state; |
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int vfno; |
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int nr_queues; |
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int ring; |
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union mbox_msg msg; |
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atomic64_t mbx_resp; |
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}; |
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/** |
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* struct nitrox_iov - SR-IOV information |
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* @num_vfs: number of VF(s) enabled |
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* @max_vf_queues: Maximum number of queues allowed for VF |
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* @vfdev: VF(s) devices |
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* @pf2vf_wq: workqueue for PF2VF communication |
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* @msix: MSI-X entry for PF in SR-IOV case |
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*/ |
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struct nitrox_iov { |
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int num_vfs; |
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int max_vf_queues; |
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struct nitrox_vfdev *vfdev; |
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struct workqueue_struct *pf2vf_wq; |
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struct msix_entry msix; |
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}; |
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/* |
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* NITROX Device states |
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*/ |
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enum ndev_state { |
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__NDEV_NOT_READY, |
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__NDEV_READY, |
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__NDEV_IN_RESET, |
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}; |
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/* NITROX support modes for VF(s) */ |
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enum vf_mode { |
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__NDEV_MODE_PF, |
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__NDEV_MODE_VF16, |
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__NDEV_MODE_VF32, |
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__NDEV_MODE_VF64, |
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__NDEV_MODE_VF128, |
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}; |
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#define __NDEV_SRIOV_BIT 0 |
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/* command queue size */ |
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#define DEFAULT_CMD_QLEN 2048 |
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/* command timeout in milliseconds */ |
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#define CMD_TIMEOUT 2000 |
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#define DEV(ndev) ((struct device *)(&(ndev)->pdev->dev)) |
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#define NITROX_CSR_ADDR(ndev, offset) \ |
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((ndev)->bar_addr + (offset)) |
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/** |
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* struct nitrox_device - NITROX Device Information. |
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* @list: pointer to linked list of devices |
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* @bar_addr: iomap address |
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* @pdev: PCI device information |
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* @state: NITROX device state |
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* @flags: flags to indicate device the features |
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* @timeout: Request timeout in jiffies |
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* @refcnt: Device usage count |
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* @idx: device index (0..N) |
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* @node: NUMA node id attached |
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* @qlen: Command queue length |
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* @nr_queues: Number of command queues |
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* @mode: Device mode PF/VF |
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* @ctx_pool: DMA pool for crypto context |
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* @pkt_inq: Packet input rings |
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* @aqmq: AQM command queues |
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* @qvec: MSI-X queue vectors information |
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* @iov: SR-IOV informatin |
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* @num_vecs: number of MSI-X vectors |
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* @stats: request statistics |
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* @hw: hardware information |
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* @debugfs_dir: debugfs directory |
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*/ |
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struct nitrox_device { |
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struct list_head list; |
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u8 __iomem *bar_addr; |
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struct pci_dev *pdev; |
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atomic_t state; |
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unsigned long flags; |
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unsigned long timeout; |
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refcount_t refcnt; |
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u8 idx; |
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int node; |
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u16 qlen; |
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u16 nr_queues; |
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enum vf_mode mode; |
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struct dma_pool *ctx_pool; |
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struct nitrox_cmdq *pkt_inq; |
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struct nitrox_cmdq *aqmq[MAX_DEV_QUEUES] ____cacheline_aligned_in_smp; |
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struct nitrox_q_vector *qvec; |
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struct nitrox_iov iov; |
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int num_vecs; |
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struct nitrox_stats stats; |
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struct nitrox_hw hw; |
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#if IS_ENABLED(CONFIG_DEBUG_FS) |
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struct dentry *debugfs_dir; |
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#endif |
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}; |
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/** |
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* nitrox_read_csr - Read from device register |
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* @ndev: NITROX device |
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* @offset: offset of the register to read |
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* |
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* Returns: value read |
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*/ |
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static inline u64 nitrox_read_csr(struct nitrox_device *ndev, u64 offset) |
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{ |
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return readq(ndev->bar_addr + offset); |
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} |
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/** |
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* nitrox_write_csr - Write to device register |
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* @ndev: NITROX device |
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* @offset: offset of the register to write |
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* @value: value to write |
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*/ |
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static inline void nitrox_write_csr(struct nitrox_device *ndev, u64 offset, |
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u64 value) |
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{ |
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writeq(value, (ndev->bar_addr + offset)); |
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} |
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static inline bool nitrox_ready(struct nitrox_device *ndev) |
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{ |
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return atomic_read(&ndev->state) == __NDEV_READY; |
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} |
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static inline bool nitrox_vfdev_ready(struct nitrox_vfdev *vfdev) |
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{ |
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return atomic_read(&vfdev->state) == __NDEV_READY; |
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} |
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#endif /* __NITROX_DEV_H */
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