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278 lines
6.7 KiB
278 lines
6.7 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* Copyright (c) 2018 NVIDIA CORPORATION. All rights reserved. |
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* |
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* based on clk-mux.c |
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* |
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* Copyright (C) 2011 Sascha Hauer, Pengutronix <[email protected]> |
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* Copyright (C) 2011 Richard Zhao, Linaro <[email protected]> |
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* Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <[email protected]> |
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* |
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*/ |
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#include <linux/clk-provider.h> |
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#include <linux/err.h> |
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#include <linux/io.h> |
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#include <linux/types.h> |
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#include "clk.h" |
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#define DIV_MASK GENMASK(7, 0) |
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#define MUX_SHIFT 29 |
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#define MUX_MASK GENMASK(MUX_SHIFT + 2, MUX_SHIFT) |
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#define SDMMC_MUL 2 |
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#define get_max_div(d) DIV_MASK |
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#define get_div_field(val) ((val) & DIV_MASK) |
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#define get_mux_field(val) (((val) & MUX_MASK) >> MUX_SHIFT) |
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static const char * const mux_sdmmc_parents[] = { |
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"pll_p", "pll_c4_out2", "pll_c4_out0", "pll_c4_out1", "clk_m" |
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}; |
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static const u8 mux_lj_idx[] = { |
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[0] = 0, [1] = 1, [2] = 2, [3] = 5, [4] = 6 |
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}; |
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static const u8 mux_non_lj_idx[] = { |
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[0] = 0, [1] = 3, [2] = 7, [3] = 4, [4] = 6 |
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}; |
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static u8 clk_sdmmc_mux_get_parent(struct clk_hw *hw) |
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{ |
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struct tegra_sdmmc_mux *sdmmc_mux = to_clk_sdmmc_mux(hw); |
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int num_parents, i; |
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u32 src, val; |
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const u8 *mux_idx; |
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num_parents = clk_hw_get_num_parents(hw); |
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val = readl_relaxed(sdmmc_mux->reg); |
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src = get_mux_field(val); |
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if (get_div_field(val)) |
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mux_idx = mux_non_lj_idx; |
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else |
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mux_idx = mux_lj_idx; |
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for (i = 0; i < num_parents; i++) { |
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if (mux_idx[i] == src) |
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return i; |
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} |
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WARN(1, "Unknown parent selector %d\n", src); |
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return 0; |
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} |
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static int clk_sdmmc_mux_set_parent(struct clk_hw *hw, u8 index) |
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{ |
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struct tegra_sdmmc_mux *sdmmc_mux = to_clk_sdmmc_mux(hw); |
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u32 val; |
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val = readl_relaxed(sdmmc_mux->reg); |
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if (get_div_field(val)) |
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index = mux_non_lj_idx[index]; |
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else |
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index = mux_lj_idx[index]; |
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val &= ~MUX_MASK; |
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val |= index << MUX_SHIFT; |
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writel(val, sdmmc_mux->reg); |
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return 0; |
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} |
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static unsigned long clk_sdmmc_mux_recalc_rate(struct clk_hw *hw, |
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unsigned long parent_rate) |
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{ |
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struct tegra_sdmmc_mux *sdmmc_mux = to_clk_sdmmc_mux(hw); |
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u32 val; |
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int div; |
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u64 rate = parent_rate; |
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val = readl_relaxed(sdmmc_mux->reg); |
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div = get_div_field(val); |
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div += SDMMC_MUL; |
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rate *= SDMMC_MUL; |
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rate += div - 1; |
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do_div(rate, div); |
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return rate; |
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} |
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static int clk_sdmmc_mux_determine_rate(struct clk_hw *hw, |
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struct clk_rate_request *req) |
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{ |
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struct tegra_sdmmc_mux *sdmmc_mux = to_clk_sdmmc_mux(hw); |
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int div; |
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unsigned long output_rate = req->best_parent_rate; |
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req->rate = max(req->rate, req->min_rate); |
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req->rate = min(req->rate, req->max_rate); |
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if (!req->rate) |
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return output_rate; |
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div = div_frac_get(req->rate, output_rate, 8, 1, sdmmc_mux->div_flags); |
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if (div < 0) |
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div = 0; |
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if (sdmmc_mux->div_flags & TEGRA_DIVIDER_ROUND_UP) |
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req->rate = DIV_ROUND_UP(output_rate * SDMMC_MUL, |
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div + SDMMC_MUL); |
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else |
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req->rate = output_rate * SDMMC_MUL / (div + SDMMC_MUL); |
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return 0; |
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} |
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static int clk_sdmmc_mux_set_rate(struct clk_hw *hw, unsigned long rate, |
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unsigned long parent_rate) |
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{ |
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struct tegra_sdmmc_mux *sdmmc_mux = to_clk_sdmmc_mux(hw); |
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int div; |
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unsigned long flags = 0; |
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u32 val; |
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u8 src; |
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div = div_frac_get(rate, parent_rate, 8, 1, sdmmc_mux->div_flags); |
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if (div < 0) |
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return div; |
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if (sdmmc_mux->lock) |
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spin_lock_irqsave(sdmmc_mux->lock, flags); |
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src = clk_sdmmc_mux_get_parent(hw); |
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if (div) |
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src = mux_non_lj_idx[src]; |
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else |
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src = mux_lj_idx[src]; |
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val = src << MUX_SHIFT; |
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val |= div; |
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writel(val, sdmmc_mux->reg); |
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fence_udelay(2, sdmmc_mux->reg); |
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if (sdmmc_mux->lock) |
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spin_unlock_irqrestore(sdmmc_mux->lock, flags); |
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return 0; |
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} |
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static int clk_sdmmc_mux_is_enabled(struct clk_hw *hw) |
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{ |
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struct tegra_sdmmc_mux *sdmmc_mux = to_clk_sdmmc_mux(hw); |
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const struct clk_ops *gate_ops = sdmmc_mux->gate_ops; |
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struct clk_hw *gate_hw = &sdmmc_mux->gate.hw; |
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__clk_hw_set_clk(gate_hw, hw); |
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return gate_ops->is_enabled(gate_hw); |
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} |
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static int clk_sdmmc_mux_enable(struct clk_hw *hw) |
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{ |
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struct tegra_sdmmc_mux *sdmmc_mux = to_clk_sdmmc_mux(hw); |
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const struct clk_ops *gate_ops = sdmmc_mux->gate_ops; |
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struct clk_hw *gate_hw = &sdmmc_mux->gate.hw; |
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__clk_hw_set_clk(gate_hw, hw); |
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return gate_ops->enable(gate_hw); |
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} |
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static void clk_sdmmc_mux_disable(struct clk_hw *hw) |
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{ |
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struct tegra_sdmmc_mux *sdmmc_mux = to_clk_sdmmc_mux(hw); |
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const struct clk_ops *gate_ops = sdmmc_mux->gate_ops; |
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struct clk_hw *gate_hw = &sdmmc_mux->gate.hw; |
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gate_ops->disable(gate_hw); |
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} |
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static void clk_sdmmc_mux_disable_unused(struct clk_hw *hw) |
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{ |
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struct tegra_sdmmc_mux *sdmmc_mux = to_clk_sdmmc_mux(hw); |
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const struct clk_ops *gate_ops = sdmmc_mux->gate_ops; |
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struct clk_hw *gate_hw = &sdmmc_mux->gate.hw; |
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gate_ops->disable_unused(gate_hw); |
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} |
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static void clk_sdmmc_mux_restore_context(struct clk_hw *hw) |
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{ |
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struct clk_hw *parent = clk_hw_get_parent(hw); |
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unsigned long parent_rate = clk_hw_get_rate(parent); |
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unsigned long rate = clk_hw_get_rate(hw); |
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int parent_id; |
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parent_id = clk_hw_get_parent_index(hw); |
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if (WARN_ON(parent_id < 0)) |
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return; |
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clk_sdmmc_mux_set_parent(hw, parent_id); |
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clk_sdmmc_mux_set_rate(hw, rate, parent_rate); |
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} |
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static const struct clk_ops tegra_clk_sdmmc_mux_ops = { |
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.get_parent = clk_sdmmc_mux_get_parent, |
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.set_parent = clk_sdmmc_mux_set_parent, |
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.determine_rate = clk_sdmmc_mux_determine_rate, |
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.recalc_rate = clk_sdmmc_mux_recalc_rate, |
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.set_rate = clk_sdmmc_mux_set_rate, |
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.is_enabled = clk_sdmmc_mux_is_enabled, |
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.enable = clk_sdmmc_mux_enable, |
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.disable = clk_sdmmc_mux_disable, |
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.disable_unused = clk_sdmmc_mux_disable_unused, |
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.restore_context = clk_sdmmc_mux_restore_context, |
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}; |
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struct clk *tegra_clk_register_sdmmc_mux_div(const char *name, |
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void __iomem *clk_base, u32 offset, u32 clk_num, u8 div_flags, |
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unsigned long flags, void *lock) |
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{ |
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struct clk *clk; |
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struct clk_init_data init; |
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const struct tegra_clk_periph_regs *bank; |
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struct tegra_sdmmc_mux *sdmmc_mux; |
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init.ops = &tegra_clk_sdmmc_mux_ops; |
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init.name = name; |
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init.flags = flags; |
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init.parent_names = mux_sdmmc_parents; |
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init.num_parents = ARRAY_SIZE(mux_sdmmc_parents); |
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bank = get_reg_bank(clk_num); |
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if (!bank) |
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return ERR_PTR(-EINVAL); |
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sdmmc_mux = kzalloc(sizeof(*sdmmc_mux), GFP_KERNEL); |
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if (!sdmmc_mux) |
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return ERR_PTR(-ENOMEM); |
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/* Data in .init is copied by clk_register(), so stack variable OK */ |
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sdmmc_mux->hw.init = &init; |
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sdmmc_mux->reg = clk_base + offset; |
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sdmmc_mux->lock = lock; |
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sdmmc_mux->gate.clk_base = clk_base; |
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sdmmc_mux->gate.regs = bank; |
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sdmmc_mux->gate.enable_refcnt = periph_clk_enb_refcnt; |
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sdmmc_mux->gate.clk_num = clk_num; |
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sdmmc_mux->gate.flags = TEGRA_PERIPH_ON_APB; |
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sdmmc_mux->div_flags = div_flags; |
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sdmmc_mux->gate_ops = &tegra_clk_periph_gate_ops; |
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clk = clk_register(NULL, &sdmmc_mux->hw); |
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if (IS_ERR(clk)) { |
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kfree(sdmmc_mux); |
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return clk; |
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} |
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sdmmc_mux->gate.hw.clk = clk; |
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return clk; |
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}
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