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161 lines
4.5 KiB
161 lines
4.5 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* Copyright (c) 2017 MediaTek Inc. |
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* Author: Chen Zhong <[email protected]> |
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* Sean Wang <[email protected]> |
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*/ |
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#include <linux/clk-provider.h> |
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#include <linux/of.h> |
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#include <linux/of_address.h> |
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#include <linux/of_device.h> |
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#include <linux/platform_device.h> |
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#include "clk-mtk.h" |
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#include "clk-gate.h" |
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#include <dt-bindings/clock/mt7622-clk.h> |
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#define GATE_PCIE(_id, _name, _parent, _shift) { \ |
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.id = _id, \ |
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.name = _name, \ |
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.parent_name = _parent, \ |
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.regs = &pcie_cg_regs, \ |
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.shift = _shift, \ |
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.ops = &mtk_clk_gate_ops_no_setclr_inv, \ |
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} |
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#define GATE_SSUSB(_id, _name, _parent, _shift) { \ |
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.id = _id, \ |
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.name = _name, \ |
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.parent_name = _parent, \ |
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.regs = &ssusb_cg_regs, \ |
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.shift = _shift, \ |
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.ops = &mtk_clk_gate_ops_no_setclr_inv, \ |
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} |
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static const struct mtk_gate_regs pcie_cg_regs = { |
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.set_ofs = 0x30, |
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.clr_ofs = 0x30, |
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.sta_ofs = 0x30, |
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}; |
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static const struct mtk_gate_regs ssusb_cg_regs = { |
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.set_ofs = 0x30, |
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.clr_ofs = 0x30, |
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.sta_ofs = 0x30, |
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}; |
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static const struct mtk_gate ssusb_clks[] = { |
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GATE_SSUSB(CLK_SSUSB_U2_PHY_1P_EN, "ssusb_u2_phy_1p", |
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"to_u2_phy_1p", 0), |
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GATE_SSUSB(CLK_SSUSB_U2_PHY_EN, "ssusb_u2_phy_en", "to_u2_phy", 1), |
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GATE_SSUSB(CLK_SSUSB_REF_EN, "ssusb_ref_en", "to_usb3_ref", 5), |
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GATE_SSUSB(CLK_SSUSB_SYS_EN, "ssusb_sys_en", "to_usb3_sys", 6), |
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GATE_SSUSB(CLK_SSUSB_MCU_EN, "ssusb_mcu_en", "axi_sel", 7), |
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GATE_SSUSB(CLK_SSUSB_DMA_EN, "ssusb_dma_en", "hif_sel", 8), |
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}; |
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static const struct mtk_gate pcie_clks[] = { |
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GATE_PCIE(CLK_PCIE_P1_AUX_EN, "pcie_p1_aux_en", "p1_1mhz", 12), |
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GATE_PCIE(CLK_PCIE_P1_OBFF_EN, "pcie_p1_obff_en", "free_run_4mhz", 13), |
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GATE_PCIE(CLK_PCIE_P1_AHB_EN, "pcie_p1_ahb_en", "axi_sel", 14), |
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GATE_PCIE(CLK_PCIE_P1_AXI_EN, "pcie_p1_axi_en", "hif_sel", 15), |
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GATE_PCIE(CLK_PCIE_P1_MAC_EN, "pcie_p1_mac_en", "pcie1_mac_en", 16), |
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GATE_PCIE(CLK_PCIE_P1_PIPE_EN, "pcie_p1_pipe_en", "pcie1_pipe_en", 17), |
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GATE_PCIE(CLK_PCIE_P0_AUX_EN, "pcie_p0_aux_en", "p0_1mhz", 18), |
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GATE_PCIE(CLK_PCIE_P0_OBFF_EN, "pcie_p0_obff_en", "free_run_4mhz", 19), |
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GATE_PCIE(CLK_PCIE_P0_AHB_EN, "pcie_p0_ahb_en", "axi_sel", 20), |
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GATE_PCIE(CLK_PCIE_P0_AXI_EN, "pcie_p0_axi_en", "hif_sel", 21), |
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GATE_PCIE(CLK_PCIE_P0_MAC_EN, "pcie_p0_mac_en", "pcie0_mac_en", 22), |
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GATE_PCIE(CLK_PCIE_P0_PIPE_EN, "pcie_p0_pipe_en", "pcie0_pipe_en", 23), |
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GATE_PCIE(CLK_SATA_AHB_EN, "sata_ahb_en", "axi_sel", 26), |
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GATE_PCIE(CLK_SATA_AXI_EN, "sata_axi_en", "hif_sel", 27), |
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GATE_PCIE(CLK_SATA_ASIC_EN, "sata_asic_en", "sata_asic", 28), |
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GATE_PCIE(CLK_SATA_RBC_EN, "sata_rbc_en", "sata_rbc", 29), |
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GATE_PCIE(CLK_SATA_PM_EN, "sata_pm_en", "univpll2_d4", 30), |
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}; |
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static int clk_mt7622_ssusbsys_init(struct platform_device *pdev) |
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{ |
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struct clk_onecell_data *clk_data; |
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struct device_node *node = pdev->dev.of_node; |
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int r; |
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clk_data = mtk_alloc_clk_data(CLK_SSUSB_NR_CLK); |
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mtk_clk_register_gates(node, ssusb_clks, ARRAY_SIZE(ssusb_clks), |
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clk_data); |
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r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); |
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if (r) |
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dev_err(&pdev->dev, |
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"could not register clock provider: %s: %d\n", |
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pdev->name, r); |
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mtk_register_reset_controller(node, 1, 0x34); |
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return r; |
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} |
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static int clk_mt7622_pciesys_init(struct platform_device *pdev) |
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{ |
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struct clk_onecell_data *clk_data; |
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struct device_node *node = pdev->dev.of_node; |
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int r; |
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clk_data = mtk_alloc_clk_data(CLK_PCIE_NR_CLK); |
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mtk_clk_register_gates(node, pcie_clks, ARRAY_SIZE(pcie_clks), |
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clk_data); |
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r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); |
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if (r) |
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dev_err(&pdev->dev, |
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"could not register clock provider: %s: %d\n", |
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pdev->name, r); |
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mtk_register_reset_controller(node, 1, 0x34); |
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return r; |
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} |
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static const struct of_device_id of_match_clk_mt7622_hif[] = { |
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{ |
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.compatible = "mediatek,mt7622-pciesys", |
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.data = clk_mt7622_pciesys_init, |
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}, { |
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.compatible = "mediatek,mt7622-ssusbsys", |
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.data = clk_mt7622_ssusbsys_init, |
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}, { |
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/* sentinel */ |
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} |
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}; |
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static int clk_mt7622_hif_probe(struct platform_device *pdev) |
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{ |
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int (*clk_init)(struct platform_device *); |
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int r; |
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clk_init = of_device_get_match_data(&pdev->dev); |
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if (!clk_init) |
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return -EINVAL; |
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r = clk_init(pdev); |
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if (r) |
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dev_err(&pdev->dev, |
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"could not register clock provider: %s: %d\n", |
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pdev->name, r); |
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return r; |
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} |
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static struct platform_driver clk_mt7622_hif_drv = { |
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.probe = clk_mt7622_hif_probe, |
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.driver = { |
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.name = "clk-mt7622-hif", |
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.of_match_table = of_match_clk_mt7622_hif, |
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}, |
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}; |
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builtin_platform_driver(clk_mt7622_hif_drv);
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