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746 lines
19 KiB
746 lines
19 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* clk-xgene.c - AppliedMicro X-Gene Clock Interface |
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* |
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* Copyright (c) 2013, Applied Micro Circuits Corporation |
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* Author: Loc Ho <[email protected]> |
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*/ |
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#include <linux/module.h> |
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#include <linux/spinlock.h> |
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#include <linux/io.h> |
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#include <linux/of.h> |
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#include <linux/clkdev.h> |
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#include <linux/clk-provider.h> |
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#include <linux/of_address.h> |
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|
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/* Register SCU_PCPPLL bit fields */ |
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#define N_DIV_RD(src) ((src) & 0x000001ff) |
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#define SC_N_DIV_RD(src) ((src) & 0x0000007f) |
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#define SC_OUTDIV2(src) (((src) & 0x00000100) >> 8) |
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|
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/* Register SCU_SOCPLL bit fields */ |
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#define CLKR_RD(src) (((src) & 0x07000000)>>24) |
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#define CLKOD_RD(src) (((src) & 0x00300000)>>20) |
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#define REGSPEC_RESET_F1_MASK 0x00010000 |
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#define CLKF_RD(src) (((src) & 0x000001ff)) |
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|
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#define XGENE_CLK_DRIVER_VER "0.1" |
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|
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static DEFINE_SPINLOCK(clk_lock); |
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|
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static inline u32 xgene_clk_read(void __iomem *csr) |
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{ |
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return readl_relaxed(csr); |
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} |
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|
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static inline void xgene_clk_write(u32 data, void __iomem *csr) |
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{ |
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writel_relaxed(data, csr); |
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} |
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|
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/* PLL Clock */ |
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enum xgene_pll_type { |
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PLL_TYPE_PCP = 0, |
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PLL_TYPE_SOC = 1, |
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}; |
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|
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struct xgene_clk_pll { |
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struct clk_hw hw; |
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void __iomem *reg; |
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spinlock_t *lock; |
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u32 pll_offset; |
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enum xgene_pll_type type; |
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int version; |
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}; |
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|
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#define to_xgene_clk_pll(_hw) container_of(_hw, struct xgene_clk_pll, hw) |
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|
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static int xgene_clk_pll_is_enabled(struct clk_hw *hw) |
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{ |
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struct xgene_clk_pll *pllclk = to_xgene_clk_pll(hw); |
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u32 data; |
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data = xgene_clk_read(pllclk->reg + pllclk->pll_offset); |
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pr_debug("%s pll %s\n", clk_hw_get_name(hw), |
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data & REGSPEC_RESET_F1_MASK ? "disabled" : "enabled"); |
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|
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return data & REGSPEC_RESET_F1_MASK ? 0 : 1; |
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} |
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|
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static unsigned long xgene_clk_pll_recalc_rate(struct clk_hw *hw, |
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unsigned long parent_rate) |
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{ |
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struct xgene_clk_pll *pllclk = to_xgene_clk_pll(hw); |
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unsigned long fref; |
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unsigned long fvco; |
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u32 pll; |
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u32 nref; |
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u32 nout; |
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u32 nfb; |
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pll = xgene_clk_read(pllclk->reg + pllclk->pll_offset); |
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|
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if (pllclk->version <= 1) { |
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if (pllclk->type == PLL_TYPE_PCP) { |
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/* |
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* PLL VCO = Reference clock * NF |
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* PCP PLL = PLL_VCO / 2 |
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*/ |
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nout = 2; |
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fvco = parent_rate * (N_DIV_RD(pll) + 4); |
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} else { |
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/* |
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* Fref = Reference Clock / NREF; |
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* Fvco = Fref * NFB; |
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* Fout = Fvco / NOUT; |
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*/ |
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nref = CLKR_RD(pll) + 1; |
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nout = CLKOD_RD(pll) + 1; |
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nfb = CLKF_RD(pll); |
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fref = parent_rate / nref; |
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fvco = fref * nfb; |
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} |
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} else { |
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/* |
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* fvco = Reference clock * FBDIVC |
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* PLL freq = fvco / NOUT |
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*/ |
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nout = SC_OUTDIV2(pll) ? 2 : 3; |
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fvco = parent_rate * SC_N_DIV_RD(pll); |
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} |
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pr_debug("%s pll recalc rate %ld parent %ld version %d\n", |
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clk_hw_get_name(hw), fvco / nout, parent_rate, |
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pllclk->version); |
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|
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return fvco / nout; |
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} |
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|
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static const struct clk_ops xgene_clk_pll_ops = { |
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.is_enabled = xgene_clk_pll_is_enabled, |
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.recalc_rate = xgene_clk_pll_recalc_rate, |
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}; |
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|
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static struct clk *xgene_register_clk_pll(struct device *dev, |
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const char *name, const char *parent_name, |
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unsigned long flags, void __iomem *reg, u32 pll_offset, |
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u32 type, spinlock_t *lock, int version) |
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{ |
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struct xgene_clk_pll *apmclk; |
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struct clk *clk; |
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struct clk_init_data init; |
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|
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/* allocate the APM clock structure */ |
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apmclk = kzalloc(sizeof(*apmclk), GFP_KERNEL); |
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if (!apmclk) |
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return ERR_PTR(-ENOMEM); |
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|
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init.name = name; |
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init.ops = &xgene_clk_pll_ops; |
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init.flags = flags; |
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init.parent_names = parent_name ? &parent_name : NULL; |
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init.num_parents = parent_name ? 1 : 0; |
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|
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apmclk->version = version; |
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apmclk->reg = reg; |
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apmclk->lock = lock; |
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apmclk->pll_offset = pll_offset; |
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apmclk->type = type; |
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apmclk->hw.init = &init; |
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|
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/* Register the clock */ |
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clk = clk_register(dev, &apmclk->hw); |
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if (IS_ERR(clk)) { |
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pr_err("%s: could not register clk %s\n", __func__, name); |
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kfree(apmclk); |
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return NULL; |
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} |
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return clk; |
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} |
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|
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static int xgene_pllclk_version(struct device_node *np) |
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{ |
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if (of_device_is_compatible(np, "apm,xgene-socpll-clock")) |
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return 1; |
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if (of_device_is_compatible(np, "apm,xgene-pcppll-clock")) |
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return 1; |
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return 2; |
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} |
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|
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static void xgene_pllclk_init(struct device_node *np, enum xgene_pll_type pll_type) |
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{ |
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const char *clk_name = np->full_name; |
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struct clk *clk; |
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void __iomem *reg; |
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int version = xgene_pllclk_version(np); |
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|
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reg = of_iomap(np, 0); |
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if (!reg) { |
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pr_err("Unable to map CSR register for %pOF\n", np); |
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return; |
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} |
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of_property_read_string(np, "clock-output-names", &clk_name); |
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clk = xgene_register_clk_pll(NULL, |
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clk_name, of_clk_get_parent_name(np, 0), |
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0, reg, 0, pll_type, &clk_lock, |
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version); |
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if (!IS_ERR(clk)) { |
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of_clk_add_provider(np, of_clk_src_simple_get, clk); |
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clk_register_clkdev(clk, clk_name, NULL); |
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pr_debug("Add %s clock PLL\n", clk_name); |
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} |
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} |
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|
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static void xgene_socpllclk_init(struct device_node *np) |
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{ |
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xgene_pllclk_init(np, PLL_TYPE_SOC); |
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} |
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static void xgene_pcppllclk_init(struct device_node *np) |
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{ |
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xgene_pllclk_init(np, PLL_TYPE_PCP); |
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} |
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|
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/** |
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* struct xgene_clk_pmd - PMD clock |
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* |
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* @hw: handle between common and hardware-specific interfaces |
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* @reg: register containing the fractional scale multiplier (scaler) |
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* @shift: shift to the unit bit field |
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* @mask: mask to the unit bit field |
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* @denom: 1/denominator unit |
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* @lock: register lock |
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* @flags: XGENE_CLK_PMD_SCALE_INVERTED - By default the scaler is the value read |
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* from the register plus one. For example, |
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* 0 for (0 + 1) / denom, |
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* 1 for (1 + 1) / denom and etc. |
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* If this flag is set, it is |
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* 0 for (denom - 0) / denom, |
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* 1 for (denom - 1) / denom and etc. |
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*/ |
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struct xgene_clk_pmd { |
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struct clk_hw hw; |
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void __iomem *reg; |
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u8 shift; |
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u32 mask; |
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u64 denom; |
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u32 flags; |
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spinlock_t *lock; |
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}; |
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|
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#define to_xgene_clk_pmd(_hw) container_of(_hw, struct xgene_clk_pmd, hw) |
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|
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#define XGENE_CLK_PMD_SCALE_INVERTED BIT(0) |
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#define XGENE_CLK_PMD_SHIFT 8 |
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#define XGENE_CLK_PMD_WIDTH 3 |
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|
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static unsigned long xgene_clk_pmd_recalc_rate(struct clk_hw *hw, |
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unsigned long parent_rate) |
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{ |
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struct xgene_clk_pmd *fd = to_xgene_clk_pmd(hw); |
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unsigned long flags = 0; |
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u64 ret, scale; |
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u32 val; |
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|
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if (fd->lock) |
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spin_lock_irqsave(fd->lock, flags); |
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else |
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__acquire(fd->lock); |
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val = readl(fd->reg); |
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|
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if (fd->lock) |
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spin_unlock_irqrestore(fd->lock, flags); |
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else |
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__release(fd->lock); |
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ret = (u64)parent_rate; |
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scale = (val & fd->mask) >> fd->shift; |
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if (fd->flags & XGENE_CLK_PMD_SCALE_INVERTED) |
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scale = fd->denom - scale; |
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else |
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scale++; |
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|
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/* freq = parent_rate * scaler / denom */ |
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do_div(ret, fd->denom); |
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ret *= scale; |
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if (ret == 0) |
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ret = (u64)parent_rate; |
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|
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return ret; |
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} |
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static long xgene_clk_pmd_round_rate(struct clk_hw *hw, unsigned long rate, |
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unsigned long *parent_rate) |
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{ |
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struct xgene_clk_pmd *fd = to_xgene_clk_pmd(hw); |
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u64 ret, scale; |
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|
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if (!rate || rate >= *parent_rate) |
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return *parent_rate; |
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|
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/* freq = parent_rate * scaler / denom */ |
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ret = rate * fd->denom; |
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scale = DIV_ROUND_UP_ULL(ret, *parent_rate); |
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ret = (u64)*parent_rate * scale; |
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do_div(ret, fd->denom); |
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|
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return ret; |
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} |
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static int xgene_clk_pmd_set_rate(struct clk_hw *hw, unsigned long rate, |
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unsigned long parent_rate) |
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{ |
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struct xgene_clk_pmd *fd = to_xgene_clk_pmd(hw); |
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unsigned long flags = 0; |
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u64 scale, ret; |
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u32 val; |
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/* |
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* Compute the scaler: |
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* |
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* freq = parent_rate * scaler / denom, or |
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* scaler = freq * denom / parent_rate |
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*/ |
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ret = rate * fd->denom; |
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scale = DIV_ROUND_UP_ULL(ret, (u64)parent_rate); |
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|
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/* Check if inverted */ |
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if (fd->flags & XGENE_CLK_PMD_SCALE_INVERTED) |
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scale = fd->denom - scale; |
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else |
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scale--; |
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if (fd->lock) |
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spin_lock_irqsave(fd->lock, flags); |
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else |
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__acquire(fd->lock); |
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val = readl(fd->reg); |
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val &= ~fd->mask; |
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val |= (scale << fd->shift); |
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writel(val, fd->reg); |
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if (fd->lock) |
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spin_unlock_irqrestore(fd->lock, flags); |
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else |
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__release(fd->lock); |
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return 0; |
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} |
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static const struct clk_ops xgene_clk_pmd_ops = { |
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.recalc_rate = xgene_clk_pmd_recalc_rate, |
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.round_rate = xgene_clk_pmd_round_rate, |
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.set_rate = xgene_clk_pmd_set_rate, |
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}; |
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static struct clk * |
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xgene_register_clk_pmd(struct device *dev, |
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const char *name, const char *parent_name, |
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unsigned long flags, void __iomem *reg, u8 shift, |
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u8 width, u64 denom, u32 clk_flags, spinlock_t *lock) |
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{ |
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struct xgene_clk_pmd *fd; |
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struct clk_init_data init; |
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struct clk *clk; |
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fd = kzalloc(sizeof(*fd), GFP_KERNEL); |
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if (!fd) |
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return ERR_PTR(-ENOMEM); |
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init.name = name; |
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init.ops = &xgene_clk_pmd_ops; |
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init.flags = flags; |
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init.parent_names = parent_name ? &parent_name : NULL; |
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init.num_parents = parent_name ? 1 : 0; |
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|
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fd->reg = reg; |
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fd->shift = shift; |
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fd->mask = (BIT(width) - 1) << shift; |
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fd->denom = denom; |
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fd->flags = clk_flags; |
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fd->lock = lock; |
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fd->hw.init = &init; |
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clk = clk_register(dev, &fd->hw); |
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if (IS_ERR(clk)) { |
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pr_err("%s: could not register clk %s\n", __func__, name); |
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kfree(fd); |
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return NULL; |
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} |
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return clk; |
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} |
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static void xgene_pmdclk_init(struct device_node *np) |
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{ |
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const char *clk_name = np->full_name; |
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void __iomem *csr_reg; |
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struct resource res; |
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struct clk *clk; |
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u64 denom; |
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u32 flags = 0; |
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int rc; |
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|
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/* Check if the entry is disabled */ |
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if (!of_device_is_available(np)) |
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return; |
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|
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/* Parse the DTS register for resource */ |
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rc = of_address_to_resource(np, 0, &res); |
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if (rc != 0) { |
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pr_err("no DTS register for %pOF\n", np); |
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return; |
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} |
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csr_reg = of_iomap(np, 0); |
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if (!csr_reg) { |
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pr_err("Unable to map resource for %pOF\n", np); |
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return; |
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} |
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of_property_read_string(np, "clock-output-names", &clk_name); |
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|
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denom = BIT(XGENE_CLK_PMD_WIDTH); |
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flags |= XGENE_CLK_PMD_SCALE_INVERTED; |
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|
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clk = xgene_register_clk_pmd(NULL, clk_name, |
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of_clk_get_parent_name(np, 0), 0, |
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csr_reg, XGENE_CLK_PMD_SHIFT, |
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XGENE_CLK_PMD_WIDTH, denom, |
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flags, &clk_lock); |
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if (!IS_ERR(clk)) { |
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of_clk_add_provider(np, of_clk_src_simple_get, clk); |
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clk_register_clkdev(clk, clk_name, NULL); |
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pr_debug("Add %s clock\n", clk_name); |
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} else { |
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if (csr_reg) |
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iounmap(csr_reg); |
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} |
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} |
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|
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/* IP Clock */ |
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struct xgene_dev_parameters { |
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void __iomem *csr_reg; /* CSR for IP clock */ |
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u32 reg_clk_offset; /* Offset to clock enable CSR */ |
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u32 reg_clk_mask; /* Mask bit for clock enable */ |
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u32 reg_csr_offset; /* Offset to CSR reset */ |
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u32 reg_csr_mask; /* Mask bit for disable CSR reset */ |
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void __iomem *divider_reg; /* CSR for divider */ |
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u32 reg_divider_offset; /* Offset to divider register */ |
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u32 reg_divider_shift; /* Bit shift to divider field */ |
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u32 reg_divider_width; /* Width of the bit to divider field */ |
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}; |
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|
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struct xgene_clk { |
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struct clk_hw hw; |
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spinlock_t *lock; |
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struct xgene_dev_parameters param; |
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}; |
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|
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#define to_xgene_clk(_hw) container_of(_hw, struct xgene_clk, hw) |
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|
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static int xgene_clk_enable(struct clk_hw *hw) |
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{ |
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struct xgene_clk *pclk = to_xgene_clk(hw); |
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unsigned long flags = 0; |
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u32 data; |
|
|
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if (pclk->lock) |
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spin_lock_irqsave(pclk->lock, flags); |
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|
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if (pclk->param.csr_reg) { |
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pr_debug("%s clock enabled\n", clk_hw_get_name(hw)); |
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/* First enable the clock */ |
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data = xgene_clk_read(pclk->param.csr_reg + |
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pclk->param.reg_clk_offset); |
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data |= pclk->param.reg_clk_mask; |
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xgene_clk_write(data, pclk->param.csr_reg + |
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pclk->param.reg_clk_offset); |
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pr_debug("%s clk offset 0x%08X mask 0x%08X value 0x%08X\n", |
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clk_hw_get_name(hw), |
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pclk->param.reg_clk_offset, pclk->param.reg_clk_mask, |
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data); |
|
|
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/* Second enable the CSR */ |
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data = xgene_clk_read(pclk->param.csr_reg + |
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pclk->param.reg_csr_offset); |
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data &= ~pclk->param.reg_csr_mask; |
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xgene_clk_write(data, pclk->param.csr_reg + |
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pclk->param.reg_csr_offset); |
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pr_debug("%s csr offset 0x%08X mask 0x%08X value 0x%08X\n", |
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clk_hw_get_name(hw), |
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pclk->param.reg_csr_offset, pclk->param.reg_csr_mask, |
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data); |
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} |
|
|
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if (pclk->lock) |
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spin_unlock_irqrestore(pclk->lock, flags); |
|
|
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return 0; |
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} |
|
|
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static void xgene_clk_disable(struct clk_hw *hw) |
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{ |
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struct xgene_clk *pclk = to_xgene_clk(hw); |
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unsigned long flags = 0; |
|
u32 data; |
|
|
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if (pclk->lock) |
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spin_lock_irqsave(pclk->lock, flags); |
|
|
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if (pclk->param.csr_reg) { |
|
pr_debug("%s clock disabled\n", clk_hw_get_name(hw)); |
|
/* First put the CSR in reset */ |
|
data = xgene_clk_read(pclk->param.csr_reg + |
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pclk->param.reg_csr_offset); |
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data |= pclk->param.reg_csr_mask; |
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xgene_clk_write(data, pclk->param.csr_reg + |
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pclk->param.reg_csr_offset); |
|
|
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/* Second disable the clock */ |
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data = xgene_clk_read(pclk->param.csr_reg + |
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pclk->param.reg_clk_offset); |
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data &= ~pclk->param.reg_clk_mask; |
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xgene_clk_write(data, pclk->param.csr_reg + |
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pclk->param.reg_clk_offset); |
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} |
|
|
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if (pclk->lock) |
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spin_unlock_irqrestore(pclk->lock, flags); |
|
} |
|
|
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static int xgene_clk_is_enabled(struct clk_hw *hw) |
|
{ |
|
struct xgene_clk *pclk = to_xgene_clk(hw); |
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u32 data = 0; |
|
|
|
if (pclk->param.csr_reg) { |
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pr_debug("%s clock checking\n", clk_hw_get_name(hw)); |
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data = xgene_clk_read(pclk->param.csr_reg + |
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pclk->param.reg_clk_offset); |
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pr_debug("%s clock is %s\n", clk_hw_get_name(hw), |
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data & pclk->param.reg_clk_mask ? "enabled" : |
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"disabled"); |
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} |
|
|
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if (!pclk->param.csr_reg) |
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return 1; |
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return data & pclk->param.reg_clk_mask ? 1 : 0; |
|
} |
|
|
|
static unsigned long xgene_clk_recalc_rate(struct clk_hw *hw, |
|
unsigned long parent_rate) |
|
{ |
|
struct xgene_clk *pclk = to_xgene_clk(hw); |
|
u32 data; |
|
|
|
if (pclk->param.divider_reg) { |
|
data = xgene_clk_read(pclk->param.divider_reg + |
|
pclk->param.reg_divider_offset); |
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data >>= pclk->param.reg_divider_shift; |
|
data &= (1 << pclk->param.reg_divider_width) - 1; |
|
|
|
pr_debug("%s clock recalc rate %ld parent %ld\n", |
|
clk_hw_get_name(hw), |
|
parent_rate / data, parent_rate); |
|
|
|
return parent_rate / data; |
|
} else { |
|
pr_debug("%s clock recalc rate %ld parent %ld\n", |
|
clk_hw_get_name(hw), parent_rate, parent_rate); |
|
return parent_rate; |
|
} |
|
} |
|
|
|
static int xgene_clk_set_rate(struct clk_hw *hw, unsigned long rate, |
|
unsigned long parent_rate) |
|
{ |
|
struct xgene_clk *pclk = to_xgene_clk(hw); |
|
unsigned long flags = 0; |
|
u32 data; |
|
u32 divider; |
|
u32 divider_save; |
|
|
|
if (pclk->lock) |
|
spin_lock_irqsave(pclk->lock, flags); |
|
|
|
if (pclk->param.divider_reg) { |
|
/* Let's compute the divider */ |
|
if (rate > parent_rate) |
|
rate = parent_rate; |
|
divider_save = divider = parent_rate / rate; /* Rounded down */ |
|
divider &= (1 << pclk->param.reg_divider_width) - 1; |
|
divider <<= pclk->param.reg_divider_shift; |
|
|
|
/* Set new divider */ |
|
data = xgene_clk_read(pclk->param.divider_reg + |
|
pclk->param.reg_divider_offset); |
|
data &= ~(((1 << pclk->param.reg_divider_width) - 1) |
|
<< pclk->param.reg_divider_shift); |
|
data |= divider; |
|
xgene_clk_write(data, pclk->param.divider_reg + |
|
pclk->param.reg_divider_offset); |
|
pr_debug("%s clock set rate %ld\n", clk_hw_get_name(hw), |
|
parent_rate / divider_save); |
|
} else { |
|
divider_save = 1; |
|
} |
|
|
|
if (pclk->lock) |
|
spin_unlock_irqrestore(pclk->lock, flags); |
|
|
|
return parent_rate / divider_save; |
|
} |
|
|
|
static long xgene_clk_round_rate(struct clk_hw *hw, unsigned long rate, |
|
unsigned long *prate) |
|
{ |
|
struct xgene_clk *pclk = to_xgene_clk(hw); |
|
unsigned long parent_rate = *prate; |
|
u32 divider; |
|
|
|
if (pclk->param.divider_reg) { |
|
/* Let's compute the divider */ |
|
if (rate > parent_rate) |
|
rate = parent_rate; |
|
divider = parent_rate / rate; /* Rounded down */ |
|
} else { |
|
divider = 1; |
|
} |
|
|
|
return parent_rate / divider; |
|
} |
|
|
|
static const struct clk_ops xgene_clk_ops = { |
|
.enable = xgene_clk_enable, |
|
.disable = xgene_clk_disable, |
|
.is_enabled = xgene_clk_is_enabled, |
|
.recalc_rate = xgene_clk_recalc_rate, |
|
.set_rate = xgene_clk_set_rate, |
|
.round_rate = xgene_clk_round_rate, |
|
}; |
|
|
|
static struct clk *xgene_register_clk(struct device *dev, |
|
const char *name, const char *parent_name, |
|
struct xgene_dev_parameters *parameters, spinlock_t *lock) |
|
{ |
|
struct xgene_clk *apmclk; |
|
struct clk *clk; |
|
struct clk_init_data init; |
|
int rc; |
|
|
|
/* allocate the APM clock structure */ |
|
apmclk = kzalloc(sizeof(*apmclk), GFP_KERNEL); |
|
if (!apmclk) |
|
return ERR_PTR(-ENOMEM); |
|
|
|
init.name = name; |
|
init.ops = &xgene_clk_ops; |
|
init.flags = 0; |
|
init.parent_names = parent_name ? &parent_name : NULL; |
|
init.num_parents = parent_name ? 1 : 0; |
|
|
|
apmclk->lock = lock; |
|
apmclk->hw.init = &init; |
|
apmclk->param = *parameters; |
|
|
|
/* Register the clock */ |
|
clk = clk_register(dev, &apmclk->hw); |
|
if (IS_ERR(clk)) { |
|
pr_err("%s: could not register clk %s\n", __func__, name); |
|
kfree(apmclk); |
|
return clk; |
|
} |
|
|
|
/* Register the clock for lookup */ |
|
rc = clk_register_clkdev(clk, name, NULL); |
|
if (rc != 0) { |
|
pr_err("%s: could not register lookup clk %s\n", |
|
__func__, name); |
|
} |
|
return clk; |
|
} |
|
|
|
static void __init xgene_devclk_init(struct device_node *np) |
|
{ |
|
const char *clk_name = np->full_name; |
|
struct clk *clk; |
|
struct resource res; |
|
int rc; |
|
struct xgene_dev_parameters parameters; |
|
int i; |
|
|
|
/* Check if the entry is disabled */ |
|
if (!of_device_is_available(np)) |
|
return; |
|
|
|
/* Parse the DTS register for resource */ |
|
parameters.csr_reg = NULL; |
|
parameters.divider_reg = NULL; |
|
for (i = 0; i < 2; i++) { |
|
void __iomem *map_res; |
|
rc = of_address_to_resource(np, i, &res); |
|
if (rc != 0) { |
|
if (i == 0) { |
|
pr_err("no DTS register for %pOF\n", np); |
|
return; |
|
} |
|
break; |
|
} |
|
map_res = of_iomap(np, i); |
|
if (!map_res) { |
|
pr_err("Unable to map resource %d for %pOF\n", i, np); |
|
goto err; |
|
} |
|
if (strcmp(res.name, "div-reg") == 0) |
|
parameters.divider_reg = map_res; |
|
else /* if (strcmp(res->name, "csr-reg") == 0) */ |
|
parameters.csr_reg = map_res; |
|
} |
|
if (of_property_read_u32(np, "csr-offset", ¶meters.reg_csr_offset)) |
|
parameters.reg_csr_offset = 0; |
|
if (of_property_read_u32(np, "csr-mask", ¶meters.reg_csr_mask)) |
|
parameters.reg_csr_mask = 0xF; |
|
if (of_property_read_u32(np, "enable-offset", |
|
¶meters.reg_clk_offset)) |
|
parameters.reg_clk_offset = 0x8; |
|
if (of_property_read_u32(np, "enable-mask", ¶meters.reg_clk_mask)) |
|
parameters.reg_clk_mask = 0xF; |
|
if (of_property_read_u32(np, "divider-offset", |
|
¶meters.reg_divider_offset)) |
|
parameters.reg_divider_offset = 0; |
|
if (of_property_read_u32(np, "divider-width", |
|
¶meters.reg_divider_width)) |
|
parameters.reg_divider_width = 0; |
|
if (of_property_read_u32(np, "divider-shift", |
|
¶meters.reg_divider_shift)) |
|
parameters.reg_divider_shift = 0; |
|
of_property_read_string(np, "clock-output-names", &clk_name); |
|
|
|
clk = xgene_register_clk(NULL, clk_name, |
|
of_clk_get_parent_name(np, 0), ¶meters, &clk_lock); |
|
if (IS_ERR(clk)) |
|
goto err; |
|
pr_debug("Add %s clock\n", clk_name); |
|
rc = of_clk_add_provider(np, of_clk_src_simple_get, clk); |
|
if (rc != 0) |
|
pr_err("%s: could register provider clk %pOF\n", __func__, np); |
|
|
|
return; |
|
|
|
err: |
|
if (parameters.csr_reg) |
|
iounmap(parameters.csr_reg); |
|
if (parameters.divider_reg) |
|
iounmap(parameters.divider_reg); |
|
} |
|
|
|
CLK_OF_DECLARE(xgene_socpll_clock, "apm,xgene-socpll-clock", xgene_socpllclk_init); |
|
CLK_OF_DECLARE(xgene_pcppll_clock, "apm,xgene-pcppll-clock", xgene_pcppllclk_init); |
|
CLK_OF_DECLARE(xgene_pmd_clock, "apm,xgene-pmd-clock", xgene_pmdclk_init); |
|
CLK_OF_DECLARE(xgene_socpll_v2_clock, "apm,xgene-socpll-v2-clock", |
|
xgene_socpllclk_init); |
|
CLK_OF_DECLARE(xgene_pcppll_v2_clock, "apm,xgene-pcppll-v2-clock", |
|
xgene_pcppllclk_init); |
|
CLK_OF_DECLARE(xgene_dev_clock, "apm,xgene-device-clock", xgene_devclk_init);
|
|
|