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382 lines
10 KiB
382 lines
10 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* Copyright (c) 2014 Marvell Technology Group Ltd. |
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* |
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* Sebastian Hesselbarth <[email protected]> |
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* Alexandre Belloni <[email protected]> |
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*/ |
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#include <linux/clk-provider.h> |
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#include <linux/io.h> |
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#include <linux/kernel.h> |
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#include <linux/of.h> |
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#include <linux/of_address.h> |
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#include <linux/slab.h> |
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#include "berlin2-avpll.h" |
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/* |
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* Berlin2 SoCs comprise up to two PLLs called AVPLL built upon a |
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* VCO with 8 channels each, channel 8 is the odd-one-out and does |
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* not provide mul/div. |
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* |
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* Unfortunately, its registers are not named but just numbered. To |
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* get in at least some kind of structure, we split each AVPLL into |
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* the VCOs and each channel into separate clock drivers. |
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* |
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* Also, here and there the VCO registers are a bit different with |
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* respect to bit shifts. Make sure to add a comment for those. |
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*/ |
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#define NUM_CHANNELS 8 |
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#define AVPLL_CTRL(x) ((x) * 0x4) |
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#define VCO_CTRL0 AVPLL_CTRL(0) |
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/* BG2/BG2CDs VCO_B has an additional shift of 4 for its VCO_CTRL0 reg */ |
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#define VCO_RESET BIT(0) |
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#define VCO_POWERUP BIT(1) |
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#define VCO_INTERPOL_SHIFT 2 |
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#define VCO_INTERPOL_MASK (0xf << VCO_INTERPOL_SHIFT) |
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#define VCO_REG1V45_SEL_SHIFT 6 |
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#define VCO_REG1V45_SEL(x) ((x) << VCO_REG1V45_SEL_SHIFT) |
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#define VCO_REG1V45_SEL_1V40 VCO_REG1V45_SEL(0) |
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#define VCO_REG1V45_SEL_1V45 VCO_REG1V45_SEL(1) |
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#define VCO_REG1V45_SEL_1V50 VCO_REG1V45_SEL(2) |
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#define VCO_REG1V45_SEL_1V55 VCO_REG1V45_SEL(3) |
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#define VCO_REG1V45_SEL_MASK VCO_REG1V45_SEL(3) |
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#define VCO_REG0V9_SEL_SHIFT 8 |
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#define VCO_REG0V9_SEL_MASK (0xf << VCO_REG0V9_SEL_SHIFT) |
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#define VCO_VTHCAL_SHIFT 12 |
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#define VCO_VTHCAL(x) ((x) << VCO_VTHCAL_SHIFT) |
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#define VCO_VTHCAL_0V90 VCO_VTHCAL(0) |
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#define VCO_VTHCAL_0V95 VCO_VTHCAL(1) |
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#define VCO_VTHCAL_1V00 VCO_VTHCAL(2) |
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#define VCO_VTHCAL_1V05 VCO_VTHCAL(3) |
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#define VCO_VTHCAL_MASK VCO_VTHCAL(3) |
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#define VCO_KVCOEXT_SHIFT 14 |
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#define VCO_KVCOEXT_MASK (0x3 << VCO_KVCOEXT_SHIFT) |
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#define VCO_KVCOEXT_ENABLE BIT(17) |
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#define VCO_V2IEXT_SHIFT 18 |
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#define VCO_V2IEXT_MASK (0xf << VCO_V2IEXT_SHIFT) |
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#define VCO_V2IEXT_ENABLE BIT(22) |
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#define VCO_SPEED_SHIFT 23 |
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#define VCO_SPEED(x) ((x) << VCO_SPEED_SHIFT) |
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#define VCO_SPEED_1G08_1G21 VCO_SPEED(0) |
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#define VCO_SPEED_1G21_1G40 VCO_SPEED(1) |
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#define VCO_SPEED_1G40_1G61 VCO_SPEED(2) |
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#define VCO_SPEED_1G61_1G86 VCO_SPEED(3) |
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#define VCO_SPEED_1G86_2G00 VCO_SPEED(4) |
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#define VCO_SPEED_2G00_2G22 VCO_SPEED(5) |
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#define VCO_SPEED_2G22 VCO_SPEED(6) |
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#define VCO_SPEED_MASK VCO_SPEED(0x7) |
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#define VCO_CLKDET_ENABLE BIT(26) |
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#define VCO_CTRL1 AVPLL_CTRL(1) |
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#define VCO_REFDIV_SHIFT 0 |
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#define VCO_REFDIV(x) ((x) << VCO_REFDIV_SHIFT) |
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#define VCO_REFDIV_1 VCO_REFDIV(0) |
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#define VCO_REFDIV_2 VCO_REFDIV(1) |
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#define VCO_REFDIV_4 VCO_REFDIV(2) |
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#define VCO_REFDIV_3 VCO_REFDIV(3) |
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#define VCO_REFDIV_MASK VCO_REFDIV(0x3f) |
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#define VCO_FBDIV_SHIFT 6 |
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#define VCO_FBDIV(x) ((x) << VCO_FBDIV_SHIFT) |
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#define VCO_FBDIV_MASK VCO_FBDIV(0xff) |
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#define VCO_ICP_SHIFT 14 |
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/* PLL Charge Pump Current = 10uA * (x + 1) */ |
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#define VCO_ICP(x) ((x) << VCO_ICP_SHIFT) |
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#define VCO_ICP_MASK VCO_ICP(0xf) |
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#define VCO_LOAD_CAP BIT(18) |
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#define VCO_CALIBRATION_START BIT(19) |
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#define VCO_FREQOFFSETn(x) AVPLL_CTRL(3 + (x)) |
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#define VCO_FREQOFFSET_MASK 0x7ffff |
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#define VCO_CTRL10 AVPLL_CTRL(10) |
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#define VCO_POWERUP_CH1 BIT(20) |
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#define VCO_CTRL11 AVPLL_CTRL(11) |
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#define VCO_CTRL12 AVPLL_CTRL(12) |
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#define VCO_CTRL13 AVPLL_CTRL(13) |
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#define VCO_CTRL14 AVPLL_CTRL(14) |
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#define VCO_CTRL15 AVPLL_CTRL(15) |
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#define VCO_SYNC1n(x) AVPLL_CTRL(15 + (x)) |
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#define VCO_SYNC1_MASK 0x1ffff |
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#define VCO_SYNC2n(x) AVPLL_CTRL(23 + (x)) |
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#define VCO_SYNC2_MASK 0x1ffff |
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#define VCO_CTRL30 AVPLL_CTRL(30) |
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#define VCO_DPLL_CH1_ENABLE BIT(17) |
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struct berlin2_avpll_vco { |
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struct clk_hw hw; |
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void __iomem *base; |
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u8 flags; |
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}; |
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#define to_avpll_vco(hw) container_of(hw, struct berlin2_avpll_vco, hw) |
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static int berlin2_avpll_vco_is_enabled(struct clk_hw *hw) |
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{ |
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struct berlin2_avpll_vco *vco = to_avpll_vco(hw); |
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u32 reg; |
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reg = readl_relaxed(vco->base + VCO_CTRL0); |
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if (vco->flags & BERLIN2_AVPLL_BIT_QUIRK) |
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reg >>= 4; |
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return !!(reg & VCO_POWERUP); |
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} |
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static int berlin2_avpll_vco_enable(struct clk_hw *hw) |
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{ |
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struct berlin2_avpll_vco *vco = to_avpll_vco(hw); |
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u32 reg; |
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reg = readl_relaxed(vco->base + VCO_CTRL0); |
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if (vco->flags & BERLIN2_AVPLL_BIT_QUIRK) |
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reg |= VCO_POWERUP << 4; |
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else |
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reg |= VCO_POWERUP; |
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writel_relaxed(reg, vco->base + VCO_CTRL0); |
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return 0; |
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} |
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static void berlin2_avpll_vco_disable(struct clk_hw *hw) |
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{ |
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struct berlin2_avpll_vco *vco = to_avpll_vco(hw); |
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u32 reg; |
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reg = readl_relaxed(vco->base + VCO_CTRL0); |
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if (vco->flags & BERLIN2_AVPLL_BIT_QUIRK) |
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reg &= ~(VCO_POWERUP << 4); |
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else |
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reg &= ~VCO_POWERUP; |
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writel_relaxed(reg, vco->base + VCO_CTRL0); |
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} |
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static u8 vco_refdiv[] = { 1, 2, 4, 3 }; |
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static unsigned long |
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berlin2_avpll_vco_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) |
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{ |
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struct berlin2_avpll_vco *vco = to_avpll_vco(hw); |
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u32 reg, refdiv, fbdiv; |
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u64 freq = parent_rate; |
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/* AVPLL VCO frequency: Fvco = (Fref / refdiv) * fbdiv */ |
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reg = readl_relaxed(vco->base + VCO_CTRL1); |
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refdiv = (reg & VCO_REFDIV_MASK) >> VCO_REFDIV_SHIFT; |
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refdiv = vco_refdiv[refdiv]; |
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fbdiv = (reg & VCO_FBDIV_MASK) >> VCO_FBDIV_SHIFT; |
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freq *= fbdiv; |
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do_div(freq, refdiv); |
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return (unsigned long)freq; |
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} |
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static const struct clk_ops berlin2_avpll_vco_ops = { |
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.is_enabled = berlin2_avpll_vco_is_enabled, |
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.enable = berlin2_avpll_vco_enable, |
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.disable = berlin2_avpll_vco_disable, |
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.recalc_rate = berlin2_avpll_vco_recalc_rate, |
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}; |
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int __init berlin2_avpll_vco_register(void __iomem *base, |
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const char *name, const char *parent_name, |
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u8 vco_flags, unsigned long flags) |
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{ |
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struct berlin2_avpll_vco *vco; |
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struct clk_init_data init; |
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vco = kzalloc(sizeof(*vco), GFP_KERNEL); |
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if (!vco) |
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return -ENOMEM; |
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vco->base = base; |
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vco->flags = vco_flags; |
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vco->hw.init = &init; |
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init.name = name; |
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init.ops = &berlin2_avpll_vco_ops; |
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init.parent_names = &parent_name; |
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init.num_parents = 1; |
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init.flags = flags; |
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return clk_hw_register(NULL, &vco->hw); |
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} |
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struct berlin2_avpll_channel { |
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struct clk_hw hw; |
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void __iomem *base; |
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u8 flags; |
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u8 index; |
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}; |
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#define to_avpll_channel(hw) container_of(hw, struct berlin2_avpll_channel, hw) |
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static int berlin2_avpll_channel_is_enabled(struct clk_hw *hw) |
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{ |
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struct berlin2_avpll_channel *ch = to_avpll_channel(hw); |
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u32 reg; |
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if (ch->index == 7) |
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return 1; |
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reg = readl_relaxed(ch->base + VCO_CTRL10); |
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reg &= VCO_POWERUP_CH1 << ch->index; |
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return !!reg; |
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} |
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static int berlin2_avpll_channel_enable(struct clk_hw *hw) |
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{ |
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struct berlin2_avpll_channel *ch = to_avpll_channel(hw); |
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u32 reg; |
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reg = readl_relaxed(ch->base + VCO_CTRL10); |
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reg |= VCO_POWERUP_CH1 << ch->index; |
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writel_relaxed(reg, ch->base + VCO_CTRL10); |
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return 0; |
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} |
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static void berlin2_avpll_channel_disable(struct clk_hw *hw) |
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{ |
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struct berlin2_avpll_channel *ch = to_avpll_channel(hw); |
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u32 reg; |
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reg = readl_relaxed(ch->base + VCO_CTRL10); |
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reg &= ~(VCO_POWERUP_CH1 << ch->index); |
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writel_relaxed(reg, ch->base + VCO_CTRL10); |
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} |
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static const u8 div_hdmi[] = { 1, 2, 4, 6 }; |
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static const u8 div_av1[] = { 1, 2, 5, 5 }; |
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static unsigned long |
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berlin2_avpll_channel_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) |
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{ |
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struct berlin2_avpll_channel *ch = to_avpll_channel(hw); |
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u32 reg, div_av2, div_av3, divider = 1; |
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u64 freq = parent_rate; |
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reg = readl_relaxed(ch->base + VCO_CTRL30); |
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if ((reg & (VCO_DPLL_CH1_ENABLE << ch->index)) == 0) |
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goto skip_div; |
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/* |
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* Fch = (Fref * sync2) / |
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* (sync1 * div_hdmi * div_av1 * div_av2 * div_av3) |
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*/ |
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reg = readl_relaxed(ch->base + VCO_SYNC1n(ch->index)); |
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/* BG2/BG2CDs SYNC1 reg on AVPLL_B channel 1 is shifted by 4 */ |
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if (ch->flags & BERLIN2_AVPLL_BIT_QUIRK && ch->index == 0) |
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reg >>= 4; |
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divider = reg & VCO_SYNC1_MASK; |
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reg = readl_relaxed(ch->base + VCO_SYNC2n(ch->index)); |
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freq *= reg & VCO_SYNC2_MASK; |
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/* Channel 8 has no dividers */ |
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if (ch->index == 7) |
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goto skip_div; |
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/* |
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* HDMI divider start at VCO_CTRL11, bit 7; MSB is enable, lower 2 bit |
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* determine divider. |
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*/ |
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reg = readl_relaxed(ch->base + VCO_CTRL11) >> 7; |
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reg = (reg >> (ch->index * 3)); |
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if (reg & BIT(2)) |
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divider *= div_hdmi[reg & 0x3]; |
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/* |
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* AV1 divider start at VCO_CTRL11, bit 28; MSB is enable, lower 2 bit |
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* determine divider. |
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*/ |
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if (ch->index == 0) { |
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reg = readl_relaxed(ch->base + VCO_CTRL11); |
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reg >>= 28; |
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} else { |
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reg = readl_relaxed(ch->base + VCO_CTRL12); |
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reg >>= (ch->index-1) * 3; |
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} |
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if (reg & BIT(2)) |
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divider *= div_av1[reg & 0x3]; |
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/* |
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* AV2 divider start at VCO_CTRL12, bit 18; each 7 bits wide, |
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* zero is not a valid value. |
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*/ |
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if (ch->index < 2) { |
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reg = readl_relaxed(ch->base + VCO_CTRL12); |
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reg >>= 18 + (ch->index * 7); |
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} else if (ch->index < 7) { |
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reg = readl_relaxed(ch->base + VCO_CTRL13); |
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reg >>= (ch->index - 2) * 7; |
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} else { |
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reg = readl_relaxed(ch->base + VCO_CTRL14); |
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} |
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div_av2 = reg & 0x7f; |
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if (div_av2) |
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divider *= div_av2; |
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/* |
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* AV3 divider start at VCO_CTRL14, bit 7; each 4 bits wide. |
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* AV2/AV3 form a fractional divider, where only specfic values for AV3 |
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* are allowed. AV3 != 0 divides by AV2/2, AV3=0 is bypass. |
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*/ |
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if (ch->index < 6) { |
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reg = readl_relaxed(ch->base + VCO_CTRL14); |
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reg >>= 7 + (ch->index * 4); |
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} else { |
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reg = readl_relaxed(ch->base + VCO_CTRL15); |
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} |
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div_av3 = reg & 0xf; |
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if (div_av2 && div_av3) |
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freq *= 2; |
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skip_div: |
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do_div(freq, divider); |
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return (unsigned long)freq; |
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} |
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static const struct clk_ops berlin2_avpll_channel_ops = { |
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.is_enabled = berlin2_avpll_channel_is_enabled, |
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.enable = berlin2_avpll_channel_enable, |
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.disable = berlin2_avpll_channel_disable, |
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.recalc_rate = berlin2_avpll_channel_recalc_rate, |
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}; |
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/* |
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* Another nice quirk: |
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* On some production SoCs, AVPLL channels are scrambled with respect |
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* to the channel numbering in the registers but still referenced by |
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* their original channel numbers. We deal with it by having a flag |
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* and a translation table for the index. |
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*/ |
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static const u8 quirk_index[] __initconst = { 0, 6, 5, 4, 3, 2, 1, 7 }; |
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int __init berlin2_avpll_channel_register(void __iomem *base, |
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const char *name, u8 index, const char *parent_name, |
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u8 ch_flags, unsigned long flags) |
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{ |
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struct berlin2_avpll_channel *ch; |
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struct clk_init_data init; |
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ch = kzalloc(sizeof(*ch), GFP_KERNEL); |
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if (!ch) |
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return -ENOMEM; |
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ch->base = base; |
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if (ch_flags & BERLIN2_AVPLL_SCRAMBLE_QUIRK) |
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ch->index = quirk_index[index]; |
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else |
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ch->index = index; |
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ch->flags = ch_flags; |
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ch->hw.init = &init; |
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init.name = name; |
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init.ops = &berlin2_avpll_channel_ops; |
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init.parent_names = &parent_name; |
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init.num_parents = 1; |
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init.flags = flags; |
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return clk_hw_register(NULL, &ch->hw); |
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}
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