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179 lines
3.9 KiB
179 lines
3.9 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* arch/arm/plat-iop/time.c |
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* |
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* Timer code for IOP32x and IOP33x based systems |
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* |
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* Author: Deepak Saxena <[email protected]> |
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* |
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* Copyright 2002-2003 MontaVista Software Inc. |
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*/ |
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#include <linux/kernel.h> |
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#include <linux/interrupt.h> |
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#include <linux/time.h> |
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#include <linux/init.h> |
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#include <linux/timex.h> |
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#include <linux/io.h> |
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#include <linux/clocksource.h> |
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#include <linux/clockchips.h> |
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#include <linux/export.h> |
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#include <linux/sched_clock.h> |
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#include <asm/irq.h> |
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#include <linux/uaccess.h> |
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#include <asm/mach/irq.h> |
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#include <asm/mach/time.h> |
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#include "hardware.h" |
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#include "irqs.h" |
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/* |
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* Minimum clocksource/clockevent timer range in seconds |
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*/ |
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#define IOP_MIN_RANGE 4 |
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/* |
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* IOP clocksource (free-running timer 1). |
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*/ |
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static u64 notrace iop_clocksource_read(struct clocksource *unused) |
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{ |
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return 0xffffffffu - read_tcr1(); |
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} |
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static struct clocksource iop_clocksource = { |
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.name = "iop_timer1", |
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.rating = 300, |
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.read = iop_clocksource_read, |
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.mask = CLOCKSOURCE_MASK(32), |
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.flags = CLOCK_SOURCE_IS_CONTINUOUS, |
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}; |
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/* |
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* IOP sched_clock() implementation via its clocksource. |
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*/ |
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static u64 notrace iop_read_sched_clock(void) |
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{ |
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return 0xffffffffu - read_tcr1(); |
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} |
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/* |
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* IOP clockevents (interrupting timer 0). |
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*/ |
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static int iop_set_next_event(unsigned long delta, |
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struct clock_event_device *unused) |
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{ |
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u32 tmr = IOP_TMR_PRIVILEGED | IOP_TMR_RATIO_1_1; |
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BUG_ON(delta == 0); |
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write_tmr0(tmr & ~(IOP_TMR_EN | IOP_TMR_RELOAD)); |
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write_tcr0(delta); |
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write_tmr0((tmr & ~IOP_TMR_RELOAD) | IOP_TMR_EN); |
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return 0; |
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} |
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static unsigned long ticks_per_jiffy; |
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static int iop_set_periodic(struct clock_event_device *evt) |
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{ |
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u32 tmr = read_tmr0(); |
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write_tmr0(tmr & ~IOP_TMR_EN); |
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write_tcr0(ticks_per_jiffy - 1); |
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write_trr0(ticks_per_jiffy - 1); |
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tmr |= (IOP_TMR_RELOAD | IOP_TMR_EN); |
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write_tmr0(tmr); |
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return 0; |
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} |
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static int iop_set_oneshot(struct clock_event_device *evt) |
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{ |
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u32 tmr = read_tmr0(); |
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/* ->set_next_event sets period and enables timer */ |
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tmr &= ~(IOP_TMR_RELOAD | IOP_TMR_EN); |
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write_tmr0(tmr); |
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return 0; |
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} |
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static int iop_shutdown(struct clock_event_device *evt) |
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{ |
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u32 tmr = read_tmr0(); |
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tmr &= ~IOP_TMR_EN; |
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write_tmr0(tmr); |
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return 0; |
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} |
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static int iop_resume(struct clock_event_device *evt) |
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{ |
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u32 tmr = read_tmr0(); |
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tmr |= IOP_TMR_EN; |
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write_tmr0(tmr); |
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return 0; |
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} |
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static struct clock_event_device iop_clockevent = { |
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.name = "iop_timer0", |
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.features = CLOCK_EVT_FEAT_PERIODIC | |
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CLOCK_EVT_FEAT_ONESHOT, |
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.rating = 300, |
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.set_next_event = iop_set_next_event, |
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.set_state_shutdown = iop_shutdown, |
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.set_state_periodic = iop_set_periodic, |
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.tick_resume = iop_resume, |
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.set_state_oneshot = iop_set_oneshot, |
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}; |
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static irqreturn_t |
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iop_timer_interrupt(int irq, void *dev_id) |
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{ |
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struct clock_event_device *evt = dev_id; |
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write_tisr(1); |
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evt->event_handler(evt); |
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return IRQ_HANDLED; |
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} |
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static unsigned long iop_tick_rate; |
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unsigned long get_iop_tick_rate(void) |
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{ |
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return iop_tick_rate; |
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} |
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EXPORT_SYMBOL(get_iop_tick_rate); |
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void __init iop_init_time(unsigned long tick_rate) |
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{ |
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u32 timer_ctl; |
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int irq = IRQ_IOP32X_TIMER0; |
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sched_clock_register(iop_read_sched_clock, 32, tick_rate); |
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ticks_per_jiffy = DIV_ROUND_CLOSEST(tick_rate, HZ); |
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iop_tick_rate = tick_rate; |
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timer_ctl = IOP_TMR_EN | IOP_TMR_PRIVILEGED | |
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IOP_TMR_RELOAD | IOP_TMR_RATIO_1_1; |
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/* |
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* Set up interrupting clockevent timer 0. |
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*/ |
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write_tmr0(timer_ctl & ~IOP_TMR_EN); |
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write_tisr(1); |
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if (request_irq(irq, iop_timer_interrupt, IRQF_TIMER | IRQF_IRQPOLL, |
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"IOP Timer Tick", &iop_clockevent)) |
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pr_err("Failed to request irq() %d (IOP Timer Tick)\n", irq); |
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iop_clockevent.cpumask = cpumask_of(0); |
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clockevents_config_and_register(&iop_clockevent, tick_rate, |
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0xf, 0xfffffffe); |
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/* |
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* Set up free-running clocksource timer 1. |
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*/ |
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write_trr1(0xffffffff); |
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write_tcr1(0xffffffff); |
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write_tmr1(timer_ctl); |
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clocksource_register_hz(&iop_clocksource, tick_rate); |
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}
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