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338 lines
8.1 KiB
338 lines
8.1 KiB
// SPDX-License-Identifier: GPL-2.0 |
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// |
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// Xilinx ASoC SPDIF audio support |
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// |
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// Copyright (C) 2018 Xilinx, Inc. |
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// |
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// Author: Maruthi Srinivas Bayyavarapu <[email protected]> |
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// |
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#include <linux/clk.h> |
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#include <linux/io.h> |
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#include <linux/module.h> |
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#include <linux/of.h> |
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#include <linux/of_platform.h> |
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#include <linux/platform_device.h> |
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#include <sound/pcm_params.h> |
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#include <sound/soc.h> |
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#define XLNX_SPDIF_RATES \ |
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(SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 | \ |
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SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 | \ |
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SNDRV_PCM_RATE_192000) |
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#define XLNX_SPDIF_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE) |
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#define XSPDIF_IRQ_STS_REG 0x20 |
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#define XSPDIF_IRQ_ENABLE_REG 0x28 |
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#define XSPDIF_SOFT_RESET_REG 0x40 |
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#define XSPDIF_CONTROL_REG 0x44 |
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#define XSPDIF_CHAN_0_STS_REG 0x4C |
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#define XSPDIF_GLOBAL_IRQ_ENABLE_REG 0x1C |
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#define XSPDIF_CH_A_USER_DATA_REG_0 0x64 |
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#define XSPDIF_CORE_ENABLE_MASK BIT(0) |
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#define XSPDIF_FIFO_FLUSH_MASK BIT(1) |
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#define XSPDIF_CH_STS_MASK BIT(5) |
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#define XSPDIF_GLOBAL_IRQ_ENABLE BIT(31) |
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#define XSPDIF_CLOCK_CONFIG_BITS_MASK GENMASK(5, 2) |
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#define XSPDIF_CLOCK_CONFIG_BITS_SHIFT 2 |
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#define XSPDIF_SOFT_RESET_VALUE 0xA |
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#define MAX_CHANNELS 2 |
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#define AES_SAMPLE_WIDTH 32 |
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#define CH_STATUS_UPDATE_TIMEOUT 40 |
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struct spdif_dev_data { |
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u32 mode; |
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u32 aclk; |
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bool rx_chsts_updated; |
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void __iomem *base; |
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struct clk *axi_clk; |
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wait_queue_head_t chsts_q; |
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}; |
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static irqreturn_t xlnx_spdifrx_irq_handler(int irq, void *arg) |
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{ |
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u32 val; |
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struct spdif_dev_data *ctx = arg; |
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val = readl(ctx->base + XSPDIF_IRQ_STS_REG); |
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if (val & XSPDIF_CH_STS_MASK) { |
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writel(val & XSPDIF_CH_STS_MASK, |
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ctx->base + XSPDIF_IRQ_STS_REG); |
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val = readl(ctx->base + |
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XSPDIF_IRQ_ENABLE_REG); |
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writel(val & ~XSPDIF_CH_STS_MASK, |
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ctx->base + XSPDIF_IRQ_ENABLE_REG); |
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ctx->rx_chsts_updated = true; |
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wake_up_interruptible(&ctx->chsts_q); |
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return IRQ_HANDLED; |
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} |
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return IRQ_NONE; |
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} |
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static int xlnx_spdif_startup(struct snd_pcm_substream *substream, |
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struct snd_soc_dai *dai) |
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{ |
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u32 val; |
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struct spdif_dev_data *ctx = dev_get_drvdata(dai->dev); |
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val = readl(ctx->base + XSPDIF_CONTROL_REG); |
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val |= XSPDIF_FIFO_FLUSH_MASK; |
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writel(val, ctx->base + XSPDIF_CONTROL_REG); |
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if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) { |
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writel(XSPDIF_CH_STS_MASK, |
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ctx->base + XSPDIF_IRQ_ENABLE_REG); |
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writel(XSPDIF_GLOBAL_IRQ_ENABLE, |
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ctx->base + XSPDIF_GLOBAL_IRQ_ENABLE_REG); |
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} |
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return 0; |
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} |
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static void xlnx_spdif_shutdown(struct snd_pcm_substream *substream, |
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struct snd_soc_dai *dai) |
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{ |
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struct spdif_dev_data *ctx = dev_get_drvdata(dai->dev); |
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writel(XSPDIF_SOFT_RESET_VALUE, ctx->base + XSPDIF_SOFT_RESET_REG); |
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} |
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static int xlnx_spdif_hw_params(struct snd_pcm_substream *substream, |
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struct snd_pcm_hw_params *params, |
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struct snd_soc_dai *dai) |
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{ |
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u32 val, clk_div, clk_cfg; |
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struct spdif_dev_data *ctx = dev_get_drvdata(dai->dev); |
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clk_div = DIV_ROUND_CLOSEST(ctx->aclk, MAX_CHANNELS * AES_SAMPLE_WIDTH * |
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params_rate(params)); |
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switch (clk_div) { |
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case 4: |
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clk_cfg = 0; |
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break; |
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case 8: |
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clk_cfg = 1; |
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break; |
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case 16: |
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clk_cfg = 2; |
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break; |
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case 24: |
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clk_cfg = 3; |
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break; |
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case 32: |
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clk_cfg = 4; |
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break; |
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case 48: |
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clk_cfg = 5; |
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break; |
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case 64: |
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clk_cfg = 6; |
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break; |
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default: |
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return -EINVAL; |
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} |
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val = readl(ctx->base + XSPDIF_CONTROL_REG); |
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val &= ~XSPDIF_CLOCK_CONFIG_BITS_MASK; |
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val |= clk_cfg << XSPDIF_CLOCK_CONFIG_BITS_SHIFT; |
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writel(val, ctx->base + XSPDIF_CONTROL_REG); |
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return 0; |
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} |
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static int rx_stream_detect(struct snd_soc_dai *dai) |
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{ |
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int err; |
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struct spdif_dev_data *ctx = dev_get_drvdata(dai->dev); |
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unsigned long jiffies = msecs_to_jiffies(CH_STATUS_UPDATE_TIMEOUT); |
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/* start capture only if stream is detected within 40ms timeout */ |
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err = wait_event_interruptible_timeout(ctx->chsts_q, |
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ctx->rx_chsts_updated, |
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jiffies); |
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if (!err) { |
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dev_err(dai->dev, "No streaming audio detected!\n"); |
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return -EINVAL; |
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} |
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ctx->rx_chsts_updated = false; |
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return 0; |
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} |
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static int xlnx_spdif_trigger(struct snd_pcm_substream *substream, int cmd, |
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struct snd_soc_dai *dai) |
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{ |
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u32 val; |
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int ret = 0; |
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struct spdif_dev_data *ctx = dev_get_drvdata(dai->dev); |
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val = readl(ctx->base + XSPDIF_CONTROL_REG); |
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switch (cmd) { |
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case SNDRV_PCM_TRIGGER_START: |
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case SNDRV_PCM_TRIGGER_RESUME: |
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case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: |
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val |= XSPDIF_CORE_ENABLE_MASK; |
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writel(val, ctx->base + XSPDIF_CONTROL_REG); |
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if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) |
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ret = rx_stream_detect(dai); |
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break; |
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case SNDRV_PCM_TRIGGER_STOP: |
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case SNDRV_PCM_TRIGGER_SUSPEND: |
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case SNDRV_PCM_TRIGGER_PAUSE_PUSH: |
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val &= ~XSPDIF_CORE_ENABLE_MASK; |
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writel(val, ctx->base + XSPDIF_CONTROL_REG); |
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break; |
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default: |
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ret = -EINVAL; |
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} |
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return ret; |
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} |
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static const struct snd_soc_dai_ops xlnx_spdif_dai_ops = { |
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.startup = xlnx_spdif_startup, |
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.shutdown = xlnx_spdif_shutdown, |
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.trigger = xlnx_spdif_trigger, |
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.hw_params = xlnx_spdif_hw_params, |
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}; |
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static struct snd_soc_dai_driver xlnx_spdif_tx_dai = { |
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.name = "xlnx_spdif_tx", |
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.playback = { |
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.channels_min = 2, |
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.channels_max = 2, |
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.rates = XLNX_SPDIF_RATES, |
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.formats = XLNX_SPDIF_FORMATS, |
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}, |
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.ops = &xlnx_spdif_dai_ops, |
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}; |
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static struct snd_soc_dai_driver xlnx_spdif_rx_dai = { |
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.name = "xlnx_spdif_rx", |
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.capture = { |
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.channels_min = 2, |
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.channels_max = 2, |
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.rates = XLNX_SPDIF_RATES, |
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.formats = XLNX_SPDIF_FORMATS, |
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}, |
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.ops = &xlnx_spdif_dai_ops, |
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}; |
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static const struct snd_soc_component_driver xlnx_spdif_component = { |
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.name = "xlnx-spdif", |
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}; |
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static const struct of_device_id xlnx_spdif_of_match[] = { |
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{ .compatible = "xlnx,spdif-2.0", }, |
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{}, |
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}; |
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MODULE_DEVICE_TABLE(of, xlnx_spdif_of_match); |
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static int xlnx_spdif_probe(struct platform_device *pdev) |
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{ |
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int ret; |
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struct resource *res; |
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struct snd_soc_dai_driver *dai_drv; |
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struct spdif_dev_data *ctx; |
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struct device *dev = &pdev->dev; |
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struct device_node *node = dev->of_node; |
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ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); |
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if (!ctx) |
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return -ENOMEM; |
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ctx->axi_clk = devm_clk_get(dev, "s_axi_aclk"); |
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if (IS_ERR(ctx->axi_clk)) { |
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ret = PTR_ERR(ctx->axi_clk); |
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dev_err(dev, "failed to get s_axi_aclk(%d)\n", ret); |
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return ret; |
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} |
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ret = clk_prepare_enable(ctx->axi_clk); |
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if (ret) { |
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dev_err(dev, "failed to enable s_axi_aclk(%d)\n", ret); |
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return ret; |
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} |
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ctx->base = devm_platform_ioremap_resource(pdev, 0); |
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if (IS_ERR(ctx->base)) { |
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ret = PTR_ERR(ctx->base); |
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goto clk_err; |
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} |
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ret = of_property_read_u32(node, "xlnx,spdif-mode", &ctx->mode); |
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if (ret < 0) { |
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dev_err(dev, "cannot get SPDIF mode\n"); |
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goto clk_err; |
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} |
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if (ctx->mode) { |
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dai_drv = &xlnx_spdif_tx_dai; |
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} else { |
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res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); |
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if (!res) { |
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dev_err(dev, "No IRQ resource found\n"); |
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ret = -ENODEV; |
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goto clk_err; |
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} |
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ret = devm_request_irq(dev, res->start, |
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xlnx_spdifrx_irq_handler, |
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0, "XLNX_SPDIF_RX", ctx); |
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if (ret) { |
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dev_err(dev, "spdif rx irq request failed\n"); |
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ret = -ENODEV; |
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goto clk_err; |
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} |
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init_waitqueue_head(&ctx->chsts_q); |
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dai_drv = &xlnx_spdif_rx_dai; |
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} |
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ret = of_property_read_u32(node, "xlnx,aud_clk_i", &ctx->aclk); |
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if (ret < 0) { |
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dev_err(dev, "cannot get aud_clk_i value\n"); |
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goto clk_err; |
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} |
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dev_set_drvdata(dev, ctx); |
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ret = devm_snd_soc_register_component(dev, &xlnx_spdif_component, |
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dai_drv, 1); |
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if (ret) { |
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dev_err(dev, "SPDIF component registration failed\n"); |
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goto clk_err; |
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} |
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writel(XSPDIF_SOFT_RESET_VALUE, ctx->base + XSPDIF_SOFT_RESET_REG); |
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dev_info(dev, "%s DAI registered\n", dai_drv->name); |
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clk_err: |
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clk_disable_unprepare(ctx->axi_clk); |
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return ret; |
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} |
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static int xlnx_spdif_remove(struct platform_device *pdev) |
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{ |
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struct spdif_dev_data *ctx = dev_get_drvdata(&pdev->dev); |
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clk_disable_unprepare(ctx->axi_clk); |
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return 0; |
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} |
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static struct platform_driver xlnx_spdif_driver = { |
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.driver = { |
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.name = "xlnx-spdif", |
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.of_match_table = xlnx_spdif_of_match, |
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}, |
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.probe = xlnx_spdif_probe, |
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.remove = xlnx_spdif_remove, |
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}; |
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module_platform_driver(xlnx_spdif_driver); |
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MODULE_AUTHOR("Maruthi Srinivas Bayyavarapu <[email protected]>"); |
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MODULE_DESCRIPTION("XILINX SPDIF driver"); |
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MODULE_LICENSE("GPL v2");
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