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769 lines
22 KiB
769 lines
22 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* ALSA SoC I2S (McBSP) Audio Layer for TI DAVINCI processor |
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* |
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* Author: Vladimir Barinov, <[email protected]> |
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* Copyright: (C) 2007 MontaVista Software, Inc., <[email protected]> |
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* |
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* DT support (c) 2016 Petr Kulhavy, Barix AG <[email protected]> |
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* based on davinci-mcasp.c DT support |
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* |
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* TODO: |
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* on DA850 implement HW FIFOs instead of DMA into DXR and DRR registers |
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*/ |
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|
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#include <linux/init.h> |
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#include <linux/module.h> |
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#include <linux/device.h> |
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#include <linux/slab.h> |
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#include <linux/delay.h> |
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#include <linux/io.h> |
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#include <linux/clk.h> |
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#include <linux/platform_data/davinci_asp.h> |
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#include <sound/core.h> |
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#include <sound/pcm.h> |
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#include <sound/pcm_params.h> |
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#include <sound/initval.h> |
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#include <sound/soc.h> |
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#include <sound/dmaengine_pcm.h> |
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|
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#include "edma-pcm.h" |
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#include "davinci-i2s.h" |
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#define DRV_NAME "davinci-i2s" |
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|
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/* |
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* NOTE: terminology here is confusing. |
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* |
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* - This driver supports the "Audio Serial Port" (ASP), |
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* found on dm6446, dm355, and other DaVinci chips. |
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* |
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* - But it labels it a "Multi-channel Buffered Serial Port" |
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* (McBSP) as on older chips like the dm642 ... which was |
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* backward-compatible, possibly explaining that confusion. |
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* |
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* - OMAP chips have a controller called McBSP, which is |
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* incompatible with the DaVinci flavor of McBSP. |
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* |
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* - Newer DaVinci chips have a controller called McASP, |
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* incompatible with ASP and with either McBSP. |
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* |
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* In short: this uses ASP to implement I2S, not McBSP. |
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* And it won't be the only DaVinci implemention of I2S. |
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*/ |
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#define DAVINCI_MCBSP_DRR_REG 0x00 |
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#define DAVINCI_MCBSP_DXR_REG 0x04 |
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#define DAVINCI_MCBSP_SPCR_REG 0x08 |
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#define DAVINCI_MCBSP_RCR_REG 0x0c |
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#define DAVINCI_MCBSP_XCR_REG 0x10 |
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#define DAVINCI_MCBSP_SRGR_REG 0x14 |
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#define DAVINCI_MCBSP_PCR_REG 0x24 |
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|
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#define DAVINCI_MCBSP_SPCR_RRST (1 << 0) |
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#define DAVINCI_MCBSP_SPCR_RINTM(v) ((v) << 4) |
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#define DAVINCI_MCBSP_SPCR_XRST (1 << 16) |
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#define DAVINCI_MCBSP_SPCR_XINTM(v) ((v) << 20) |
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#define DAVINCI_MCBSP_SPCR_GRST (1 << 22) |
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#define DAVINCI_MCBSP_SPCR_FRST (1 << 23) |
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#define DAVINCI_MCBSP_SPCR_FREE (1 << 25) |
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#define DAVINCI_MCBSP_RCR_RWDLEN1(v) ((v) << 5) |
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#define DAVINCI_MCBSP_RCR_RFRLEN1(v) ((v) << 8) |
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#define DAVINCI_MCBSP_RCR_RDATDLY(v) ((v) << 16) |
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#define DAVINCI_MCBSP_RCR_RFIG (1 << 18) |
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#define DAVINCI_MCBSP_RCR_RWDLEN2(v) ((v) << 21) |
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#define DAVINCI_MCBSP_RCR_RFRLEN2(v) ((v) << 24) |
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#define DAVINCI_MCBSP_RCR_RPHASE BIT(31) |
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#define DAVINCI_MCBSP_XCR_XWDLEN1(v) ((v) << 5) |
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#define DAVINCI_MCBSP_XCR_XFRLEN1(v) ((v) << 8) |
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#define DAVINCI_MCBSP_XCR_XDATDLY(v) ((v) << 16) |
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#define DAVINCI_MCBSP_XCR_XFIG (1 << 18) |
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#define DAVINCI_MCBSP_XCR_XWDLEN2(v) ((v) << 21) |
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#define DAVINCI_MCBSP_XCR_XFRLEN2(v) ((v) << 24) |
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#define DAVINCI_MCBSP_XCR_XPHASE BIT(31) |
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|
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#define DAVINCI_MCBSP_SRGR_FWID(v) ((v) << 8) |
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#define DAVINCI_MCBSP_SRGR_FPER(v) ((v) << 16) |
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#define DAVINCI_MCBSP_SRGR_FSGM (1 << 28) |
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#define DAVINCI_MCBSP_SRGR_CLKSM BIT(29) |
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|
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#define DAVINCI_MCBSP_PCR_CLKRP (1 << 0) |
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#define DAVINCI_MCBSP_PCR_CLKXP (1 << 1) |
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#define DAVINCI_MCBSP_PCR_FSRP (1 << 2) |
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#define DAVINCI_MCBSP_PCR_FSXP (1 << 3) |
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#define DAVINCI_MCBSP_PCR_SCLKME (1 << 7) |
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#define DAVINCI_MCBSP_PCR_CLKRM (1 << 8) |
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#define DAVINCI_MCBSP_PCR_CLKXM (1 << 9) |
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#define DAVINCI_MCBSP_PCR_FSRM (1 << 10) |
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#define DAVINCI_MCBSP_PCR_FSXM (1 << 11) |
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enum { |
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DAVINCI_MCBSP_WORD_8 = 0, |
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DAVINCI_MCBSP_WORD_12, |
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DAVINCI_MCBSP_WORD_16, |
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DAVINCI_MCBSP_WORD_20, |
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DAVINCI_MCBSP_WORD_24, |
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DAVINCI_MCBSP_WORD_32, |
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}; |
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static const unsigned char data_type[SNDRV_PCM_FORMAT_S32_LE + 1] = { |
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[SNDRV_PCM_FORMAT_S8] = 1, |
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[SNDRV_PCM_FORMAT_S16_LE] = 2, |
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[SNDRV_PCM_FORMAT_S32_LE] = 4, |
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}; |
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static const unsigned char asp_word_length[SNDRV_PCM_FORMAT_S32_LE + 1] = { |
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[SNDRV_PCM_FORMAT_S8] = DAVINCI_MCBSP_WORD_8, |
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[SNDRV_PCM_FORMAT_S16_LE] = DAVINCI_MCBSP_WORD_16, |
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[SNDRV_PCM_FORMAT_S32_LE] = DAVINCI_MCBSP_WORD_32, |
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}; |
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static const unsigned char double_fmt[SNDRV_PCM_FORMAT_S32_LE + 1] = { |
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[SNDRV_PCM_FORMAT_S8] = SNDRV_PCM_FORMAT_S16_LE, |
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[SNDRV_PCM_FORMAT_S16_LE] = SNDRV_PCM_FORMAT_S32_LE, |
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}; |
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struct davinci_mcbsp_dev { |
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struct device *dev; |
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struct snd_dmaengine_dai_dma_data dma_data[2]; |
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int dma_request[2]; |
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void __iomem *base; |
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#define MOD_DSP_A 0 |
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#define MOD_DSP_B 1 |
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int mode; |
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u32 pcr; |
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struct clk *clk; |
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/* |
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* Combining both channels into 1 element will at least double the |
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* amount of time between servicing the dma channel, increase |
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* effiency, and reduce the chance of overrun/underrun. But, |
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* it will result in the left & right channels being swapped. |
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* |
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* If relabeling the left and right channels is not possible, |
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* you may want to let the codec know to swap them back. |
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* |
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* It may allow x10 the amount of time to service dma requests, |
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* if the codec is master and is using an unnecessarily fast bit clock |
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* (ie. tlvaic23b), independent of the sample rate. So, having an |
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* entire frame at once means it can be serviced at the sample rate |
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* instead of the bit clock rate. |
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* |
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* In the now unlikely case that an underrun still |
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* occurs, both the left and right samples will be repeated |
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* so that no pops are heard, and the left and right channels |
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* won't end up being swapped because of the underrun. |
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*/ |
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unsigned enable_channel_combine:1; |
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unsigned int fmt; |
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int clk_div; |
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int clk_input_pin; |
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bool i2s_accurate_sck; |
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}; |
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static inline void davinci_mcbsp_write_reg(struct davinci_mcbsp_dev *dev, |
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int reg, u32 val) |
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{ |
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__raw_writel(val, dev->base + reg); |
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} |
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static inline u32 davinci_mcbsp_read_reg(struct davinci_mcbsp_dev *dev, int reg) |
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{ |
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return __raw_readl(dev->base + reg); |
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} |
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static void toggle_clock(struct davinci_mcbsp_dev *dev, int playback) |
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{ |
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u32 m = playback ? DAVINCI_MCBSP_PCR_CLKXP : DAVINCI_MCBSP_PCR_CLKRP; |
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/* The clock needs to toggle to complete reset. |
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* So, fake it by toggling the clk polarity. |
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*/ |
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davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, dev->pcr ^ m); |
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davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, dev->pcr); |
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} |
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static void davinci_mcbsp_start(struct davinci_mcbsp_dev *dev, |
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struct snd_pcm_substream *substream) |
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{ |
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int playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK); |
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u32 spcr; |
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u32 mask = playback ? DAVINCI_MCBSP_SPCR_XRST : DAVINCI_MCBSP_SPCR_RRST; |
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|
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/* Enable transmitter or receiver */ |
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spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG); |
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spcr |= mask; |
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if (dev->pcr & (DAVINCI_MCBSP_PCR_FSXM | DAVINCI_MCBSP_PCR_FSRM)) { |
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/* Start frame sync */ |
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spcr |= DAVINCI_MCBSP_SPCR_FRST; |
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} |
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davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr); |
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} |
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static void davinci_mcbsp_stop(struct davinci_mcbsp_dev *dev, int playback) |
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{ |
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u32 spcr; |
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/* Reset transmitter/receiver and sample rate/frame sync generators */ |
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spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG); |
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spcr &= ~(DAVINCI_MCBSP_SPCR_GRST | DAVINCI_MCBSP_SPCR_FRST); |
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spcr &= playback ? ~DAVINCI_MCBSP_SPCR_XRST : ~DAVINCI_MCBSP_SPCR_RRST; |
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davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr); |
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toggle_clock(dev, playback); |
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} |
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#define DEFAULT_BITPERSAMPLE 16 |
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static int davinci_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai, |
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unsigned int fmt) |
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{ |
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struct davinci_mcbsp_dev *dev = snd_soc_dai_get_drvdata(cpu_dai); |
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unsigned int pcr; |
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unsigned int srgr; |
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bool inv_fs = false; |
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/* Attention srgr is updated by hw_params! */ |
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srgr = DAVINCI_MCBSP_SRGR_FSGM | |
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DAVINCI_MCBSP_SRGR_FPER(DEFAULT_BITPERSAMPLE * 2 - 1) | |
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DAVINCI_MCBSP_SRGR_FWID(DEFAULT_BITPERSAMPLE - 1); |
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dev->fmt = fmt; |
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/* set master/slave audio interface */ |
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switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { |
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case SND_SOC_DAIFMT_CBS_CFS: |
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/* cpu is master */ |
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pcr = DAVINCI_MCBSP_PCR_FSXM | |
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DAVINCI_MCBSP_PCR_FSRM | |
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DAVINCI_MCBSP_PCR_CLKXM | |
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DAVINCI_MCBSP_PCR_CLKRM; |
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break; |
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case SND_SOC_DAIFMT_CBM_CFS: |
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pcr = DAVINCI_MCBSP_PCR_FSRM | DAVINCI_MCBSP_PCR_FSXM; |
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/* |
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* Selection of the clock input pin that is the |
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* input for the Sample Rate Generator. |
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* McBSP FSR and FSX are driven by the Sample Rate |
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* Generator. |
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*/ |
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switch (dev->clk_input_pin) { |
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case MCBSP_CLKS: |
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pcr |= DAVINCI_MCBSP_PCR_CLKXM | |
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DAVINCI_MCBSP_PCR_CLKRM; |
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break; |
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case MCBSP_CLKR: |
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pcr |= DAVINCI_MCBSP_PCR_SCLKME; |
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break; |
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default: |
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dev_err(dev->dev, "bad clk_input_pin\n"); |
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return -EINVAL; |
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} |
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break; |
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case SND_SOC_DAIFMT_CBM_CFM: |
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/* codec is master */ |
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pcr = 0; |
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break; |
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default: |
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printk(KERN_ERR "%s:bad master\n", __func__); |
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return -EINVAL; |
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} |
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/* interface format */ |
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switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { |
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case SND_SOC_DAIFMT_I2S: |
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/* Davinci doesn't support TRUE I2S, but some codecs will have |
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* the left and right channels contiguous. This allows |
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* dsp_a mode to be used with an inverted normal frame clk. |
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* If your codec is master and does not have contiguous |
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* channels, then you will have sound on only one channel. |
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* Try using a different mode, or codec as slave. |
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* |
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* The TLV320AIC33 is an example of a codec where this works. |
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* It has a variable bit clock frequency allowing it to have |
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* valid data on every bit clock. |
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* |
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* The TLV320AIC23 is an example of a codec where this does not |
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* work. It has a fixed bit clock frequency with progressively |
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* more empty bit clock slots between channels as the sample |
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* rate is lowered. |
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*/ |
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inv_fs = true; |
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fallthrough; |
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case SND_SOC_DAIFMT_DSP_A: |
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dev->mode = MOD_DSP_A; |
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break; |
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case SND_SOC_DAIFMT_DSP_B: |
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dev->mode = MOD_DSP_B; |
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break; |
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default: |
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printk(KERN_ERR "%s:bad format\n", __func__); |
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return -EINVAL; |
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} |
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switch (fmt & SND_SOC_DAIFMT_INV_MASK) { |
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case SND_SOC_DAIFMT_NB_NF: |
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/* CLKRP Receive clock polarity, |
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* 1 - sampled on rising edge of CLKR |
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* valid on rising edge |
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* CLKXP Transmit clock polarity, |
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* 1 - clocked on falling edge of CLKX |
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* valid on rising edge |
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* FSRP Receive frame sync pol, 0 - active high |
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* FSXP Transmit frame sync pol, 0 - active high |
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*/ |
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pcr |= (DAVINCI_MCBSP_PCR_CLKXP | DAVINCI_MCBSP_PCR_CLKRP); |
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break; |
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case SND_SOC_DAIFMT_IB_IF: |
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/* CLKRP Receive clock polarity, |
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* 0 - sampled on falling edge of CLKR |
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* valid on falling edge |
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* CLKXP Transmit clock polarity, |
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* 0 - clocked on rising edge of CLKX |
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* valid on falling edge |
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* FSRP Receive frame sync pol, 1 - active low |
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* FSXP Transmit frame sync pol, 1 - active low |
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*/ |
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pcr |= (DAVINCI_MCBSP_PCR_FSXP | DAVINCI_MCBSP_PCR_FSRP); |
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break; |
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case SND_SOC_DAIFMT_NB_IF: |
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/* CLKRP Receive clock polarity, |
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* 1 - sampled on rising edge of CLKR |
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* valid on rising edge |
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* CLKXP Transmit clock polarity, |
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* 1 - clocked on falling edge of CLKX |
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* valid on rising edge |
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* FSRP Receive frame sync pol, 1 - active low |
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* FSXP Transmit frame sync pol, 1 - active low |
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*/ |
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pcr |= (DAVINCI_MCBSP_PCR_CLKXP | DAVINCI_MCBSP_PCR_CLKRP | |
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DAVINCI_MCBSP_PCR_FSXP | DAVINCI_MCBSP_PCR_FSRP); |
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break; |
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case SND_SOC_DAIFMT_IB_NF: |
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/* CLKRP Receive clock polarity, |
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* 0 - sampled on falling edge of CLKR |
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* valid on falling edge |
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* CLKXP Transmit clock polarity, |
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* 0 - clocked on rising edge of CLKX |
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* valid on falling edge |
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* FSRP Receive frame sync pol, 0 - active high |
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* FSXP Transmit frame sync pol, 0 - active high |
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*/ |
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break; |
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default: |
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return -EINVAL; |
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} |
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if (inv_fs == true) |
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pcr ^= (DAVINCI_MCBSP_PCR_FSXP | DAVINCI_MCBSP_PCR_FSRP); |
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davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SRGR_REG, srgr); |
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dev->pcr = pcr; |
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davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, pcr); |
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return 0; |
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} |
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|
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static int davinci_i2s_dai_set_clkdiv(struct snd_soc_dai *cpu_dai, |
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int div_id, int div) |
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{ |
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struct davinci_mcbsp_dev *dev = snd_soc_dai_get_drvdata(cpu_dai); |
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|
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if (div_id != DAVINCI_MCBSP_CLKGDV) |
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return -ENODEV; |
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dev->clk_div = div; |
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return 0; |
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} |
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|
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static int davinci_i2s_hw_params(struct snd_pcm_substream *substream, |
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struct snd_pcm_hw_params *params, |
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struct snd_soc_dai *dai) |
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{ |
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struct davinci_mcbsp_dev *dev = snd_soc_dai_get_drvdata(dai); |
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struct snd_interval *i = NULL; |
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int mcbsp_word_length, master; |
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unsigned int rcr, xcr, srgr, clk_div, freq, framesize; |
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u32 spcr; |
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snd_pcm_format_t fmt; |
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unsigned element_cnt = 1; |
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|
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/* general line settings */ |
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spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG); |
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if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) { |
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spcr |= DAVINCI_MCBSP_SPCR_RINTM(3) | DAVINCI_MCBSP_SPCR_FREE; |
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davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr); |
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} else { |
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spcr |= DAVINCI_MCBSP_SPCR_XINTM(3) | DAVINCI_MCBSP_SPCR_FREE; |
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davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr); |
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} |
|
|
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master = dev->fmt & SND_SOC_DAIFMT_MASTER_MASK; |
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fmt = params_format(params); |
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mcbsp_word_length = asp_word_length[fmt]; |
|
|
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switch (master) { |
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case SND_SOC_DAIFMT_CBS_CFS: |
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freq = clk_get_rate(dev->clk); |
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srgr = DAVINCI_MCBSP_SRGR_FSGM | |
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DAVINCI_MCBSP_SRGR_CLKSM; |
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srgr |= DAVINCI_MCBSP_SRGR_FWID(mcbsp_word_length * |
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8 - 1); |
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if (dev->i2s_accurate_sck) { |
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clk_div = 256; |
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do { |
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framesize = (freq / (--clk_div)) / |
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params->rate_num * |
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params->rate_den; |
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} while (((framesize < 33) || (framesize > 4095)) && |
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(clk_div)); |
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clk_div--; |
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srgr |= DAVINCI_MCBSP_SRGR_FPER(framesize - 1); |
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} else { |
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/* symmetric waveforms */ |
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clk_div = freq / (mcbsp_word_length * 16) / |
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params->rate_num * params->rate_den; |
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srgr |= DAVINCI_MCBSP_SRGR_FPER(mcbsp_word_length * |
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16 - 1); |
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} |
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clk_div &= 0xFF; |
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srgr |= clk_div; |
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break; |
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case SND_SOC_DAIFMT_CBM_CFS: |
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srgr = DAVINCI_MCBSP_SRGR_FSGM; |
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clk_div = dev->clk_div - 1; |
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srgr |= DAVINCI_MCBSP_SRGR_FWID(mcbsp_word_length * 8 - 1); |
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srgr |= DAVINCI_MCBSP_SRGR_FPER(mcbsp_word_length * 16 - 1); |
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clk_div &= 0xFF; |
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srgr |= clk_div; |
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break; |
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case SND_SOC_DAIFMT_CBM_CFM: |
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/* Clock and frame sync given from external sources */ |
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i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_SAMPLE_BITS); |
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srgr = DAVINCI_MCBSP_SRGR_FSGM; |
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srgr |= DAVINCI_MCBSP_SRGR_FWID(snd_interval_value(i) - 1); |
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pr_debug("%s - %d FWID set: re-read srgr = %X\n", |
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__func__, __LINE__, snd_interval_value(i) - 1); |
|
|
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i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_FRAME_BITS); |
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srgr |= DAVINCI_MCBSP_SRGR_FPER(snd_interval_value(i) - 1); |
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break; |
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default: |
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return -EINVAL; |
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} |
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davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SRGR_REG, srgr); |
|
|
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rcr = DAVINCI_MCBSP_RCR_RFIG; |
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xcr = DAVINCI_MCBSP_XCR_XFIG; |
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if (dev->mode == MOD_DSP_B) { |
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rcr |= DAVINCI_MCBSP_RCR_RDATDLY(0); |
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xcr |= DAVINCI_MCBSP_XCR_XDATDLY(0); |
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} else { |
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rcr |= DAVINCI_MCBSP_RCR_RDATDLY(1); |
|
xcr |= DAVINCI_MCBSP_XCR_XDATDLY(1); |
|
} |
|
/* Determine xfer data type */ |
|
fmt = params_format(params); |
|
if ((fmt > SNDRV_PCM_FORMAT_S32_LE) || !data_type[fmt]) { |
|
printk(KERN_WARNING "davinci-i2s: unsupported PCM format\n"); |
|
return -EINVAL; |
|
} |
|
|
|
if (params_channels(params) == 2) { |
|
element_cnt = 2; |
|
if (double_fmt[fmt] && dev->enable_channel_combine) { |
|
element_cnt = 1; |
|
fmt = double_fmt[fmt]; |
|
} |
|
switch (master) { |
|
case SND_SOC_DAIFMT_CBS_CFS: |
|
case SND_SOC_DAIFMT_CBS_CFM: |
|
rcr |= DAVINCI_MCBSP_RCR_RFRLEN2(0); |
|
xcr |= DAVINCI_MCBSP_XCR_XFRLEN2(0); |
|
rcr |= DAVINCI_MCBSP_RCR_RPHASE; |
|
xcr |= DAVINCI_MCBSP_XCR_XPHASE; |
|
break; |
|
case SND_SOC_DAIFMT_CBM_CFM: |
|
case SND_SOC_DAIFMT_CBM_CFS: |
|
rcr |= DAVINCI_MCBSP_RCR_RFRLEN2(element_cnt - 1); |
|
xcr |= DAVINCI_MCBSP_XCR_XFRLEN2(element_cnt - 1); |
|
break; |
|
default: |
|
return -EINVAL; |
|
} |
|
} |
|
mcbsp_word_length = asp_word_length[fmt]; |
|
|
|
switch (master) { |
|
case SND_SOC_DAIFMT_CBS_CFS: |
|
case SND_SOC_DAIFMT_CBS_CFM: |
|
rcr |= DAVINCI_MCBSP_RCR_RFRLEN1(0); |
|
xcr |= DAVINCI_MCBSP_XCR_XFRLEN1(0); |
|
break; |
|
case SND_SOC_DAIFMT_CBM_CFM: |
|
case SND_SOC_DAIFMT_CBM_CFS: |
|
rcr |= DAVINCI_MCBSP_RCR_RFRLEN1(element_cnt - 1); |
|
xcr |= DAVINCI_MCBSP_XCR_XFRLEN1(element_cnt - 1); |
|
break; |
|
default: |
|
return -EINVAL; |
|
} |
|
|
|
rcr |= DAVINCI_MCBSP_RCR_RWDLEN1(mcbsp_word_length) | |
|
DAVINCI_MCBSP_RCR_RWDLEN2(mcbsp_word_length); |
|
xcr |= DAVINCI_MCBSP_XCR_XWDLEN1(mcbsp_word_length) | |
|
DAVINCI_MCBSP_XCR_XWDLEN2(mcbsp_word_length); |
|
|
|
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) |
|
davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_XCR_REG, xcr); |
|
else |
|
davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_RCR_REG, rcr); |
|
|
|
pr_debug("%s - %d srgr=%X\n", __func__, __LINE__, srgr); |
|
pr_debug("%s - %d xcr=%X\n", __func__, __LINE__, xcr); |
|
pr_debug("%s - %d rcr=%X\n", __func__, __LINE__, rcr); |
|
return 0; |
|
} |
|
|
|
static int davinci_i2s_prepare(struct snd_pcm_substream *substream, |
|
struct snd_soc_dai *dai) |
|
{ |
|
struct davinci_mcbsp_dev *dev = snd_soc_dai_get_drvdata(dai); |
|
int playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK); |
|
u32 spcr; |
|
u32 mask = playback ? DAVINCI_MCBSP_SPCR_XRST : DAVINCI_MCBSP_SPCR_RRST; |
|
|
|
davinci_mcbsp_stop(dev, playback); |
|
|
|
spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG); |
|
if (spcr & mask) { |
|
/* start off disabled */ |
|
davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, |
|
spcr & ~mask); |
|
toggle_clock(dev, playback); |
|
} |
|
if (dev->pcr & (DAVINCI_MCBSP_PCR_FSXM | DAVINCI_MCBSP_PCR_FSRM | |
|
DAVINCI_MCBSP_PCR_CLKXM | DAVINCI_MCBSP_PCR_CLKRM)) { |
|
/* Start the sample generator */ |
|
spcr |= DAVINCI_MCBSP_SPCR_GRST; |
|
davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr); |
|
} |
|
|
|
if (playback) { |
|
/* Enable the transmitter */ |
|
spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG); |
|
spcr |= DAVINCI_MCBSP_SPCR_XRST; |
|
davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr); |
|
|
|
/* wait for any unexpected frame sync error to occur */ |
|
udelay(100); |
|
|
|
/* Disable the transmitter to clear any outstanding XSYNCERR */ |
|
spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG); |
|
spcr &= ~DAVINCI_MCBSP_SPCR_XRST; |
|
davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr); |
|
toggle_clock(dev, playback); |
|
} |
|
|
|
return 0; |
|
} |
|
|
|
static int davinci_i2s_trigger(struct snd_pcm_substream *substream, int cmd, |
|
struct snd_soc_dai *dai) |
|
{ |
|
struct davinci_mcbsp_dev *dev = snd_soc_dai_get_drvdata(dai); |
|
int ret = 0; |
|
int playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK); |
|
|
|
switch (cmd) { |
|
case SNDRV_PCM_TRIGGER_START: |
|
case SNDRV_PCM_TRIGGER_RESUME: |
|
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: |
|
davinci_mcbsp_start(dev, substream); |
|
break; |
|
case SNDRV_PCM_TRIGGER_STOP: |
|
case SNDRV_PCM_TRIGGER_SUSPEND: |
|
case SNDRV_PCM_TRIGGER_PAUSE_PUSH: |
|
davinci_mcbsp_stop(dev, playback); |
|
break; |
|
default: |
|
ret = -EINVAL; |
|
} |
|
return ret; |
|
} |
|
|
|
static void davinci_i2s_shutdown(struct snd_pcm_substream *substream, |
|
struct snd_soc_dai *dai) |
|
{ |
|
struct davinci_mcbsp_dev *dev = snd_soc_dai_get_drvdata(dai); |
|
int playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK); |
|
davinci_mcbsp_stop(dev, playback); |
|
} |
|
|
|
#define DAVINCI_I2S_RATES SNDRV_PCM_RATE_8000_96000 |
|
#define DAVINCI_I2S_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \ |
|
SNDRV_PCM_FMTBIT_S32_LE) |
|
|
|
static const struct snd_soc_dai_ops davinci_i2s_dai_ops = { |
|
.shutdown = davinci_i2s_shutdown, |
|
.prepare = davinci_i2s_prepare, |
|
.trigger = davinci_i2s_trigger, |
|
.hw_params = davinci_i2s_hw_params, |
|
.set_fmt = davinci_i2s_set_dai_fmt, |
|
.set_clkdiv = davinci_i2s_dai_set_clkdiv, |
|
|
|
}; |
|
|
|
static int davinci_i2s_dai_probe(struct snd_soc_dai *dai) |
|
{ |
|
struct davinci_mcbsp_dev *dev = snd_soc_dai_get_drvdata(dai); |
|
|
|
dai->playback_dma_data = &dev->dma_data[SNDRV_PCM_STREAM_PLAYBACK]; |
|
dai->capture_dma_data = &dev->dma_data[SNDRV_PCM_STREAM_CAPTURE]; |
|
|
|
return 0; |
|
} |
|
|
|
static struct snd_soc_dai_driver davinci_i2s_dai = { |
|
.probe = davinci_i2s_dai_probe, |
|
.playback = { |
|
.channels_min = 2, |
|
.channels_max = 2, |
|
.rates = DAVINCI_I2S_RATES, |
|
.formats = DAVINCI_I2S_FORMATS, |
|
}, |
|
.capture = { |
|
.channels_min = 2, |
|
.channels_max = 2, |
|
.rates = DAVINCI_I2S_RATES, |
|
.formats = DAVINCI_I2S_FORMATS, |
|
}, |
|
.ops = &davinci_i2s_dai_ops, |
|
|
|
}; |
|
|
|
static const struct snd_soc_component_driver davinci_i2s_component = { |
|
.name = DRV_NAME, |
|
}; |
|
|
|
static int davinci_i2s_probe(struct platform_device *pdev) |
|
{ |
|
struct snd_dmaengine_dai_dma_data *dma_data; |
|
struct davinci_mcbsp_dev *dev; |
|
struct resource *mem, *res; |
|
void __iomem *io_base; |
|
int *dma; |
|
int ret; |
|
|
|
mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu"); |
|
if (!mem) { |
|
dev_warn(&pdev->dev, |
|
"\"mpu\" mem resource not found, using index 0\n"); |
|
mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
|
if (!mem) { |
|
dev_err(&pdev->dev, "no mem resource?\n"); |
|
return -ENODEV; |
|
} |
|
} |
|
|
|
io_base = devm_ioremap_resource(&pdev->dev, mem); |
|
if (IS_ERR(io_base)) |
|
return PTR_ERR(io_base); |
|
|
|
dev = devm_kzalloc(&pdev->dev, sizeof(struct davinci_mcbsp_dev), |
|
GFP_KERNEL); |
|
if (!dev) |
|
return -ENOMEM; |
|
|
|
dev->base = io_base; |
|
|
|
/* setup DMA, first TX, then RX */ |
|
dma_data = &dev->dma_data[SNDRV_PCM_STREAM_PLAYBACK]; |
|
dma_data->addr = (dma_addr_t)(mem->start + DAVINCI_MCBSP_DXR_REG); |
|
|
|
res = platform_get_resource(pdev, IORESOURCE_DMA, 0); |
|
if (res) { |
|
dma = &dev->dma_request[SNDRV_PCM_STREAM_PLAYBACK]; |
|
*dma = res->start; |
|
dma_data->filter_data = dma; |
|
} else if (IS_ENABLED(CONFIG_OF) && pdev->dev.of_node) { |
|
dma_data->filter_data = "tx"; |
|
} else { |
|
dev_err(&pdev->dev, "Missing DMA tx resource\n"); |
|
return -ENODEV; |
|
} |
|
|
|
dma_data = &dev->dma_data[SNDRV_PCM_STREAM_CAPTURE]; |
|
dma_data->addr = (dma_addr_t)(mem->start + DAVINCI_MCBSP_DRR_REG); |
|
|
|
res = platform_get_resource(pdev, IORESOURCE_DMA, 1); |
|
if (res) { |
|
dma = &dev->dma_request[SNDRV_PCM_STREAM_CAPTURE]; |
|
*dma = res->start; |
|
dma_data->filter_data = dma; |
|
} else if (IS_ENABLED(CONFIG_OF) && pdev->dev.of_node) { |
|
dma_data->filter_data = "rx"; |
|
} else { |
|
dev_err(&pdev->dev, "Missing DMA rx resource\n"); |
|
return -ENODEV; |
|
} |
|
|
|
dev->clk = clk_get(&pdev->dev, NULL); |
|
if (IS_ERR(dev->clk)) |
|
return -ENODEV; |
|
clk_enable(dev->clk); |
|
|
|
dev->dev = &pdev->dev; |
|
dev_set_drvdata(&pdev->dev, dev); |
|
|
|
ret = snd_soc_register_component(&pdev->dev, &davinci_i2s_component, |
|
&davinci_i2s_dai, 1); |
|
if (ret != 0) |
|
goto err_release_clk; |
|
|
|
ret = edma_pcm_platform_register(&pdev->dev); |
|
if (ret) { |
|
dev_err(&pdev->dev, "register PCM failed: %d\n", ret); |
|
goto err_unregister_component; |
|
} |
|
|
|
return 0; |
|
|
|
err_unregister_component: |
|
snd_soc_unregister_component(&pdev->dev); |
|
err_release_clk: |
|
clk_disable(dev->clk); |
|
clk_put(dev->clk); |
|
return ret; |
|
} |
|
|
|
static int davinci_i2s_remove(struct platform_device *pdev) |
|
{ |
|
struct davinci_mcbsp_dev *dev = dev_get_drvdata(&pdev->dev); |
|
|
|
snd_soc_unregister_component(&pdev->dev); |
|
|
|
clk_disable(dev->clk); |
|
clk_put(dev->clk); |
|
dev->clk = NULL; |
|
|
|
return 0; |
|
} |
|
|
|
static const struct of_device_id davinci_i2s_match[] __maybe_unused = { |
|
{ .compatible = "ti,da850-mcbsp" }, |
|
{}, |
|
}; |
|
MODULE_DEVICE_TABLE(of, davinci_i2s_match); |
|
|
|
static struct platform_driver davinci_mcbsp_driver = { |
|
.probe = davinci_i2s_probe, |
|
.remove = davinci_i2s_remove, |
|
.driver = { |
|
.name = "davinci-mcbsp", |
|
.of_match_table = of_match_ptr(davinci_i2s_match), |
|
}, |
|
}; |
|
|
|
module_platform_driver(davinci_mcbsp_driver); |
|
|
|
MODULE_AUTHOR("Vladimir Barinov"); |
|
MODULE_DESCRIPTION("TI DAVINCI I2S (McBSP) SoC Interface"); |
|
MODULE_LICENSE("GPL");
|
|
|