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87 lines
2.1 KiB
87 lines
2.1 KiB
/* SPDX-License-Identifier: GPL-2.0-only */ |
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/* |
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* skl-i2s.h - i2s blob mapping |
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* |
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* Copyright (C) 2017 Intel Corp |
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* Author: Subhransu S. Prusty < [email protected]> |
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* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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* |
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* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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*/ |
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#ifndef __SOUND_SOC_SKL_I2S_H |
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#define __SOUND_SOC_SKL_I2S_H |
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#define SKL_I2S_MAX_TIME_SLOTS 8 |
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#define SKL_MCLK_DIV_CLK_SRC_MASK GENMASK(17, 16) |
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#define SKL_MNDSS_DIV_CLK_SRC_MASK GENMASK(21, 20) |
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#define SKL_SHIFT(x) (ffs(x) - 1) |
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#define SKL_MCLK_DIV_RATIO_MASK GENMASK(11, 0) |
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#define is_legacy_blob(x) (x.signature != 0xEE) |
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#define ext_to_legacy_blob(i2s_config_blob_ext) \ |
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((struct skl_i2s_config_blob_legacy *) i2s_config_blob_ext) |
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#define get_clk_src(mclk, mask) \ |
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((mclk.mdivctrl & mask) >> SKL_SHIFT(mask)) |
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struct skl_i2s_config { |
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u32 ssc0; |
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u32 ssc1; |
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u32 sscto; |
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u32 sspsp; |
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u32 sstsa; |
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u32 ssrsa; |
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u32 ssc2; |
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u32 sspsp2; |
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u32 ssc3; |
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u32 ssioc; |
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} __packed; |
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struct skl_i2s_config_mclk { |
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u32 mdivctrl; |
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u32 mdivr; |
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}; |
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struct skl_i2s_config_mclk_ext { |
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u32 mdivctrl; |
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u32 mdivr_count; |
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u32 mdivr[]; |
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} __packed; |
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struct skl_i2s_config_blob_signature { |
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u32 minor_ver : 8; |
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u32 major_ver : 8; |
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u32 resvdz : 8; |
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u32 signature : 8; |
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} __packed; |
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struct skl_i2s_config_blob_header { |
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struct skl_i2s_config_blob_signature sig; |
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u32 size; |
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}; |
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/** |
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* struct skl_i2s_config_blob_legacy - Structure defines I2S Gateway |
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* configuration legacy blob |
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* |
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* @gtw_attr: Gateway attribute for the I2S Gateway |
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* @tdm_ts_group: TDM slot mapping against channels in the Gateway. |
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* @i2s_cfg: I2S HW registers |
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* @mclk: MCLK clock source and divider values |
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*/ |
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struct skl_i2s_config_blob_legacy { |
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u32 gtw_attr; |
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u32 tdm_ts_group[SKL_I2S_MAX_TIME_SLOTS]; |
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struct skl_i2s_config i2s_cfg; |
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struct skl_i2s_config_mclk mclk; |
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}; |
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struct skl_i2s_config_blob_ext { |
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u32 gtw_attr; |
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struct skl_i2s_config_blob_header hdr; |
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u32 tdm_ts_group[SKL_I2S_MAX_TIME_SLOTS]; |
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struct skl_i2s_config i2s_cfg; |
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struct skl_i2s_config_mclk_ext mclk; |
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} __packed; |
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#endif /* __SOUND_SOC_SKL_I2S_H */
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