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250 lines
6.2 KiB
250 lines
6.2 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* Intel Smart Sound Technology (SST) DSP Core Driver |
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* |
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* Copyright (C) 2013, Intel Corporation. All rights reserved. |
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*/ |
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#include <linux/slab.h> |
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#include <linux/export.h> |
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#include <linux/interrupt.h> |
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#include <linux/module.h> |
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#include <linux/platform_device.h> |
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#include <linux/io-64-nonatomic-lo-hi.h> |
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#include <linux/delay.h> |
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#include "sst-dsp.h" |
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#include "sst-dsp-priv.h" |
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#define CREATE_TRACE_POINTS |
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#include <trace/events/intel-sst.h> |
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/* Internal generic low-level SST IO functions - can be overidden */ |
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void sst_shim32_write(void __iomem *addr, u32 offset, u32 value) |
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{ |
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writel(value, addr + offset); |
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} |
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EXPORT_SYMBOL_GPL(sst_shim32_write); |
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u32 sst_shim32_read(void __iomem *addr, u32 offset) |
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{ |
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return readl(addr + offset); |
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} |
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EXPORT_SYMBOL_GPL(sst_shim32_read); |
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void sst_shim32_write64(void __iomem *addr, u32 offset, u64 value) |
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{ |
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writeq(value, addr + offset); |
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} |
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EXPORT_SYMBOL_GPL(sst_shim32_write64); |
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u64 sst_shim32_read64(void __iomem *addr, u32 offset) |
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{ |
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return readq(addr + offset); |
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} |
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EXPORT_SYMBOL_GPL(sst_shim32_read64); |
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/* Public API */ |
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void sst_dsp_shim_write(struct sst_dsp *sst, u32 offset, u32 value) |
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{ |
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unsigned long flags; |
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spin_lock_irqsave(&sst->spinlock, flags); |
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sst->ops->write(sst->addr.shim, offset, value); |
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spin_unlock_irqrestore(&sst->spinlock, flags); |
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} |
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EXPORT_SYMBOL_GPL(sst_dsp_shim_write); |
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u32 sst_dsp_shim_read(struct sst_dsp *sst, u32 offset) |
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{ |
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unsigned long flags; |
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u32 val; |
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spin_lock_irqsave(&sst->spinlock, flags); |
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val = sst->ops->read(sst->addr.shim, offset); |
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spin_unlock_irqrestore(&sst->spinlock, flags); |
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return val; |
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} |
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EXPORT_SYMBOL_GPL(sst_dsp_shim_read); |
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void sst_dsp_shim_write_unlocked(struct sst_dsp *sst, u32 offset, u32 value) |
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{ |
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sst->ops->write(sst->addr.shim, offset, value); |
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} |
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EXPORT_SYMBOL_GPL(sst_dsp_shim_write_unlocked); |
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u32 sst_dsp_shim_read_unlocked(struct sst_dsp *sst, u32 offset) |
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{ |
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return sst->ops->read(sst->addr.shim, offset); |
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} |
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EXPORT_SYMBOL_GPL(sst_dsp_shim_read_unlocked); |
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int sst_dsp_shim_update_bits_unlocked(struct sst_dsp *sst, u32 offset, |
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u32 mask, u32 value) |
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{ |
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bool change; |
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unsigned int old, new; |
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u32 ret; |
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ret = sst_dsp_shim_read_unlocked(sst, offset); |
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old = ret; |
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new = (old & (~mask)) | (value & mask); |
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change = (old != new); |
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if (change) |
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sst_dsp_shim_write_unlocked(sst, offset, new); |
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return change; |
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} |
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EXPORT_SYMBOL_GPL(sst_dsp_shim_update_bits_unlocked); |
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/* This is for registers bits with attribute RWC */ |
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void sst_dsp_shim_update_bits_forced_unlocked(struct sst_dsp *sst, u32 offset, |
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u32 mask, u32 value) |
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{ |
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unsigned int old, new; |
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u32 ret; |
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ret = sst_dsp_shim_read_unlocked(sst, offset); |
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old = ret; |
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new = (old & (~mask)) | (value & mask); |
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sst_dsp_shim_write_unlocked(sst, offset, new); |
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} |
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EXPORT_SYMBOL_GPL(sst_dsp_shim_update_bits_forced_unlocked); |
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int sst_dsp_shim_update_bits(struct sst_dsp *sst, u32 offset, |
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u32 mask, u32 value) |
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{ |
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unsigned long flags; |
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bool change; |
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spin_lock_irqsave(&sst->spinlock, flags); |
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change = sst_dsp_shim_update_bits_unlocked(sst, offset, mask, value); |
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spin_unlock_irqrestore(&sst->spinlock, flags); |
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return change; |
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} |
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EXPORT_SYMBOL_GPL(sst_dsp_shim_update_bits); |
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/* This is for registers bits with attribute RWC */ |
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void sst_dsp_shim_update_bits_forced(struct sst_dsp *sst, u32 offset, |
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u32 mask, u32 value) |
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{ |
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unsigned long flags; |
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spin_lock_irqsave(&sst->spinlock, flags); |
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sst_dsp_shim_update_bits_forced_unlocked(sst, offset, mask, value); |
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spin_unlock_irqrestore(&sst->spinlock, flags); |
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} |
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EXPORT_SYMBOL_GPL(sst_dsp_shim_update_bits_forced); |
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int sst_dsp_register_poll(struct sst_dsp *ctx, u32 offset, u32 mask, |
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u32 target, u32 time, char *operation) |
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{ |
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u32 reg; |
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unsigned long timeout; |
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int k = 0, s = 500; |
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/* |
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* split the loop into sleeps of varying resolution. more accurately, |
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* the range of wakeups are: |
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* Phase 1(first 5ms): min sleep 0.5ms; max sleep 1ms. |
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* Phase 2:( 5ms to 10ms) : min sleep 0.5ms; max sleep 10ms |
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* (usleep_range (500, 1000) and usleep_range(5000, 10000) are |
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* both possible in this phase depending on whether k > 10 or not). |
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* Phase 3: (beyond 10 ms) min sleep 5ms; max sleep 10ms. |
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*/ |
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timeout = jiffies + msecs_to_jiffies(time); |
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while ((((reg = sst_dsp_shim_read_unlocked(ctx, offset)) & mask) != target) |
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&& time_before(jiffies, timeout)) { |
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k++; |
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if (k > 10) |
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s = 5000; |
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usleep_range(s, 2*s); |
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} |
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if ((reg & mask) == target) { |
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dev_dbg(ctx->dev, "FW Poll Status: reg=%#x %s successful\n", |
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reg, operation); |
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return 0; |
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} |
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dev_dbg(ctx->dev, "FW Poll Status: reg=%#x %s timedout\n", |
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reg, operation); |
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return -ETIME; |
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} |
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EXPORT_SYMBOL_GPL(sst_dsp_register_poll); |
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int sst_dsp_mailbox_init(struct sst_dsp *sst, u32 inbox_offset, size_t inbox_size, |
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u32 outbox_offset, size_t outbox_size) |
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{ |
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sst->mailbox.in_base = sst->addr.lpe + inbox_offset; |
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sst->mailbox.out_base = sst->addr.lpe + outbox_offset; |
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sst->mailbox.in_size = inbox_size; |
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sst->mailbox.out_size = outbox_size; |
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return 0; |
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} |
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EXPORT_SYMBOL_GPL(sst_dsp_mailbox_init); |
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void sst_dsp_outbox_write(struct sst_dsp *sst, void *message, size_t bytes) |
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{ |
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u32 i; |
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trace_sst_ipc_outbox_write(bytes); |
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memcpy_toio(sst->mailbox.out_base, message, bytes); |
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for (i = 0; i < bytes; i += 4) |
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trace_sst_ipc_outbox_wdata(i, *(u32 *)(message + i)); |
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} |
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EXPORT_SYMBOL_GPL(sst_dsp_outbox_write); |
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void sst_dsp_outbox_read(struct sst_dsp *sst, void *message, size_t bytes) |
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{ |
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u32 i; |
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trace_sst_ipc_outbox_read(bytes); |
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memcpy_fromio(message, sst->mailbox.out_base, bytes); |
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for (i = 0; i < bytes; i += 4) |
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trace_sst_ipc_outbox_rdata(i, *(u32 *)(message + i)); |
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} |
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EXPORT_SYMBOL_GPL(sst_dsp_outbox_read); |
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void sst_dsp_inbox_write(struct sst_dsp *sst, void *message, size_t bytes) |
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{ |
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u32 i; |
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trace_sst_ipc_inbox_write(bytes); |
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memcpy_toio(sst->mailbox.in_base, message, bytes); |
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for (i = 0; i < bytes; i += 4) |
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trace_sst_ipc_inbox_wdata(i, *(u32 *)(message + i)); |
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} |
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EXPORT_SYMBOL_GPL(sst_dsp_inbox_write); |
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void sst_dsp_inbox_read(struct sst_dsp *sst, void *message, size_t bytes) |
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{ |
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u32 i; |
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trace_sst_ipc_inbox_read(bytes); |
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memcpy_fromio(message, sst->mailbox.in_base, bytes); |
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for (i = 0; i < bytes; i += 4) |
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trace_sst_ipc_inbox_rdata(i, *(u32 *)(message + i)); |
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} |
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EXPORT_SYMBOL_GPL(sst_dsp_inbox_read); |
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/* Module information */ |
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MODULE_AUTHOR("Liam Girdwood"); |
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MODULE_DESCRIPTION("Intel SST Core"); |
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MODULE_LICENSE("GPL v2");
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