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811 lines
20 KiB
811 lines
20 KiB
// SPDX-License-Identifier: GPL-2.0 |
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// Copyright 2018 NXP |
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#include <linux/clk.h> |
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#include <linux/device.h> |
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#include <linux/interrupt.h> |
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#include <linux/kobject.h> |
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#include <linux/kernel.h> |
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#include <linux/module.h> |
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#include <linux/of.h> |
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#include <linux/of_address.h> |
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#include <linux/of_irq.h> |
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#include <linux/of_platform.h> |
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#include <linux/pm_runtime.h> |
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#include <linux/regmap.h> |
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#include <linux/sysfs.h> |
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#include <linux/types.h> |
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#include <sound/dmaengine_pcm.h> |
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#include <sound/pcm.h> |
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#include <sound/soc.h> |
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#include <sound/tlv.h> |
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#include <sound/core.h> |
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#include "fsl_micfil.h" |
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#include "imx-pcm.h" |
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|
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#define FSL_MICFIL_RATES SNDRV_PCM_RATE_8000_48000 |
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#define FSL_MICFIL_FORMATS (SNDRV_PCM_FMTBIT_S16_LE) |
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struct fsl_micfil { |
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struct platform_device *pdev; |
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struct regmap *regmap; |
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const struct fsl_micfil_soc_data *soc; |
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struct clk *mclk; |
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struct snd_dmaengine_dai_dma_data dma_params_rx; |
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unsigned int dataline; |
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char name[32]; |
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int irq[MICFIL_IRQ_LINES]; |
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unsigned int mclk_streams; |
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int quality; /*QUALITY 2-0 bits */ |
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bool slave_mode; |
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int channel_gain[8]; |
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}; |
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struct fsl_micfil_soc_data { |
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unsigned int fifos; |
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unsigned int fifo_depth; |
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unsigned int dataline; |
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bool imx; |
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}; |
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static struct fsl_micfil_soc_data fsl_micfil_imx8mm = { |
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.imx = true, |
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.fifos = 8, |
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.fifo_depth = 8, |
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.dataline = 0xf, |
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}; |
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static const struct of_device_id fsl_micfil_dt_ids[] = { |
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{ .compatible = "fsl,imx8mm-micfil", .data = &fsl_micfil_imx8mm }, |
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{} |
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}; |
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MODULE_DEVICE_TABLE(of, fsl_micfil_dt_ids); |
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|
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/* Table 5. Quality Modes |
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* Medium 0 0 0 |
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* High 0 0 1 |
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* Very Low 2 1 0 0 |
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* Very Low 1 1 0 1 |
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* Very Low 0 1 1 0 |
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* Low 1 1 1 |
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*/ |
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static const char * const micfil_quality_select_texts[] = { |
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"Medium", "High", |
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"N/A", "N/A", |
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"VLow2", "VLow1", |
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"VLow0", "Low", |
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}; |
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static const struct soc_enum fsl_micfil_quality_enum = |
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SOC_ENUM_SINGLE(REG_MICFIL_CTRL2, |
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MICFIL_CTRL2_QSEL_SHIFT, |
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ARRAY_SIZE(micfil_quality_select_texts), |
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micfil_quality_select_texts); |
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static DECLARE_TLV_DB_SCALE(gain_tlv, 0, 100, 0); |
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static const struct snd_kcontrol_new fsl_micfil_snd_controls[] = { |
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SOC_SINGLE_SX_TLV("CH0 Volume", REG_MICFIL_OUT_CTRL, |
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MICFIL_OUTGAIN_CHX_SHIFT(0), 0xF, 0x7, gain_tlv), |
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SOC_SINGLE_SX_TLV("CH1 Volume", REG_MICFIL_OUT_CTRL, |
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MICFIL_OUTGAIN_CHX_SHIFT(1), 0xF, 0x7, gain_tlv), |
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SOC_SINGLE_SX_TLV("CH2 Volume", REG_MICFIL_OUT_CTRL, |
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MICFIL_OUTGAIN_CHX_SHIFT(2), 0xF, 0x7, gain_tlv), |
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SOC_SINGLE_SX_TLV("CH3 Volume", REG_MICFIL_OUT_CTRL, |
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MICFIL_OUTGAIN_CHX_SHIFT(3), 0xF, 0x7, gain_tlv), |
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SOC_SINGLE_SX_TLV("CH4 Volume", REG_MICFIL_OUT_CTRL, |
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MICFIL_OUTGAIN_CHX_SHIFT(4), 0xF, 0x7, gain_tlv), |
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SOC_SINGLE_SX_TLV("CH5 Volume", REG_MICFIL_OUT_CTRL, |
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MICFIL_OUTGAIN_CHX_SHIFT(5), 0xF, 0x7, gain_tlv), |
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SOC_SINGLE_SX_TLV("CH6 Volume", REG_MICFIL_OUT_CTRL, |
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MICFIL_OUTGAIN_CHX_SHIFT(6), 0xF, 0x7, gain_tlv), |
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SOC_SINGLE_SX_TLV("CH7 Volume", REG_MICFIL_OUT_CTRL, |
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MICFIL_OUTGAIN_CHX_SHIFT(7), 0xF, 0x7, gain_tlv), |
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SOC_ENUM_EXT("MICFIL Quality Select", |
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fsl_micfil_quality_enum, |
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snd_soc_get_enum_double, snd_soc_put_enum_double), |
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}; |
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static inline int get_pdm_clk(struct fsl_micfil *micfil, |
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unsigned int rate) |
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{ |
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u32 ctrl2_reg; |
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int qsel, osr; |
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int bclk; |
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regmap_read(micfil->regmap, REG_MICFIL_CTRL2, &ctrl2_reg); |
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osr = 16 - ((ctrl2_reg & MICFIL_CTRL2_CICOSR_MASK) |
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>> MICFIL_CTRL2_CICOSR_SHIFT); |
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regmap_read(micfil->regmap, REG_MICFIL_CTRL2, &ctrl2_reg); |
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qsel = ctrl2_reg & MICFIL_CTRL2_QSEL_MASK; |
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switch (qsel) { |
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case MICFIL_HIGH_QUALITY: |
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bclk = rate * 8 * osr / 2; /* kfactor = 0.5 */ |
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break; |
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case MICFIL_MEDIUM_QUALITY: |
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case MICFIL_VLOW0_QUALITY: |
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bclk = rate * 4 * osr * 1; /* kfactor = 1 */ |
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break; |
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case MICFIL_LOW_QUALITY: |
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case MICFIL_VLOW1_QUALITY: |
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bclk = rate * 2 * osr * 2; /* kfactor = 2 */ |
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break; |
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case MICFIL_VLOW2_QUALITY: |
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bclk = rate * osr * 4; /* kfactor = 4 */ |
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break; |
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default: |
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dev_err(&micfil->pdev->dev, |
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"Please make sure you select a valid quality.\n"); |
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bclk = -1; |
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break; |
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} |
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return bclk; |
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} |
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static inline int get_clk_div(struct fsl_micfil *micfil, |
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unsigned int rate) |
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{ |
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u32 ctrl2_reg; |
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long mclk_rate; |
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int clk_div; |
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regmap_read(micfil->regmap, REG_MICFIL_CTRL2, &ctrl2_reg); |
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mclk_rate = clk_get_rate(micfil->mclk); |
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clk_div = mclk_rate / (get_pdm_clk(micfil, rate) * 2); |
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return clk_div; |
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} |
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/* The SRES is a self-negated bit which provides the CPU with the |
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* capability to initialize the PDM Interface module through the |
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* slave-bus interface. This bit always reads as zero, and this |
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* bit is only effective when MDIS is cleared |
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*/ |
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static int fsl_micfil_reset(struct device *dev) |
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{ |
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struct fsl_micfil *micfil = dev_get_drvdata(dev); |
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int ret; |
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ret = regmap_update_bits(micfil->regmap, |
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REG_MICFIL_CTRL1, |
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MICFIL_CTRL1_MDIS_MASK, |
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0); |
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if (ret) { |
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dev_err(dev, "failed to clear MDIS bit %d\n", ret); |
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return ret; |
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} |
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ret = regmap_update_bits(micfil->regmap, |
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REG_MICFIL_CTRL1, |
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MICFIL_CTRL1_SRES_MASK, |
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MICFIL_CTRL1_SRES); |
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if (ret) { |
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dev_err(dev, "failed to reset MICFIL: %d\n", ret); |
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return ret; |
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} |
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return 0; |
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} |
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static int fsl_micfil_set_mclk_rate(struct fsl_micfil *micfil, |
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unsigned int freq) |
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{ |
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struct device *dev = &micfil->pdev->dev; |
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int ret; |
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clk_disable_unprepare(micfil->mclk); |
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ret = clk_set_rate(micfil->mclk, freq * 1024); |
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if (ret) |
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dev_warn(dev, "failed to set rate (%u): %d\n", |
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freq * 1024, ret); |
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clk_prepare_enable(micfil->mclk); |
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return ret; |
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} |
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static int fsl_micfil_startup(struct snd_pcm_substream *substream, |
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struct snd_soc_dai *dai) |
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{ |
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struct fsl_micfil *micfil = snd_soc_dai_get_drvdata(dai); |
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if (!micfil) { |
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dev_err(dai->dev, "micfil dai priv_data not set\n"); |
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return -EINVAL; |
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} |
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return 0; |
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} |
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static int fsl_micfil_trigger(struct snd_pcm_substream *substream, int cmd, |
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struct snd_soc_dai *dai) |
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{ |
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struct fsl_micfil *micfil = snd_soc_dai_get_drvdata(dai); |
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struct device *dev = &micfil->pdev->dev; |
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int ret; |
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switch (cmd) { |
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case SNDRV_PCM_TRIGGER_START: |
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case SNDRV_PCM_TRIGGER_RESUME: |
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case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: |
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ret = fsl_micfil_reset(dev); |
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if (ret) { |
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dev_err(dev, "failed to soft reset\n"); |
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return ret; |
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} |
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/* DMA Interrupt Selection - DISEL bits |
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* 00 - DMA and IRQ disabled |
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* 01 - DMA req enabled |
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* 10 - IRQ enabled |
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* 11 - reserved |
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*/ |
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ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1, |
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MICFIL_CTRL1_DISEL_MASK, |
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(1 << MICFIL_CTRL1_DISEL_SHIFT)); |
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if (ret) { |
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dev_err(dev, "failed to update DISEL bits\n"); |
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return ret; |
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} |
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/* Enable the module */ |
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ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1, |
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MICFIL_CTRL1_PDMIEN_MASK, |
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MICFIL_CTRL1_PDMIEN); |
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if (ret) { |
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dev_err(dev, "failed to enable the module\n"); |
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return ret; |
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} |
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break; |
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case SNDRV_PCM_TRIGGER_STOP: |
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case SNDRV_PCM_TRIGGER_SUSPEND: |
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case SNDRV_PCM_TRIGGER_PAUSE_PUSH: |
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/* Disable the module */ |
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ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1, |
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MICFIL_CTRL1_PDMIEN_MASK, |
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0); |
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if (ret) { |
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dev_err(dev, "failed to enable the module\n"); |
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return ret; |
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} |
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ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1, |
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MICFIL_CTRL1_DISEL_MASK, |
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(0 << MICFIL_CTRL1_DISEL_SHIFT)); |
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if (ret) { |
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dev_err(dev, "failed to update DISEL bits\n"); |
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return ret; |
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} |
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break; |
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default: |
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return -EINVAL; |
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} |
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return 0; |
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} |
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static int fsl_set_clock_params(struct device *dev, unsigned int rate) |
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{ |
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struct fsl_micfil *micfil = dev_get_drvdata(dev); |
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int clk_div; |
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int ret; |
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ret = fsl_micfil_set_mclk_rate(micfil, rate); |
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if (ret < 0) |
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dev_err(dev, "failed to set mclk[%lu] to rate %u\n", |
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clk_get_rate(micfil->mclk), rate); |
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/* set CICOSR */ |
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ret |= regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL2, |
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MICFIL_CTRL2_CICOSR_MASK, |
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MICFIL_CTRL2_OSR_DEFAULT); |
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if (ret) |
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dev_err(dev, "failed to set CICOSR in reg 0x%X\n", |
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REG_MICFIL_CTRL2); |
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/* set CLK_DIV */ |
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clk_div = get_clk_div(micfil, rate); |
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if (clk_div < 0) |
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ret = -EINVAL; |
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ret |= regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL2, |
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MICFIL_CTRL2_CLKDIV_MASK, clk_div); |
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if (ret) |
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dev_err(dev, "failed to set CLKDIV in reg 0x%X\n", |
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REG_MICFIL_CTRL2); |
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return ret; |
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} |
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static int fsl_micfil_hw_params(struct snd_pcm_substream *substream, |
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struct snd_pcm_hw_params *params, |
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struct snd_soc_dai *dai) |
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{ |
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struct fsl_micfil *micfil = snd_soc_dai_get_drvdata(dai); |
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unsigned int channels = params_channels(params); |
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unsigned int rate = params_rate(params); |
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struct device *dev = &micfil->pdev->dev; |
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int ret; |
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/* 1. Disable the module */ |
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ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1, |
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MICFIL_CTRL1_PDMIEN_MASK, 0); |
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if (ret) { |
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dev_err(dev, "failed to disable the module\n"); |
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return ret; |
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} |
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/* enable channels */ |
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ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1, |
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0xFF, ((1 << channels) - 1)); |
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if (ret) { |
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dev_err(dev, "failed to enable channels %d, reg 0x%X\n", ret, |
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REG_MICFIL_CTRL1); |
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return ret; |
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} |
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ret = fsl_set_clock_params(dev, rate); |
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if (ret < 0) { |
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dev_err(dev, "Failed to set clock parameters [%d]\n", ret); |
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return ret; |
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} |
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micfil->dma_params_rx.maxburst = channels * MICFIL_DMA_MAXBURST_RX; |
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return 0; |
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} |
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static int fsl_micfil_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id, |
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unsigned int freq, int dir) |
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{ |
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struct fsl_micfil *micfil = snd_soc_dai_get_drvdata(dai); |
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struct device *dev = &micfil->pdev->dev; |
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int ret; |
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if (!freq) |
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return 0; |
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ret = fsl_micfil_set_mclk_rate(micfil, freq); |
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if (ret < 0) |
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dev_err(dev, "failed to set mclk[%lu] to rate %u\n", |
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clk_get_rate(micfil->mclk), freq); |
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return ret; |
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} |
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static const struct snd_soc_dai_ops fsl_micfil_dai_ops = { |
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.startup = fsl_micfil_startup, |
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.trigger = fsl_micfil_trigger, |
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.hw_params = fsl_micfil_hw_params, |
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.set_sysclk = fsl_micfil_set_dai_sysclk, |
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}; |
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static int fsl_micfil_dai_probe(struct snd_soc_dai *cpu_dai) |
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{ |
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struct fsl_micfil *micfil = dev_get_drvdata(cpu_dai->dev); |
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struct device *dev = cpu_dai->dev; |
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unsigned int val; |
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int ret; |
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int i; |
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/* set qsel to medium */ |
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ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL2, |
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MICFIL_CTRL2_QSEL_MASK, MICFIL_MEDIUM_QUALITY); |
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if (ret) { |
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dev_err(dev, "failed to set quality mode bits, reg 0x%X\n", |
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REG_MICFIL_CTRL2); |
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return ret; |
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} |
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|
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/* set default gain to max_gain */ |
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regmap_write(micfil->regmap, REG_MICFIL_OUT_CTRL, 0x77777777); |
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for (i = 0; i < 8; i++) |
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micfil->channel_gain[i] = 0xF; |
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snd_soc_dai_init_dma_data(cpu_dai, NULL, |
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&micfil->dma_params_rx); |
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/* FIFO Watermark Control - FIFOWMK*/ |
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val = MICFIL_FIFO_CTRL_FIFOWMK(micfil->soc->fifo_depth) - 1; |
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ret = regmap_update_bits(micfil->regmap, REG_MICFIL_FIFO_CTRL, |
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MICFIL_FIFO_CTRL_FIFOWMK_MASK, |
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val); |
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if (ret) { |
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dev_err(dev, "failed to set FIFOWMK\n"); |
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return ret; |
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} |
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snd_soc_dai_set_drvdata(cpu_dai, micfil); |
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|
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return 0; |
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} |
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static struct snd_soc_dai_driver fsl_micfil_dai = { |
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.probe = fsl_micfil_dai_probe, |
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.capture = { |
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.stream_name = "CPU-Capture", |
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.channels_min = 1, |
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.channels_max = 8, |
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.rates = FSL_MICFIL_RATES, |
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.formats = FSL_MICFIL_FORMATS, |
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}, |
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.ops = &fsl_micfil_dai_ops, |
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}; |
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|
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static const struct snd_soc_component_driver fsl_micfil_component = { |
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.name = "fsl-micfil-dai", |
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.controls = fsl_micfil_snd_controls, |
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.num_controls = ARRAY_SIZE(fsl_micfil_snd_controls), |
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|
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}; |
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|
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/* REGMAP */ |
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static const struct reg_default fsl_micfil_reg_defaults[] = { |
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{REG_MICFIL_CTRL1, 0x00000000}, |
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{REG_MICFIL_CTRL2, 0x00000000}, |
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{REG_MICFIL_STAT, 0x00000000}, |
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{REG_MICFIL_FIFO_CTRL, 0x00000007}, |
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{REG_MICFIL_FIFO_STAT, 0x00000000}, |
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{REG_MICFIL_DATACH0, 0x00000000}, |
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{REG_MICFIL_DATACH1, 0x00000000}, |
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{REG_MICFIL_DATACH2, 0x00000000}, |
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{REG_MICFIL_DATACH3, 0x00000000}, |
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{REG_MICFIL_DATACH4, 0x00000000}, |
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{REG_MICFIL_DATACH5, 0x00000000}, |
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{REG_MICFIL_DATACH6, 0x00000000}, |
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{REG_MICFIL_DATACH7, 0x00000000}, |
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{REG_MICFIL_DC_CTRL, 0x00000000}, |
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{REG_MICFIL_OUT_CTRL, 0x00000000}, |
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{REG_MICFIL_OUT_STAT, 0x00000000}, |
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{REG_MICFIL_VAD0_CTRL1, 0x00000000}, |
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{REG_MICFIL_VAD0_CTRL2, 0x000A0000}, |
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{REG_MICFIL_VAD0_STAT, 0x00000000}, |
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{REG_MICFIL_VAD0_SCONFIG, 0x00000000}, |
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{REG_MICFIL_VAD0_NCONFIG, 0x80000000}, |
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{REG_MICFIL_VAD0_NDATA, 0x00000000}, |
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{REG_MICFIL_VAD0_ZCD, 0x00000004}, |
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}; |
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|
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static bool fsl_micfil_readable_reg(struct device *dev, unsigned int reg) |
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{ |
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switch (reg) { |
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case REG_MICFIL_CTRL1: |
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case REG_MICFIL_CTRL2: |
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case REG_MICFIL_STAT: |
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case REG_MICFIL_FIFO_CTRL: |
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case REG_MICFIL_FIFO_STAT: |
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case REG_MICFIL_DATACH0: |
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case REG_MICFIL_DATACH1: |
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case REG_MICFIL_DATACH2: |
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case REG_MICFIL_DATACH3: |
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case REG_MICFIL_DATACH4: |
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case REG_MICFIL_DATACH5: |
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case REG_MICFIL_DATACH6: |
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case REG_MICFIL_DATACH7: |
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case REG_MICFIL_DC_CTRL: |
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case REG_MICFIL_OUT_CTRL: |
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case REG_MICFIL_OUT_STAT: |
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case REG_MICFIL_VAD0_CTRL1: |
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case REG_MICFIL_VAD0_CTRL2: |
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case REG_MICFIL_VAD0_STAT: |
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case REG_MICFIL_VAD0_SCONFIG: |
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case REG_MICFIL_VAD0_NCONFIG: |
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case REG_MICFIL_VAD0_NDATA: |
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case REG_MICFIL_VAD0_ZCD: |
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return true; |
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default: |
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return false; |
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} |
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} |
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|
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static bool fsl_micfil_writeable_reg(struct device *dev, unsigned int reg) |
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{ |
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switch (reg) { |
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case REG_MICFIL_CTRL1: |
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case REG_MICFIL_CTRL2: |
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case REG_MICFIL_STAT: /* Write 1 to Clear */ |
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case REG_MICFIL_FIFO_CTRL: |
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case REG_MICFIL_FIFO_STAT: /* Write 1 to Clear */ |
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case REG_MICFIL_DC_CTRL: |
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case REG_MICFIL_OUT_CTRL: |
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case REG_MICFIL_OUT_STAT: /* Write 1 to Clear */ |
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case REG_MICFIL_VAD0_CTRL1: |
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case REG_MICFIL_VAD0_CTRL2: |
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case REG_MICFIL_VAD0_STAT: /* Write 1 to Clear */ |
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case REG_MICFIL_VAD0_SCONFIG: |
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case REG_MICFIL_VAD0_NCONFIG: |
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case REG_MICFIL_VAD0_ZCD: |
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return true; |
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default: |
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return false; |
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} |
|
} |
|
|
|
static bool fsl_micfil_volatile_reg(struct device *dev, unsigned int reg) |
|
{ |
|
switch (reg) { |
|
case REG_MICFIL_STAT: |
|
case REG_MICFIL_DATACH0: |
|
case REG_MICFIL_DATACH1: |
|
case REG_MICFIL_DATACH2: |
|
case REG_MICFIL_DATACH3: |
|
case REG_MICFIL_DATACH4: |
|
case REG_MICFIL_DATACH5: |
|
case REG_MICFIL_DATACH6: |
|
case REG_MICFIL_DATACH7: |
|
case REG_MICFIL_VAD0_STAT: |
|
case REG_MICFIL_VAD0_NDATA: |
|
return true; |
|
default: |
|
return false; |
|
} |
|
} |
|
|
|
static const struct regmap_config fsl_micfil_regmap_config = { |
|
.reg_bits = 32, |
|
.reg_stride = 4, |
|
.val_bits = 32, |
|
|
|
.max_register = REG_MICFIL_VAD0_ZCD, |
|
.reg_defaults = fsl_micfil_reg_defaults, |
|
.num_reg_defaults = ARRAY_SIZE(fsl_micfil_reg_defaults), |
|
.readable_reg = fsl_micfil_readable_reg, |
|
.volatile_reg = fsl_micfil_volatile_reg, |
|
.writeable_reg = fsl_micfil_writeable_reg, |
|
.cache_type = REGCACHE_RBTREE, |
|
}; |
|
|
|
/* END OF REGMAP */ |
|
|
|
static irqreturn_t micfil_isr(int irq, void *devid) |
|
{ |
|
struct fsl_micfil *micfil = (struct fsl_micfil *)devid; |
|
struct platform_device *pdev = micfil->pdev; |
|
u32 stat_reg; |
|
u32 fifo_stat_reg; |
|
u32 ctrl1_reg; |
|
bool dma_enabled; |
|
int i; |
|
|
|
regmap_read(micfil->regmap, REG_MICFIL_STAT, &stat_reg); |
|
regmap_read(micfil->regmap, REG_MICFIL_CTRL1, &ctrl1_reg); |
|
regmap_read(micfil->regmap, REG_MICFIL_FIFO_STAT, &fifo_stat_reg); |
|
|
|
dma_enabled = MICFIL_DMA_ENABLED(ctrl1_reg); |
|
|
|
/* Channel 0-7 Output Data Flags */ |
|
for (i = 0; i < MICFIL_OUTPUT_CHANNELS; i++) { |
|
if (stat_reg & MICFIL_STAT_CHXF_MASK(i)) |
|
dev_dbg(&pdev->dev, |
|
"Data available in Data Channel %d\n", i); |
|
/* if DMA is not enabled, field must be written with 1 |
|
* to clear |
|
*/ |
|
if (!dma_enabled) |
|
regmap_write_bits(micfil->regmap, |
|
REG_MICFIL_STAT, |
|
MICFIL_STAT_CHXF_MASK(i), |
|
1); |
|
} |
|
|
|
for (i = 0; i < MICFIL_FIFO_NUM; i++) { |
|
if (fifo_stat_reg & MICFIL_FIFO_STAT_FIFOX_OVER_MASK(i)) |
|
dev_dbg(&pdev->dev, |
|
"FIFO Overflow Exception flag for channel %d\n", |
|
i); |
|
|
|
if (fifo_stat_reg & MICFIL_FIFO_STAT_FIFOX_UNDER_MASK(i)) |
|
dev_dbg(&pdev->dev, |
|
"FIFO Underflow Exception flag for channel %d\n", |
|
i); |
|
} |
|
|
|
return IRQ_HANDLED; |
|
} |
|
|
|
static irqreturn_t micfil_err_isr(int irq, void *devid) |
|
{ |
|
struct fsl_micfil *micfil = (struct fsl_micfil *)devid; |
|
struct platform_device *pdev = micfil->pdev; |
|
u32 stat_reg; |
|
|
|
regmap_read(micfil->regmap, REG_MICFIL_STAT, &stat_reg); |
|
|
|
if (stat_reg & MICFIL_STAT_BSY_FIL_MASK) |
|
dev_dbg(&pdev->dev, "isr: Decimation Filter is running\n"); |
|
|
|
if (stat_reg & MICFIL_STAT_FIR_RDY_MASK) |
|
dev_dbg(&pdev->dev, "isr: FIR Filter Data ready\n"); |
|
|
|
if (stat_reg & MICFIL_STAT_LOWFREQF_MASK) { |
|
dev_dbg(&pdev->dev, "isr: ipg_clk_app is too low\n"); |
|
regmap_write_bits(micfil->regmap, REG_MICFIL_STAT, |
|
MICFIL_STAT_LOWFREQF_MASK, 1); |
|
} |
|
|
|
return IRQ_HANDLED; |
|
} |
|
|
|
static int fsl_micfil_probe(struct platform_device *pdev) |
|
{ |
|
struct device_node *np = pdev->dev.of_node; |
|
struct fsl_micfil *micfil; |
|
struct resource *res; |
|
void __iomem *regs; |
|
int ret, i; |
|
unsigned long irqflag = 0; |
|
|
|
micfil = devm_kzalloc(&pdev->dev, sizeof(*micfil), GFP_KERNEL); |
|
if (!micfil) |
|
return -ENOMEM; |
|
|
|
micfil->pdev = pdev; |
|
strncpy(micfil->name, np->name, sizeof(micfil->name) - 1); |
|
|
|
micfil->soc = of_device_get_match_data(&pdev->dev); |
|
|
|
/* ipg_clk is used to control the registers |
|
* ipg_clk_app is used to operate the filter |
|
*/ |
|
micfil->mclk = devm_clk_get(&pdev->dev, "ipg_clk_app"); |
|
if (IS_ERR(micfil->mclk)) { |
|
dev_err(&pdev->dev, "failed to get core clock: %ld\n", |
|
PTR_ERR(micfil->mclk)); |
|
return PTR_ERR(micfil->mclk); |
|
} |
|
|
|
/* init regmap */ |
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
|
regs = devm_ioremap_resource(&pdev->dev, res); |
|
if (IS_ERR(regs)) |
|
return PTR_ERR(regs); |
|
|
|
micfil->regmap = devm_regmap_init_mmio_clk(&pdev->dev, |
|
"ipg_clk", |
|
regs, |
|
&fsl_micfil_regmap_config); |
|
if (IS_ERR(micfil->regmap)) { |
|
dev_err(&pdev->dev, "failed to init MICFIL regmap: %ld\n", |
|
PTR_ERR(micfil->regmap)); |
|
return PTR_ERR(micfil->regmap); |
|
} |
|
|
|
/* dataline mask for RX */ |
|
ret = of_property_read_u32_index(np, |
|
"fsl,dataline", |
|
0, |
|
&micfil->dataline); |
|
if (ret) |
|
micfil->dataline = 1; |
|
|
|
if (micfil->dataline & ~micfil->soc->dataline) { |
|
dev_err(&pdev->dev, "dataline setting error, Mask is 0x%X\n", |
|
micfil->soc->dataline); |
|
return -EINVAL; |
|
} |
|
|
|
/* get IRQs */ |
|
for (i = 0; i < MICFIL_IRQ_LINES; i++) { |
|
micfil->irq[i] = platform_get_irq(pdev, i); |
|
dev_err(&pdev->dev, "GET IRQ: %d\n", micfil->irq[i]); |
|
if (micfil->irq[i] < 0) |
|
return micfil->irq[i]; |
|
} |
|
|
|
if (of_property_read_bool(np, "fsl,shared-interrupt")) |
|
irqflag = IRQF_SHARED; |
|
|
|
/* Digital Microphone interface interrupt */ |
|
ret = devm_request_irq(&pdev->dev, micfil->irq[0], |
|
micfil_isr, irqflag, |
|
micfil->name, micfil); |
|
if (ret) { |
|
dev_err(&pdev->dev, "failed to claim mic interface irq %u\n", |
|
micfil->irq[0]); |
|
return ret; |
|
} |
|
|
|
/* Digital Microphone interface error interrupt */ |
|
ret = devm_request_irq(&pdev->dev, micfil->irq[1], |
|
micfil_err_isr, irqflag, |
|
micfil->name, micfil); |
|
if (ret) { |
|
dev_err(&pdev->dev, "failed to claim mic interface error irq %u\n", |
|
micfil->irq[1]); |
|
return ret; |
|
} |
|
|
|
micfil->dma_params_rx.chan_name = "rx"; |
|
micfil->dma_params_rx.addr = res->start + REG_MICFIL_DATACH0; |
|
micfil->dma_params_rx.maxburst = MICFIL_DMA_MAXBURST_RX; |
|
|
|
|
|
platform_set_drvdata(pdev, micfil); |
|
|
|
pm_runtime_enable(&pdev->dev); |
|
|
|
ret = devm_snd_soc_register_component(&pdev->dev, &fsl_micfil_component, |
|
&fsl_micfil_dai, 1); |
|
if (ret) { |
|
dev_err(&pdev->dev, "failed to register component %s\n", |
|
fsl_micfil_component.name); |
|
return ret; |
|
} |
|
|
|
ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0); |
|
if (ret) |
|
dev_err(&pdev->dev, "failed to pcm register\n"); |
|
|
|
return ret; |
|
} |
|
|
|
static int __maybe_unused fsl_micfil_runtime_suspend(struct device *dev) |
|
{ |
|
struct fsl_micfil *micfil = dev_get_drvdata(dev); |
|
|
|
regcache_cache_only(micfil->regmap, true); |
|
|
|
clk_disable_unprepare(micfil->mclk); |
|
|
|
return 0; |
|
} |
|
|
|
static int __maybe_unused fsl_micfil_runtime_resume(struct device *dev) |
|
{ |
|
struct fsl_micfil *micfil = dev_get_drvdata(dev); |
|
int ret; |
|
|
|
ret = clk_prepare_enable(micfil->mclk); |
|
if (ret < 0) |
|
return ret; |
|
|
|
regcache_cache_only(micfil->regmap, false); |
|
regcache_mark_dirty(micfil->regmap); |
|
regcache_sync(micfil->regmap); |
|
|
|
return 0; |
|
} |
|
|
|
static int __maybe_unused fsl_micfil_suspend(struct device *dev) |
|
{ |
|
pm_runtime_force_suspend(dev); |
|
|
|
return 0; |
|
} |
|
|
|
static int __maybe_unused fsl_micfil_resume(struct device *dev) |
|
{ |
|
pm_runtime_force_resume(dev); |
|
|
|
return 0; |
|
} |
|
|
|
static const struct dev_pm_ops fsl_micfil_pm_ops = { |
|
SET_RUNTIME_PM_OPS(fsl_micfil_runtime_suspend, |
|
fsl_micfil_runtime_resume, |
|
NULL) |
|
SET_SYSTEM_SLEEP_PM_OPS(fsl_micfil_suspend, |
|
fsl_micfil_resume) |
|
}; |
|
|
|
static struct platform_driver fsl_micfil_driver = { |
|
.probe = fsl_micfil_probe, |
|
.driver = { |
|
.name = "fsl-micfil-dai", |
|
.pm = &fsl_micfil_pm_ops, |
|
.of_match_table = fsl_micfil_dt_ids, |
|
}, |
|
}; |
|
module_platform_driver(fsl_micfil_driver); |
|
|
|
MODULE_AUTHOR("Cosmin-Gabriel Samoila <[email protected]>"); |
|
MODULE_DESCRIPTION("NXP PDM Microphone Interface (MICFIL) driver"); |
|
MODULE_LICENSE("GPL v2");
|
|
|