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560 lines
14 KiB
560 lines
14 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* |
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* Implementation of primary ALSA driver code base for NVIDIA Tegra HDA. |
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*/ |
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#include <linux/clk.h> |
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#include <linux/clocksource.h> |
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#include <linux/completion.h> |
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#include <linux/delay.h> |
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#include <linux/dma-mapping.h> |
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#include <linux/init.h> |
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#include <linux/interrupt.h> |
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#include <linux/io.h> |
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#include <linux/kernel.h> |
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#include <linux/module.h> |
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#include <linux/moduleparam.h> |
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#include <linux/mutex.h> |
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#include <linux/of_device.h> |
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#include <linux/reset.h> |
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#include <linux/slab.h> |
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#include <linux/time.h> |
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#include <linux/string.h> |
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#include <linux/pm_runtime.h> |
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#include <sound/core.h> |
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#include <sound/initval.h> |
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#include <sound/hda_codec.h> |
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#include "hda_controller.h" |
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/* Defines for Nvidia Tegra HDA support */ |
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#define HDA_BAR0 0x8000 |
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#define HDA_CFG_CMD 0x1004 |
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#define HDA_CFG_BAR0 0x1010 |
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#define HDA_ENABLE_IO_SPACE (1 << 0) |
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#define HDA_ENABLE_MEM_SPACE (1 << 1) |
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#define HDA_ENABLE_BUS_MASTER (1 << 2) |
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#define HDA_ENABLE_SERR (1 << 8) |
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#define HDA_DISABLE_INTR (1 << 10) |
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#define HDA_BAR0_INIT_PROGRAM 0xFFFFFFFF |
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#define HDA_BAR0_FINAL_PROGRAM (1 << 14) |
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/* IPFS */ |
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#define HDA_IPFS_CONFIG 0x180 |
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#define HDA_IPFS_EN_FPCI 0x1 |
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#define HDA_IPFS_FPCI_BAR0 0x80 |
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#define HDA_FPCI_BAR0_START 0x40 |
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#define HDA_IPFS_INTR_MASK 0x188 |
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#define HDA_IPFS_EN_INTR (1 << 16) |
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/* FPCI */ |
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#define FPCI_DBG_CFG_2 0x10F4 |
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#define FPCI_GCAP_NSDO_SHIFT 18 |
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#define FPCI_GCAP_NSDO_MASK (0x3 << FPCI_GCAP_NSDO_SHIFT) |
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/* max number of SDs */ |
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#define NUM_CAPTURE_SD 1 |
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#define NUM_PLAYBACK_SD 1 |
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/* |
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* Tegra194 does not reflect correct number of SDO lines. Below macro |
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* is used to update the GCAP register to workaround the issue. |
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*/ |
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#define TEGRA194_NUM_SDO_LINES 4 |
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struct hda_tegra { |
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struct azx chip; |
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struct device *dev; |
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struct reset_control *reset; |
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struct clk_bulk_data clocks[3]; |
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unsigned int nclocks; |
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void __iomem *regs; |
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struct work_struct probe_work; |
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}; |
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#ifdef CONFIG_PM |
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static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT; |
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module_param(power_save, bint, 0644); |
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MODULE_PARM_DESC(power_save, |
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"Automatic power-saving timeout (in seconds, 0 = disable)."); |
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#else |
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#define power_save 0 |
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#endif |
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static const struct hda_controller_ops hda_tegra_ops; /* nothing special */ |
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static void hda_tegra_init(struct hda_tegra *hda) |
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{ |
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u32 v; |
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/* Enable PCI access */ |
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v = readl(hda->regs + HDA_IPFS_CONFIG); |
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v |= HDA_IPFS_EN_FPCI; |
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writel(v, hda->regs + HDA_IPFS_CONFIG); |
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/* Enable MEM/IO space and bus master */ |
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v = readl(hda->regs + HDA_CFG_CMD); |
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v &= ~HDA_DISABLE_INTR; |
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v |= HDA_ENABLE_MEM_SPACE | HDA_ENABLE_IO_SPACE | |
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HDA_ENABLE_BUS_MASTER | HDA_ENABLE_SERR; |
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writel(v, hda->regs + HDA_CFG_CMD); |
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writel(HDA_BAR0_INIT_PROGRAM, hda->regs + HDA_CFG_BAR0); |
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writel(HDA_BAR0_FINAL_PROGRAM, hda->regs + HDA_CFG_BAR0); |
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writel(HDA_FPCI_BAR0_START, hda->regs + HDA_IPFS_FPCI_BAR0); |
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v = readl(hda->regs + HDA_IPFS_INTR_MASK); |
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v |= HDA_IPFS_EN_INTR; |
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writel(v, hda->regs + HDA_IPFS_INTR_MASK); |
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} |
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/* |
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* power management |
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*/ |
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static int __maybe_unused hda_tegra_suspend(struct device *dev) |
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{ |
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struct snd_card *card = dev_get_drvdata(dev); |
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int rc; |
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rc = pm_runtime_force_suspend(dev); |
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if (rc < 0) |
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return rc; |
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snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); |
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return 0; |
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} |
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static int __maybe_unused hda_tegra_resume(struct device *dev) |
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{ |
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struct snd_card *card = dev_get_drvdata(dev); |
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int rc; |
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rc = pm_runtime_force_resume(dev); |
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if (rc < 0) |
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return rc; |
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snd_power_change_state(card, SNDRV_CTL_POWER_D0); |
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return 0; |
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} |
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static int __maybe_unused hda_tegra_runtime_suspend(struct device *dev) |
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{ |
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struct snd_card *card = dev_get_drvdata(dev); |
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struct azx *chip = card->private_data; |
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struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip); |
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if (chip && chip->running) { |
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/* enable controller wake up event */ |
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azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) | |
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STATESTS_INT_MASK); |
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azx_stop_chip(chip); |
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azx_enter_link_reset(chip); |
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} |
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clk_bulk_disable_unprepare(hda->nclocks, hda->clocks); |
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return 0; |
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} |
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static int __maybe_unused hda_tegra_runtime_resume(struct device *dev) |
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{ |
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struct snd_card *card = dev_get_drvdata(dev); |
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struct azx *chip = card->private_data; |
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struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip); |
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int rc; |
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if (!chip->running) { |
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rc = reset_control_assert(hda->reset); |
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if (rc) |
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return rc; |
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} |
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rc = clk_bulk_prepare_enable(hda->nclocks, hda->clocks); |
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if (rc != 0) |
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return rc; |
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if (chip->running) { |
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hda_tegra_init(hda); |
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azx_init_chip(chip, 1); |
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/* disable controller wake up event*/ |
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azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) & |
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~STATESTS_INT_MASK); |
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} else { |
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usleep_range(10, 100); |
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rc = reset_control_deassert(hda->reset); |
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if (rc) |
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return rc; |
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} |
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return 0; |
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} |
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static const struct dev_pm_ops hda_tegra_pm = { |
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SET_SYSTEM_SLEEP_PM_OPS(hda_tegra_suspend, hda_tegra_resume) |
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SET_RUNTIME_PM_OPS(hda_tegra_runtime_suspend, |
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hda_tegra_runtime_resume, |
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NULL) |
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}; |
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static int hda_tegra_dev_disconnect(struct snd_device *device) |
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{ |
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struct azx *chip = device->device_data; |
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chip->bus.shutdown = 1; |
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return 0; |
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} |
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/* |
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* destructor |
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*/ |
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static int hda_tegra_dev_free(struct snd_device *device) |
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{ |
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struct azx *chip = device->device_data; |
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struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip); |
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cancel_work_sync(&hda->probe_work); |
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if (azx_bus(chip)->chip_init) { |
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azx_stop_all_streams(chip); |
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azx_stop_chip(chip); |
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} |
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azx_free_stream_pages(chip); |
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azx_free_streams(chip); |
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snd_hdac_bus_exit(azx_bus(chip)); |
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return 0; |
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} |
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static int hda_tegra_init_chip(struct azx *chip, struct platform_device *pdev) |
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{ |
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struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip); |
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struct hdac_bus *bus = azx_bus(chip); |
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struct device *dev = hda->dev; |
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struct resource *res; |
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
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hda->regs = devm_ioremap_resource(dev, res); |
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if (IS_ERR(hda->regs)) |
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return PTR_ERR(hda->regs); |
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bus->remap_addr = hda->regs + HDA_BAR0; |
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bus->addr = res->start + HDA_BAR0; |
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hda_tegra_init(hda); |
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return 0; |
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} |
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static int hda_tegra_first_init(struct azx *chip, struct platform_device *pdev) |
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{ |
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struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip); |
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struct hdac_bus *bus = azx_bus(chip); |
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struct snd_card *card = chip->card; |
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int err; |
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unsigned short gcap; |
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int irq_id = platform_get_irq(pdev, 0); |
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const char *sname, *drv_name = "tegra-hda"; |
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struct device_node *np = pdev->dev.of_node; |
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err = hda_tegra_init_chip(chip, pdev); |
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if (err) |
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return err; |
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err = devm_request_irq(chip->card->dev, irq_id, azx_interrupt, |
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IRQF_SHARED, KBUILD_MODNAME, chip); |
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if (err) { |
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dev_err(chip->card->dev, |
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"unable to request IRQ %d, disabling device\n", |
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irq_id); |
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return err; |
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} |
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bus->irq = irq_id; |
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bus->dma_stop_delay = 100; |
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card->sync_irq = bus->irq; |
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/* |
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* Tegra194 has 4 SDO lines and the STRIPE can be used to |
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* indicate how many of the SDO lines the stream should be |
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* striped. But GCAP register does not reflect the true |
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* capability of HW. Below workaround helps to fix this. |
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* |
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* GCAP_NSDO is bits 19:18 in T_AZA_DBG_CFG_2, |
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* 0 for 1 SDO, 1 for 2 SDO, 2 for 4 SDO lines. |
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*/ |
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if (of_device_is_compatible(np, "nvidia,tegra194-hda")) { |
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u32 val; |
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dev_info(card->dev, "Override SDO lines to %u\n", |
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TEGRA194_NUM_SDO_LINES); |
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val = readl(hda->regs + FPCI_DBG_CFG_2) & ~FPCI_GCAP_NSDO_MASK; |
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val |= (TEGRA194_NUM_SDO_LINES >> 1) << FPCI_GCAP_NSDO_SHIFT; |
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writel(val, hda->regs + FPCI_DBG_CFG_2); |
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} |
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gcap = azx_readw(chip, GCAP); |
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dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap); |
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chip->align_buffer_size = 1; |
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/* read number of streams from GCAP register instead of using |
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* hardcoded value |
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*/ |
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chip->capture_streams = (gcap >> 8) & 0x0f; |
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chip->playback_streams = (gcap >> 12) & 0x0f; |
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if (!chip->playback_streams && !chip->capture_streams) { |
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/* gcap didn't give any info, switching to old method */ |
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chip->playback_streams = NUM_PLAYBACK_SD; |
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chip->capture_streams = NUM_CAPTURE_SD; |
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} |
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chip->capture_index_offset = 0; |
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chip->playback_index_offset = chip->capture_streams; |
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chip->num_streams = chip->playback_streams + chip->capture_streams; |
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/* initialize streams */ |
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err = azx_init_streams(chip); |
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if (err < 0) { |
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dev_err(card->dev, "failed to initialize streams: %d\n", err); |
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return err; |
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} |
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err = azx_alloc_stream_pages(chip); |
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if (err < 0) { |
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dev_err(card->dev, "failed to allocate stream pages: %d\n", |
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err); |
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return err; |
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} |
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/* initialize chip */ |
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azx_init_chip(chip, 1); |
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/* |
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* Playback (for 44.1K/48K, 2-channel, 16-bps) fails with |
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* 4 SDO lines due to legacy design limitation. Following |
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* is, from HD Audio Specification (Revision 1.0a), used to |
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* control striping of the stream across multiple SDO lines |
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* for sample rates <= 48K. |
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* |
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* { ((num_channels * bits_per_sample) / number of SDOs) >= 8 } |
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* |
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* Due to legacy design issue it is recommended that above |
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* ratio must be greater than 8. Since number of SDO lines is |
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* in powers of 2, next available ratio is 16 which can be |
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* used as a limiting factor here. |
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*/ |
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if (of_device_is_compatible(np, "nvidia,tegra30-hda")) |
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chip->bus.core.sdo_limit = 16; |
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/* codec detection */ |
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if (!bus->codec_mask) { |
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dev_err(card->dev, "no codecs found!\n"); |
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return -ENODEV; |
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} |
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/* driver name */ |
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strncpy(card->driver, drv_name, sizeof(card->driver)); |
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/* shortname for card */ |
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sname = of_get_property(np, "nvidia,model", NULL); |
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if (!sname) |
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sname = drv_name; |
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if (strlen(sname) > sizeof(card->shortname)) |
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dev_info(card->dev, "truncating shortname for card\n"); |
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strncpy(card->shortname, sname, sizeof(card->shortname)); |
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/* longname for card */ |
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snprintf(card->longname, sizeof(card->longname), |
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"%s at 0x%lx irq %i", |
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card->shortname, bus->addr, bus->irq); |
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return 0; |
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} |
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/* |
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* constructor |
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*/ |
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static void hda_tegra_probe_work(struct work_struct *work); |
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static int hda_tegra_create(struct snd_card *card, |
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unsigned int driver_caps, |
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struct hda_tegra *hda) |
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{ |
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static const struct snd_device_ops ops = { |
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.dev_disconnect = hda_tegra_dev_disconnect, |
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.dev_free = hda_tegra_dev_free, |
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}; |
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struct azx *chip; |
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int err; |
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chip = &hda->chip; |
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mutex_init(&chip->open_mutex); |
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chip->card = card; |
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chip->ops = &hda_tegra_ops; |
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chip->driver_caps = driver_caps; |
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chip->driver_type = driver_caps & 0xff; |
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chip->dev_index = 0; |
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INIT_LIST_HEAD(&chip->pcm_list); |
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chip->codec_probe_mask = -1; |
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chip->single_cmd = false; |
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chip->snoop = true; |
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INIT_WORK(&hda->probe_work, hda_tegra_probe_work); |
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err = azx_bus_init(chip, NULL); |
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if (err < 0) |
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return err; |
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chip->bus.core.sync_write = 0; |
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chip->bus.core.needs_damn_long_delay = 1; |
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chip->bus.core.aligned_mmio = 1; |
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err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops); |
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if (err < 0) { |
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dev_err(card->dev, "Error creating device\n"); |
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return err; |
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} |
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return 0; |
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} |
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static const struct of_device_id hda_tegra_match[] = { |
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{ .compatible = "nvidia,tegra30-hda" }, |
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{ .compatible = "nvidia,tegra194-hda" }, |
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{}, |
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}; |
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MODULE_DEVICE_TABLE(of, hda_tegra_match); |
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static int hda_tegra_probe(struct platform_device *pdev) |
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{ |
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const unsigned int driver_flags = AZX_DCAPS_CORBRP_SELF_CLEAR | |
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AZX_DCAPS_PM_RUNTIME; |
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struct snd_card *card; |
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struct azx *chip; |
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struct hda_tegra *hda; |
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int err; |
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hda = devm_kzalloc(&pdev->dev, sizeof(*hda), GFP_KERNEL); |
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if (!hda) |
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return -ENOMEM; |
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hda->dev = &pdev->dev; |
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chip = &hda->chip; |
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err = snd_card_new(&pdev->dev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1, |
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THIS_MODULE, 0, &card); |
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if (err < 0) { |
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dev_err(&pdev->dev, "Error creating card!\n"); |
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return err; |
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} |
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hda->reset = devm_reset_control_array_get_exclusive(&pdev->dev); |
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if (IS_ERR(hda->reset)) { |
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err = PTR_ERR(hda->reset); |
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goto out_free; |
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} |
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hda->clocks[hda->nclocks++].id = "hda"; |
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hda->clocks[hda->nclocks++].id = "hda2hdmi"; |
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hda->clocks[hda->nclocks++].id = "hda2codec_2x"; |
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err = devm_clk_bulk_get(&pdev->dev, hda->nclocks, hda->clocks); |
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if (err < 0) |
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goto out_free; |
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err = hda_tegra_create(card, driver_flags, hda); |
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if (err < 0) |
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goto out_free; |
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card->private_data = chip; |
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dev_set_drvdata(&pdev->dev, card); |
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pm_runtime_enable(hda->dev); |
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if (!azx_has_pm_runtime(chip)) |
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pm_runtime_forbid(hda->dev); |
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schedule_work(&hda->probe_work); |
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return 0; |
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out_free: |
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snd_card_free(card); |
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return err; |
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} |
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static void hda_tegra_probe_work(struct work_struct *work) |
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{ |
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struct hda_tegra *hda = container_of(work, struct hda_tegra, probe_work); |
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struct azx *chip = &hda->chip; |
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struct platform_device *pdev = to_platform_device(hda->dev); |
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int err; |
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pm_runtime_get_sync(hda->dev); |
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err = hda_tegra_first_init(chip, pdev); |
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if (err < 0) |
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goto out_free; |
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/* create codec instances */ |
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err = azx_probe_codecs(chip, 8); |
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if (err < 0) |
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goto out_free; |
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err = azx_codec_configure(chip); |
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if (err < 0) |
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goto out_free; |
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err = snd_card_register(chip->card); |
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if (err < 0) |
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goto out_free; |
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chip->running = 1; |
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snd_hda_set_power_save(&chip->bus, power_save * 1000); |
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out_free: |
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pm_runtime_put(hda->dev); |
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return; /* no error return from async probe */ |
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} |
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static int hda_tegra_remove(struct platform_device *pdev) |
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{ |
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int ret; |
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ret = snd_card_free(dev_get_drvdata(&pdev->dev)); |
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pm_runtime_disable(&pdev->dev); |
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return ret; |
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} |
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static void hda_tegra_shutdown(struct platform_device *pdev) |
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{ |
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struct snd_card *card = dev_get_drvdata(&pdev->dev); |
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struct azx *chip; |
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if (!card) |
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return; |
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chip = card->private_data; |
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if (chip && chip->running) |
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azx_stop_chip(chip); |
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} |
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static struct platform_driver tegra_platform_hda = { |
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.driver = { |
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.name = "tegra-hda", |
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.pm = &hda_tegra_pm, |
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.of_match_table = hda_tegra_match, |
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}, |
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.probe = hda_tegra_probe, |
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.remove = hda_tegra_remove, |
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.shutdown = hda_tegra_shutdown, |
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}; |
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module_platform_driver(tegra_platform_hda); |
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MODULE_DESCRIPTION("Tegra HDA bus driver"); |
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MODULE_LICENSE("GPL v2");
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