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638 lines
17 KiB
638 lines
17 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* mtu3_qmu.c - Queue Management Unit driver for device controller |
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* |
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* Copyright (C) 2016 MediaTek Inc. |
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* |
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* Author: Chunfeng Yun <[email protected]> |
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*/ |
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|
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/* |
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* Queue Management Unit (QMU) is designed to unload SW effort |
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* to serve DMA interrupts. |
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* By preparing General Purpose Descriptor (GPD) and Buffer Descriptor (BD), |
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* SW links data buffers and triggers QMU to send / receive data to |
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* host / from device at a time. |
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* And now only GPD is supported. |
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* |
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* For more detailed information, please refer to QMU Programming Guide |
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*/ |
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#include <linux/dmapool.h> |
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#include <linux/iopoll.h> |
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#include "mtu3.h" |
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#include "mtu3_trace.h" |
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#define QMU_CHECKSUM_LEN 16 |
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#define GPD_FLAGS_HWO BIT(0) |
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#define GPD_FLAGS_BDP BIT(1) |
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#define GPD_FLAGS_BPS BIT(2) |
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#define GPD_FLAGS_ZLP BIT(6) |
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#define GPD_FLAGS_IOC BIT(7) |
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#define GET_GPD_HWO(gpd) (le32_to_cpu((gpd)->dw0_info) & GPD_FLAGS_HWO) |
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#define GPD_RX_BUF_LEN_OG(x) (((x) & 0xffff) << 16) |
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#define GPD_RX_BUF_LEN_EL(x) (((x) & 0xfffff) << 12) |
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#define GPD_RX_BUF_LEN(mtu, x) \ |
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({ \ |
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typeof(x) x_ = (x); \ |
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((mtu)->gen2cp) ? GPD_RX_BUF_LEN_EL(x_) : GPD_RX_BUF_LEN_OG(x_); \ |
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}) |
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#define GPD_DATA_LEN_OG(x) ((x) & 0xffff) |
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#define GPD_DATA_LEN_EL(x) ((x) & 0xfffff) |
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#define GPD_DATA_LEN(mtu, x) \ |
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({ \ |
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typeof(x) x_ = (x); \ |
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((mtu)->gen2cp) ? GPD_DATA_LEN_EL(x_) : GPD_DATA_LEN_OG(x_); \ |
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}) |
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#define GPD_EXT_FLAG_ZLP BIT(29) |
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#define GPD_EXT_NGP_OG(x) (((x) & 0xf) << 20) |
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#define GPD_EXT_BUF_OG(x) (((x) & 0xf) << 16) |
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#define GPD_EXT_NGP_EL(x) (((x) & 0xf) << 28) |
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#define GPD_EXT_BUF_EL(x) (((x) & 0xf) << 24) |
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#define GPD_EXT_NGP(mtu, x) \ |
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({ \ |
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typeof(x) x_ = (x); \ |
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((mtu)->gen2cp) ? GPD_EXT_NGP_EL(x_) : GPD_EXT_NGP_OG(x_); \ |
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}) |
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#define GPD_EXT_BUF(mtu, x) \ |
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({ \ |
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typeof(x) x_ = (x); \ |
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((mtu)->gen2cp) ? GPD_EXT_BUF_EL(x_) : GPD_EXT_BUF_OG(x_); \ |
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}) |
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#define HILO_GEN64(hi, lo) (((u64)(hi) << 32) + (lo)) |
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#define HILO_DMA(hi, lo) \ |
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((dma_addr_t)HILO_GEN64((le32_to_cpu(hi)), (le32_to_cpu(lo)))) |
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static dma_addr_t read_txq_cur_addr(void __iomem *mbase, u8 epnum) |
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{ |
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u32 txcpr; |
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u32 txhiar; |
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txcpr = mtu3_readl(mbase, USB_QMU_TQCPR(epnum)); |
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txhiar = mtu3_readl(mbase, USB_QMU_TQHIAR(epnum)); |
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return HILO_DMA(QMU_CUR_GPD_ADDR_HI(txhiar), txcpr); |
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} |
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static dma_addr_t read_rxq_cur_addr(void __iomem *mbase, u8 epnum) |
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{ |
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u32 rxcpr; |
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u32 rxhiar; |
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rxcpr = mtu3_readl(mbase, USB_QMU_RQCPR(epnum)); |
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rxhiar = mtu3_readl(mbase, USB_QMU_RQHIAR(epnum)); |
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return HILO_DMA(QMU_CUR_GPD_ADDR_HI(rxhiar), rxcpr); |
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} |
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static void write_txq_start_addr(void __iomem *mbase, u8 epnum, dma_addr_t dma) |
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{ |
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u32 tqhiar; |
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mtu3_writel(mbase, USB_QMU_TQSAR(epnum), |
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cpu_to_le32(lower_32_bits(dma))); |
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tqhiar = mtu3_readl(mbase, USB_QMU_TQHIAR(epnum)); |
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tqhiar &= ~QMU_START_ADDR_HI_MSK; |
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tqhiar |= QMU_START_ADDR_HI(upper_32_bits(dma)); |
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mtu3_writel(mbase, USB_QMU_TQHIAR(epnum), tqhiar); |
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} |
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static void write_rxq_start_addr(void __iomem *mbase, u8 epnum, dma_addr_t dma) |
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{ |
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u32 rqhiar; |
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mtu3_writel(mbase, USB_QMU_RQSAR(epnum), |
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cpu_to_le32(lower_32_bits(dma))); |
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rqhiar = mtu3_readl(mbase, USB_QMU_RQHIAR(epnum)); |
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rqhiar &= ~QMU_START_ADDR_HI_MSK; |
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rqhiar |= QMU_START_ADDR_HI(upper_32_bits(dma)); |
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mtu3_writel(mbase, USB_QMU_RQHIAR(epnum), rqhiar); |
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} |
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static struct qmu_gpd *gpd_dma_to_virt(struct mtu3_gpd_ring *ring, |
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dma_addr_t dma_addr) |
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{ |
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dma_addr_t dma_base = ring->dma; |
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struct qmu_gpd *gpd_head = ring->start; |
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u32 offset = (dma_addr - dma_base) / sizeof(*gpd_head); |
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if (offset >= MAX_GPD_NUM) |
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return NULL; |
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return gpd_head + offset; |
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} |
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static dma_addr_t gpd_virt_to_dma(struct mtu3_gpd_ring *ring, |
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struct qmu_gpd *gpd) |
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{ |
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dma_addr_t dma_base = ring->dma; |
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struct qmu_gpd *gpd_head = ring->start; |
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u32 offset; |
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offset = gpd - gpd_head; |
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if (offset >= MAX_GPD_NUM) |
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return 0; |
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return dma_base + (offset * sizeof(*gpd)); |
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} |
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static void gpd_ring_init(struct mtu3_gpd_ring *ring, struct qmu_gpd *gpd) |
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{ |
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ring->start = gpd; |
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ring->enqueue = gpd; |
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ring->dequeue = gpd; |
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ring->end = gpd + MAX_GPD_NUM - 1; |
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} |
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static void reset_gpd_list(struct mtu3_ep *mep) |
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{ |
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struct mtu3_gpd_ring *ring = &mep->gpd_ring; |
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struct qmu_gpd *gpd = ring->start; |
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if (gpd) { |
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gpd->dw0_info &= cpu_to_le32(~GPD_FLAGS_HWO); |
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gpd_ring_init(ring, gpd); |
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} |
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} |
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int mtu3_gpd_ring_alloc(struct mtu3_ep *mep) |
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{ |
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struct qmu_gpd *gpd; |
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struct mtu3_gpd_ring *ring = &mep->gpd_ring; |
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/* software own all gpds as default */ |
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gpd = dma_pool_zalloc(mep->mtu->qmu_gpd_pool, GFP_ATOMIC, &ring->dma); |
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if (gpd == NULL) |
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return -ENOMEM; |
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gpd_ring_init(ring, gpd); |
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return 0; |
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} |
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void mtu3_gpd_ring_free(struct mtu3_ep *mep) |
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{ |
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struct mtu3_gpd_ring *ring = &mep->gpd_ring; |
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dma_pool_free(mep->mtu->qmu_gpd_pool, |
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ring->start, ring->dma); |
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memset(ring, 0, sizeof(*ring)); |
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} |
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void mtu3_qmu_resume(struct mtu3_ep *mep) |
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{ |
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struct mtu3 *mtu = mep->mtu; |
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void __iomem *mbase = mtu->mac_base; |
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int epnum = mep->epnum; |
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u32 offset; |
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offset = mep->is_in ? USB_QMU_TQCSR(epnum) : USB_QMU_RQCSR(epnum); |
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mtu3_writel(mbase, offset, QMU_Q_RESUME); |
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if (!(mtu3_readl(mbase, offset) & QMU_Q_ACTIVE)) |
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mtu3_writel(mbase, offset, QMU_Q_RESUME); |
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} |
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static struct qmu_gpd *advance_enq_gpd(struct mtu3_gpd_ring *ring) |
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{ |
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if (ring->enqueue < ring->end) |
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ring->enqueue++; |
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else |
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ring->enqueue = ring->start; |
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return ring->enqueue; |
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} |
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static struct qmu_gpd *advance_deq_gpd(struct mtu3_gpd_ring *ring) |
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{ |
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if (ring->dequeue < ring->end) |
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ring->dequeue++; |
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else |
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ring->dequeue = ring->start; |
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return ring->dequeue; |
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} |
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/* check if a ring is emtpy */ |
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static int gpd_ring_empty(struct mtu3_gpd_ring *ring) |
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{ |
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struct qmu_gpd *enq = ring->enqueue; |
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struct qmu_gpd *next; |
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if (ring->enqueue < ring->end) |
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next = enq + 1; |
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else |
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next = ring->start; |
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/* one gpd is reserved to simplify gpd preparation */ |
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return next == ring->dequeue; |
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} |
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int mtu3_prepare_transfer(struct mtu3_ep *mep) |
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{ |
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return gpd_ring_empty(&mep->gpd_ring); |
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} |
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static int mtu3_prepare_tx_gpd(struct mtu3_ep *mep, struct mtu3_request *mreq) |
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{ |
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struct qmu_gpd *enq; |
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struct mtu3_gpd_ring *ring = &mep->gpd_ring; |
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struct qmu_gpd *gpd = ring->enqueue; |
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struct usb_request *req = &mreq->request; |
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struct mtu3 *mtu = mep->mtu; |
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dma_addr_t enq_dma; |
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u32 ext_addr; |
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gpd->dw0_info = 0; /* SW own it */ |
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gpd->buffer = cpu_to_le32(lower_32_bits(req->dma)); |
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ext_addr = GPD_EXT_BUF(mtu, upper_32_bits(req->dma)); |
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gpd->dw3_info = cpu_to_le32(GPD_DATA_LEN(mtu, req->length)); |
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/* get the next GPD */ |
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enq = advance_enq_gpd(ring); |
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enq_dma = gpd_virt_to_dma(ring, enq); |
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dev_dbg(mep->mtu->dev, "TX-EP%d queue gpd=%p, enq=%p, qdma=%pad\n", |
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mep->epnum, gpd, enq, &enq_dma); |
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enq->dw0_info &= cpu_to_le32(~GPD_FLAGS_HWO); |
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gpd->next_gpd = cpu_to_le32(lower_32_bits(enq_dma)); |
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ext_addr |= GPD_EXT_NGP(mtu, upper_32_bits(enq_dma)); |
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gpd->dw0_info = cpu_to_le32(ext_addr); |
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if (req->zero) { |
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if (mtu->gen2cp) |
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gpd->dw0_info |= cpu_to_le32(GPD_FLAGS_ZLP); |
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else |
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gpd->dw3_info |= cpu_to_le32(GPD_EXT_FLAG_ZLP); |
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} |
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gpd->dw0_info |= cpu_to_le32(GPD_FLAGS_IOC | GPD_FLAGS_HWO); |
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mreq->gpd = gpd; |
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trace_mtu3_prepare_gpd(mep, gpd); |
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return 0; |
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} |
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static int mtu3_prepare_rx_gpd(struct mtu3_ep *mep, struct mtu3_request *mreq) |
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{ |
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struct qmu_gpd *enq; |
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struct mtu3_gpd_ring *ring = &mep->gpd_ring; |
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struct qmu_gpd *gpd = ring->enqueue; |
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struct usb_request *req = &mreq->request; |
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struct mtu3 *mtu = mep->mtu; |
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dma_addr_t enq_dma; |
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u32 ext_addr; |
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gpd->dw0_info = 0; /* SW own it */ |
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gpd->buffer = cpu_to_le32(lower_32_bits(req->dma)); |
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ext_addr = GPD_EXT_BUF(mtu, upper_32_bits(req->dma)); |
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gpd->dw0_info = cpu_to_le32(GPD_RX_BUF_LEN(mtu, req->length)); |
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/* get the next GPD */ |
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enq = advance_enq_gpd(ring); |
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enq_dma = gpd_virt_to_dma(ring, enq); |
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dev_dbg(mep->mtu->dev, "RX-EP%d queue gpd=%p, enq=%p, qdma=%pad\n", |
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mep->epnum, gpd, enq, &enq_dma); |
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enq->dw0_info &= cpu_to_le32(~GPD_FLAGS_HWO); |
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gpd->next_gpd = cpu_to_le32(lower_32_bits(enq_dma)); |
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ext_addr |= GPD_EXT_NGP(mtu, upper_32_bits(enq_dma)); |
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gpd->dw3_info = cpu_to_le32(ext_addr); |
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gpd->dw0_info |= cpu_to_le32(GPD_FLAGS_IOC | GPD_FLAGS_HWO); |
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mreq->gpd = gpd; |
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trace_mtu3_prepare_gpd(mep, gpd); |
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return 0; |
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} |
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void mtu3_insert_gpd(struct mtu3_ep *mep, struct mtu3_request *mreq) |
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{ |
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if (mep->is_in) |
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mtu3_prepare_tx_gpd(mep, mreq); |
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else |
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mtu3_prepare_rx_gpd(mep, mreq); |
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} |
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int mtu3_qmu_start(struct mtu3_ep *mep) |
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{ |
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struct mtu3 *mtu = mep->mtu; |
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void __iomem *mbase = mtu->mac_base; |
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struct mtu3_gpd_ring *ring = &mep->gpd_ring; |
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u8 epnum = mep->epnum; |
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if (mep->is_in) { |
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/* set QMU start address */ |
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write_txq_start_addr(mbase, epnum, ring->dma); |
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mtu3_setbits(mbase, MU3D_EP_TXCR0(epnum), TX_DMAREQEN); |
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/* send zero length packet according to ZLP flag in GPD */ |
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mtu3_setbits(mbase, U3D_QCR1, QMU_TX_ZLP(epnum)); |
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mtu3_writel(mbase, U3D_TQERRIESR0, |
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QMU_TX_LEN_ERR(epnum) | QMU_TX_CS_ERR(epnum)); |
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if (mtu3_readl(mbase, USB_QMU_TQCSR(epnum)) & QMU_Q_ACTIVE) { |
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dev_warn(mtu->dev, "Tx %d Active Now!\n", epnum); |
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return 0; |
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} |
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mtu3_writel(mbase, USB_QMU_TQCSR(epnum), QMU_Q_START); |
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} else { |
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write_rxq_start_addr(mbase, epnum, ring->dma); |
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mtu3_setbits(mbase, MU3D_EP_RXCR0(epnum), RX_DMAREQEN); |
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/* don't expect ZLP */ |
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mtu3_clrbits(mbase, U3D_QCR3, QMU_RX_ZLP(epnum)); |
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/* move to next GPD when receive ZLP */ |
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mtu3_setbits(mbase, U3D_QCR3, QMU_RX_COZ(epnum)); |
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mtu3_writel(mbase, U3D_RQERRIESR0, |
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QMU_RX_LEN_ERR(epnum) | QMU_RX_CS_ERR(epnum)); |
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mtu3_writel(mbase, U3D_RQERRIESR1, QMU_RX_ZLP_ERR(epnum)); |
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if (mtu3_readl(mbase, USB_QMU_RQCSR(epnum)) & QMU_Q_ACTIVE) { |
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dev_warn(mtu->dev, "Rx %d Active Now!\n", epnum); |
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return 0; |
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} |
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mtu3_writel(mbase, USB_QMU_RQCSR(epnum), QMU_Q_START); |
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} |
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return 0; |
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} |
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/* may called in atomic context */ |
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void mtu3_qmu_stop(struct mtu3_ep *mep) |
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{ |
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struct mtu3 *mtu = mep->mtu; |
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void __iomem *mbase = mtu->mac_base; |
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int epnum = mep->epnum; |
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u32 value = 0; |
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u32 qcsr; |
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int ret; |
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qcsr = mep->is_in ? USB_QMU_TQCSR(epnum) : USB_QMU_RQCSR(epnum); |
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if (!(mtu3_readl(mbase, qcsr) & QMU_Q_ACTIVE)) { |
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dev_dbg(mtu->dev, "%s's qmu is inactive now!\n", mep->name); |
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return; |
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} |
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mtu3_writel(mbase, qcsr, QMU_Q_STOP); |
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ret = readl_poll_timeout_atomic(mbase + qcsr, value, |
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!(value & QMU_Q_ACTIVE), 1, 1000); |
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if (ret) { |
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dev_err(mtu->dev, "stop %s's qmu failed\n", mep->name); |
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return; |
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} |
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dev_dbg(mtu->dev, "%s's qmu stop now!\n", mep->name); |
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} |
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void mtu3_qmu_flush(struct mtu3_ep *mep) |
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{ |
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dev_dbg(mep->mtu->dev, "%s flush QMU %s\n", __func__, |
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((mep->is_in) ? "TX" : "RX")); |
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/*Stop QMU */ |
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mtu3_qmu_stop(mep); |
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reset_gpd_list(mep); |
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} |
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/* |
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* QMU can't transfer zero length packet directly (a hardware limit |
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* on old SoCs), so when needs to send ZLP, we intentionally trigger |
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* a length error interrupt, and in the ISR sends a ZLP by BMU. |
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*/ |
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static void qmu_tx_zlp_error_handler(struct mtu3 *mtu, u8 epnum) |
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{ |
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struct mtu3_ep *mep = mtu->in_eps + epnum; |
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struct mtu3_gpd_ring *ring = &mep->gpd_ring; |
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void __iomem *mbase = mtu->mac_base; |
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struct qmu_gpd *gpd_current = NULL; |
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struct mtu3_request *mreq; |
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dma_addr_t cur_gpd_dma; |
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u32 txcsr = 0; |
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int ret; |
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mreq = next_request(mep); |
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if (mreq && mreq->request.length != 0) |
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return; |
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cur_gpd_dma = read_txq_cur_addr(mbase, epnum); |
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gpd_current = gpd_dma_to_virt(ring, cur_gpd_dma); |
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if (GPD_DATA_LEN(mtu, le32_to_cpu(gpd_current->dw3_info)) != 0) { |
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dev_err(mtu->dev, "TX EP%d buffer length error(!=0)\n", epnum); |
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return; |
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} |
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dev_dbg(mtu->dev, "%s send ZLP for req=%p\n", __func__, mreq); |
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trace_mtu3_zlp_exp_gpd(mep, gpd_current); |
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mtu3_clrbits(mbase, MU3D_EP_TXCR0(mep->epnum), TX_DMAREQEN); |
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ret = readl_poll_timeout_atomic(mbase + MU3D_EP_TXCR0(mep->epnum), |
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txcsr, !(txcsr & TX_FIFOFULL), 1, 1000); |
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if (ret) { |
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dev_err(mtu->dev, "%s wait for fifo empty fail\n", __func__); |
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return; |
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} |
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mtu3_setbits(mbase, MU3D_EP_TXCR0(mep->epnum), TX_TXPKTRDY); |
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/* by pass the current GDP */ |
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gpd_current->dw0_info |= cpu_to_le32(GPD_FLAGS_BPS | GPD_FLAGS_HWO); |
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/*enable DMAREQEN, switch back to QMU mode */ |
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mtu3_setbits(mbase, MU3D_EP_TXCR0(mep->epnum), TX_DMAREQEN); |
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mtu3_qmu_resume(mep); |
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} |
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/* |
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* NOTE: request list maybe is already empty as following case: |
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* queue_tx --> qmu_interrupt(clear interrupt pending, schedule tasklet)--> |
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* queue_tx --> process_tasklet(meanwhile, the second one is transferred, |
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* tasklet process both of them)-->qmu_interrupt for second one. |
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* To avoid upper case, put qmu_done_tx in ISR directly to process it. |
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*/ |
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static void qmu_done_tx(struct mtu3 *mtu, u8 epnum) |
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{ |
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struct mtu3_ep *mep = mtu->in_eps + epnum; |
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struct mtu3_gpd_ring *ring = &mep->gpd_ring; |
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void __iomem *mbase = mtu->mac_base; |
|
struct qmu_gpd *gpd = ring->dequeue; |
|
struct qmu_gpd *gpd_current = NULL; |
|
struct usb_request *request = NULL; |
|
struct mtu3_request *mreq; |
|
dma_addr_t cur_gpd_dma; |
|
|
|
/*transfer phy address got from QMU register to virtual address */ |
|
cur_gpd_dma = read_txq_cur_addr(mbase, epnum); |
|
gpd_current = gpd_dma_to_virt(ring, cur_gpd_dma); |
|
|
|
dev_dbg(mtu->dev, "%s EP%d, last=%p, current=%p, enq=%p\n", |
|
__func__, epnum, gpd, gpd_current, ring->enqueue); |
|
|
|
while (gpd != gpd_current && !GET_GPD_HWO(gpd)) { |
|
|
|
mreq = next_request(mep); |
|
|
|
if (mreq == NULL || mreq->gpd != gpd) { |
|
dev_err(mtu->dev, "no correct TX req is found\n"); |
|
break; |
|
} |
|
|
|
request = &mreq->request; |
|
request->actual = GPD_DATA_LEN(mtu, le32_to_cpu(gpd->dw3_info)); |
|
trace_mtu3_complete_gpd(mep, gpd); |
|
mtu3_req_complete(mep, request, 0); |
|
|
|
gpd = advance_deq_gpd(ring); |
|
} |
|
|
|
dev_dbg(mtu->dev, "%s EP%d, deq=%p, enq=%p, complete\n", |
|
__func__, epnum, ring->dequeue, ring->enqueue); |
|
|
|
} |
|
|
|
static void qmu_done_rx(struct mtu3 *mtu, u8 epnum) |
|
{ |
|
struct mtu3_ep *mep = mtu->out_eps + epnum; |
|
struct mtu3_gpd_ring *ring = &mep->gpd_ring; |
|
void __iomem *mbase = mtu->mac_base; |
|
struct qmu_gpd *gpd = ring->dequeue; |
|
struct qmu_gpd *gpd_current = NULL; |
|
struct usb_request *req = NULL; |
|
struct mtu3_request *mreq; |
|
dma_addr_t cur_gpd_dma; |
|
|
|
cur_gpd_dma = read_rxq_cur_addr(mbase, epnum); |
|
gpd_current = gpd_dma_to_virt(ring, cur_gpd_dma); |
|
|
|
dev_dbg(mtu->dev, "%s EP%d, last=%p, current=%p, enq=%p\n", |
|
__func__, epnum, gpd, gpd_current, ring->enqueue); |
|
|
|
while (gpd != gpd_current && !GET_GPD_HWO(gpd)) { |
|
|
|
mreq = next_request(mep); |
|
|
|
if (mreq == NULL || mreq->gpd != gpd) { |
|
dev_err(mtu->dev, "no correct RX req is found\n"); |
|
break; |
|
} |
|
req = &mreq->request; |
|
|
|
req->actual = GPD_DATA_LEN(mtu, le32_to_cpu(gpd->dw3_info)); |
|
trace_mtu3_complete_gpd(mep, gpd); |
|
mtu3_req_complete(mep, req, 0); |
|
|
|
gpd = advance_deq_gpd(ring); |
|
} |
|
|
|
dev_dbg(mtu->dev, "%s EP%d, deq=%p, enq=%p, complete\n", |
|
__func__, epnum, ring->dequeue, ring->enqueue); |
|
} |
|
|
|
static void qmu_done_isr(struct mtu3 *mtu, u32 done_status) |
|
{ |
|
int i; |
|
|
|
for (i = 1; i < mtu->num_eps; i++) { |
|
if (done_status & QMU_RX_DONE_INT(i)) |
|
qmu_done_rx(mtu, i); |
|
if (done_status & QMU_TX_DONE_INT(i)) |
|
qmu_done_tx(mtu, i); |
|
} |
|
} |
|
|
|
static void qmu_exception_isr(struct mtu3 *mtu, u32 qmu_status) |
|
{ |
|
void __iomem *mbase = mtu->mac_base; |
|
u32 errval; |
|
int i; |
|
|
|
if ((qmu_status & RXQ_CSERR_INT) || (qmu_status & RXQ_LENERR_INT)) { |
|
errval = mtu3_readl(mbase, U3D_RQERRIR0); |
|
for (i = 1; i < mtu->num_eps; i++) { |
|
if (errval & QMU_RX_CS_ERR(i)) |
|
dev_err(mtu->dev, "Rx %d CS error!\n", i); |
|
|
|
if (errval & QMU_RX_LEN_ERR(i)) |
|
dev_err(mtu->dev, "RX %d Length error\n", i); |
|
} |
|
mtu3_writel(mbase, U3D_RQERRIR0, errval); |
|
} |
|
|
|
if (qmu_status & RXQ_ZLPERR_INT) { |
|
errval = mtu3_readl(mbase, U3D_RQERRIR1); |
|
for (i = 1; i < mtu->num_eps; i++) { |
|
if (errval & QMU_RX_ZLP_ERR(i)) |
|
dev_dbg(mtu->dev, "RX EP%d Recv ZLP\n", i); |
|
} |
|
mtu3_writel(mbase, U3D_RQERRIR1, errval); |
|
} |
|
|
|
if ((qmu_status & TXQ_CSERR_INT) || (qmu_status & TXQ_LENERR_INT)) { |
|
errval = mtu3_readl(mbase, U3D_TQERRIR0); |
|
for (i = 1; i < mtu->num_eps; i++) { |
|
if (errval & QMU_TX_CS_ERR(i)) |
|
dev_err(mtu->dev, "Tx %d checksum error!\n", i); |
|
|
|
if (errval & QMU_TX_LEN_ERR(i)) |
|
qmu_tx_zlp_error_handler(mtu, i); |
|
} |
|
mtu3_writel(mbase, U3D_TQERRIR0, errval); |
|
} |
|
} |
|
|
|
irqreturn_t mtu3_qmu_isr(struct mtu3 *mtu) |
|
{ |
|
void __iomem *mbase = mtu->mac_base; |
|
u32 qmu_status; |
|
u32 qmu_done_status; |
|
|
|
/* U3D_QISAR1 is read update */ |
|
qmu_status = mtu3_readl(mbase, U3D_QISAR1); |
|
qmu_status &= mtu3_readl(mbase, U3D_QIER1); |
|
|
|
qmu_done_status = mtu3_readl(mbase, U3D_QISAR0); |
|
qmu_done_status &= mtu3_readl(mbase, U3D_QIER0); |
|
mtu3_writel(mbase, U3D_QISAR0, qmu_done_status); /* W1C */ |
|
dev_dbg(mtu->dev, "=== QMUdone[tx=%x, rx=%x] QMUexp[%x] ===\n", |
|
(qmu_done_status & 0xFFFF), qmu_done_status >> 16, |
|
qmu_status); |
|
trace_mtu3_qmu_isr(qmu_done_status, qmu_status); |
|
|
|
if (qmu_done_status) |
|
qmu_done_isr(mtu, qmu_done_status); |
|
|
|
if (qmu_status) |
|
qmu_exception_isr(mtu, qmu_status); |
|
|
|
return IRQ_HANDLED; |
|
} |
|
|
|
int mtu3_qmu_init(struct mtu3 *mtu) |
|
{ |
|
|
|
compiletime_assert(QMU_GPD_SIZE == 16, "QMU_GPD size SHOULD be 16B"); |
|
|
|
mtu->qmu_gpd_pool = dma_pool_create("QMU_GPD", mtu->dev, |
|
QMU_GPD_RING_SIZE, QMU_GPD_SIZE, 0); |
|
|
|
if (!mtu->qmu_gpd_pool) |
|
return -ENOMEM; |
|
|
|
return 0; |
|
} |
|
|
|
void mtu3_qmu_exit(struct mtu3 *mtu) |
|
{ |
|
dma_pool_destroy(mtu->qmu_gpd_pool); |
|
}
|
|
|