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222 lines
5.4 KiB
222 lines
5.4 KiB
// SPDX-License-Identifier: GPL-2.0+ |
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/* |
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* USB Peripheral Controller driver for Aeroflex Gaisler GRUSBDC. |
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* |
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* 2013 (c) Aeroflex Gaisler AB |
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* |
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* This driver supports GRUSBDC USB Device Controller cores available in the |
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* GRLIB VHDL IP core library. |
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* |
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* Full documentation of the GRUSBDC core can be found here: |
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* https://www.gaisler.com/products/grlib/grip.pdf |
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* |
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* Contributors: |
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* - Andreas Larsson <[email protected]> |
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* - Marko Isomaki |
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*/ |
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/* Control registers on the AMBA bus */ |
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#define GR_MAXEP 16 /* Max # endpoints for *each* direction */ |
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struct gr_epregs { |
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u32 epctrl; |
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union { |
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struct { /* Slave mode*/ |
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u32 slvctrl; |
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u32 slvdata; |
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}; |
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struct { /* DMA mode*/ |
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u32 dmactrl; |
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u32 dmaaddr; |
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}; |
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}; |
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u32 epstat; |
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}; |
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struct gr_regs { |
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struct gr_epregs epo[GR_MAXEP]; /* 0x000 - 0x0fc */ |
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struct gr_epregs epi[GR_MAXEP]; /* 0x100 - 0x1fc */ |
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u32 control; /* 0x200 */ |
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u32 status; /* 0x204 */ |
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}; |
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#define GR_EPCTRL_BUFSZ_SCALER 8 |
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#define GR_EPCTRL_BUFSZ_MASK 0xffe00000 |
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#define GR_EPCTRL_BUFSZ_POS 21 |
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#define GR_EPCTRL_PI BIT(20) |
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#define GR_EPCTRL_CB BIT(19) |
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#define GR_EPCTRL_CS BIT(18) |
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#define GR_EPCTRL_MAXPL_MASK 0x0003ff80 |
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#define GR_EPCTRL_MAXPL_POS 7 |
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#define GR_EPCTRL_NT_MASK 0x00000060 |
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#define GR_EPCTRL_NT_POS 5 |
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#define GR_EPCTRL_TT_MASK 0x00000018 |
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#define GR_EPCTRL_TT_POS 3 |
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#define GR_EPCTRL_EH BIT(2) |
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#define GR_EPCTRL_ED BIT(1) |
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#define GR_EPCTRL_EV BIT(0) |
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#define GR_DMACTRL_AE BIT(10) |
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#define GR_DMACTRL_AD BIT(3) |
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#define GR_DMACTRL_AI BIT(2) |
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#define GR_DMACTRL_IE BIT(1) |
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#define GR_DMACTRL_DA BIT(0) |
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#define GR_EPSTAT_PT BIT(29) |
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#define GR_EPSTAT_PR BIT(29) |
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#define GR_EPSTAT_B1CNT_MASK 0x1fff0000 |
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#define GR_EPSTAT_B1CNT_POS 16 |
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#define GR_EPSTAT_B0CNT_MASK 0x0000fff8 |
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#define GR_EPSTAT_B0CNT_POS 3 |
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#define GR_EPSTAT_B1 BIT(2) |
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#define GR_EPSTAT_B0 BIT(1) |
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#define GR_EPSTAT_BS BIT(0) |
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#define GR_CONTROL_SI BIT(31) |
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#define GR_CONTROL_UI BIT(30) |
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#define GR_CONTROL_VI BIT(29) |
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#define GR_CONTROL_SP BIT(28) |
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#define GR_CONTROL_FI BIT(27) |
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#define GR_CONTROL_EP BIT(14) |
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#define GR_CONTROL_DH BIT(13) |
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#define GR_CONTROL_RW BIT(12) |
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#define GR_CONTROL_TS_MASK 0x00000e00 |
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#define GR_CONTROL_TS_POS 9 |
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#define GR_CONTROL_TM BIT(8) |
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#define GR_CONTROL_UA_MASK 0x000000fe |
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#define GR_CONTROL_UA_POS 1 |
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#define GR_CONTROL_SU BIT(0) |
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#define GR_STATUS_NEPI_MASK 0xf0000000 |
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#define GR_STATUS_NEPI_POS 28 |
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#define GR_STATUS_NEPO_MASK 0x0f000000 |
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#define GR_STATUS_NEPO_POS 24 |
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#define GR_STATUS_DM BIT(23) |
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#define GR_STATUS_SU BIT(17) |
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#define GR_STATUS_UR BIT(16) |
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#define GR_STATUS_VB BIT(15) |
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#define GR_STATUS_SP BIT(14) |
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#define GR_STATUS_AF_MASK 0x00003800 |
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#define GR_STATUS_AF_POS 11 |
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#define GR_STATUS_FN_MASK 0x000007ff |
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#define GR_STATUS_FN_POS 0 |
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#define MAX_CTRL_PL_SIZE 64 /* As per USB standard for full and high speed */ |
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/*-------------------------------------------------------------------------*/ |
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/* Driver data structures and utilities */ |
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struct gr_dma_desc { |
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u32 ctrl; |
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u32 data; |
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u32 next; |
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/* These must be last because hw uses the previous three */ |
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u32 paddr; |
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struct gr_dma_desc *next_desc; |
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}; |
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#define GR_DESC_OUT_CTRL_SE BIT(17) |
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#define GR_DESC_OUT_CTRL_IE BIT(15) |
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#define GR_DESC_OUT_CTRL_NX BIT(14) |
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#define GR_DESC_OUT_CTRL_EN BIT(13) |
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#define GR_DESC_OUT_CTRL_LEN_MASK 0x00001fff |
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#define GR_DESC_IN_CTRL_MO BIT(18) |
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#define GR_DESC_IN_CTRL_PI BIT(17) |
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#define GR_DESC_IN_CTRL_ML BIT(16) |
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#define GR_DESC_IN_CTRL_IE BIT(15) |
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#define GR_DESC_IN_CTRL_NX BIT(14) |
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#define GR_DESC_IN_CTRL_EN BIT(13) |
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#define GR_DESC_IN_CTRL_LEN_MASK 0x00001fff |
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#define GR_DESC_DMAADDR_MASK 0xfffffffc |
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struct gr_ep { |
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struct usb_ep ep; |
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struct gr_udc *dev; |
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u16 bytes_per_buffer; |
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unsigned int dma_start; |
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struct gr_epregs __iomem *regs; |
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unsigned num:8; |
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unsigned is_in:1; |
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unsigned stopped:1; |
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unsigned wedged:1; |
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unsigned callback:1; |
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/* analogous to a host-side qh */ |
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struct list_head queue; |
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struct list_head ep_list; |
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/* Bounce buffer for end of "odd" sized OUT requests */ |
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void *tailbuf; |
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dma_addr_t tailbuf_paddr; |
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}; |
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struct gr_request { |
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struct usb_request req; |
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struct list_head queue; |
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/* Chain of dma descriptors */ |
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struct gr_dma_desc *first_desc; /* First in the chain */ |
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struct gr_dma_desc *curr_desc; /* Current descriptor */ |
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struct gr_dma_desc *last_desc; /* Last in the chain */ |
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u16 evenlen; /* Size of even length head (if oddlen != 0) */ |
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u16 oddlen; /* Size of odd length tail if buffer length is "odd" */ |
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u8 setup; /* Setup packet */ |
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}; |
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enum gr_ep0state { |
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GR_EP0_DISCONNECT = 0, /* No host */ |
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GR_EP0_SETUP, /* Between STATUS ack and SETUP report */ |
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GR_EP0_IDATA, /* IN data stage */ |
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GR_EP0_ODATA, /* OUT data stage */ |
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GR_EP0_ISTATUS, /* Status stage after IN data stage */ |
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GR_EP0_OSTATUS, /* Status stage after OUT data stage */ |
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GR_EP0_STALL, /* Data or status stages */ |
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GR_EP0_SUSPEND, /* USB suspend */ |
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}; |
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struct gr_udc { |
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struct usb_gadget gadget; |
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struct gr_ep epi[GR_MAXEP]; |
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struct gr_ep epo[GR_MAXEP]; |
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struct usb_gadget_driver *driver; |
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struct dma_pool *desc_pool; |
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struct device *dev; |
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enum gr_ep0state ep0state; |
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struct gr_request *ep0reqo; |
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struct gr_request *ep0reqi; |
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struct gr_regs __iomem *regs; |
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int irq; |
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int irqi; |
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int irqo; |
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unsigned added:1; |
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unsigned irq_enabled:1; |
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unsigned remote_wakeup:1; |
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u8 test_mode; |
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enum usb_device_state suspended_from; |
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unsigned int nepi; |
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unsigned int nepo; |
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struct list_head ep_list; |
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spinlock_t lock; /* General lock, a.k.a. "dev->lock" in comments */ |
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struct dentry *dfs_root; |
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}; |
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#define to_gr_udc(gadget) (container_of((gadget), struct gr_udc, gadget))
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