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289 lines
7.0 KiB
289 lines
7.0 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* Toshiba TC86C001 ("Goku-S") USB Device Controller driver |
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* |
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* Copyright (C) 2000-2002 Lineo |
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* by Stuart Lynne, Tom Rushworth, and Bruce Balden |
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* Copyright (C) 2002 Toshiba Corporation |
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* Copyright (C) 2003 MontaVista Software ([email protected]) |
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*/ |
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/* |
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* PCI BAR 0 points to these registers. |
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*/ |
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struct goku_udc_regs { |
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/* irq management */ |
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u32 int_status; /* 0x000 */ |
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u32 int_enable; |
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#define INT_SUSPEND 0x00001 /* or resume */ |
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#define INT_USBRESET 0x00002 |
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#define INT_ENDPOINT0 0x00004 |
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#define INT_SETUP 0x00008 |
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#define INT_STATUS 0x00010 |
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#define INT_STATUSNAK 0x00020 |
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#define INT_EPxDATASET(n) (0x00020 << (n)) /* 0 < n < 4 */ |
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# define INT_EP1DATASET 0x00040 |
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# define INT_EP2DATASET 0x00080 |
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# define INT_EP3DATASET 0x00100 |
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#define INT_EPnNAK(n) (0x00100 << (n)) /* 0 < n < 4 */ |
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# define INT_EP1NAK 0x00200 |
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# define INT_EP2NAK 0x00400 |
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# define INT_EP3NAK 0x00800 |
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#define INT_SOF 0x01000 |
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#define INT_ERR 0x02000 |
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#define INT_MSTWRSET 0x04000 |
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#define INT_MSTWREND 0x08000 |
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#define INT_MSTWRTMOUT 0x10000 |
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#define INT_MSTRDEND 0x20000 |
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#define INT_SYSERROR 0x40000 |
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#define INT_PWRDETECT 0x80000 |
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#define INT_DEVWIDE \ |
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(INT_PWRDETECT|INT_SYSERROR/*|INT_ERR*/|INT_USBRESET|INT_SUSPEND) |
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#define INT_EP0 \ |
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(INT_SETUP|INT_ENDPOINT0/*|INT_STATUS*/|INT_STATUSNAK) |
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u32 dma_master; |
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#define MST_EOPB_DIS 0x0800 |
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#define MST_EOPB_ENA 0x0400 |
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#define MST_TIMEOUT_DIS 0x0200 |
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#define MST_TIMEOUT_ENA 0x0100 |
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#define MST_RD_EOPB 0x0080 /* write-only */ |
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#define MST_RD_RESET 0x0040 |
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#define MST_WR_RESET 0x0020 |
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#define MST_RD_ENA 0x0004 /* 1:start, 0:ignore */ |
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#define MST_WR_ENA 0x0002 /* 1:start, 0:ignore */ |
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#define MST_CONNECTION 0x0001 /* 0 for ep1out/ep2in */ |
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#define MST_R_BITS (MST_EOPB_DIS|MST_EOPB_ENA \ |
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|MST_RD_ENA|MST_RD_RESET) |
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#define MST_W_BITS (MST_TIMEOUT_DIS|MST_TIMEOUT_ENA \ |
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|MST_WR_ENA|MST_WR_RESET) |
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#define MST_RW_BITS (MST_R_BITS|MST_W_BITS \ |
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|MST_CONNECTION) |
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/* these values assume (dma_master & MST_CONNECTION) == 0 */ |
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#define UDC_MSTWR_ENDPOINT 1 |
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#define UDC_MSTRD_ENDPOINT 2 |
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/* dma master write */ |
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u32 out_dma_start; |
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u32 out_dma_end; |
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u32 out_dma_current; |
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/* dma master read */ |
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u32 in_dma_start; |
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u32 in_dma_end; |
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u32 in_dma_current; |
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u32 power_detect; |
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#define PW_DETECT 0x04 |
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#define PW_RESETB 0x02 |
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#define PW_PULLUP 0x01 |
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u8 _reserved0 [0x1d8]; |
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/* endpoint registers */ |
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u32 ep_fifo [4]; /* 0x200 */ |
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u8 _reserved1 [0x10]; |
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u32 ep_mode [4]; /* only 1-3 valid */ |
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u8 _reserved2 [0x10]; |
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u32 ep_status [4]; |
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#define EPxSTATUS_TOGGLE 0x40 |
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#define EPxSTATUS_SUSPEND 0x20 |
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#define EPxSTATUS_EP_MASK (0x07<<2) |
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# define EPxSTATUS_EP_READY (0<<2) |
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# define EPxSTATUS_EP_DATAIN (1<<2) |
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# define EPxSTATUS_EP_FULL (2<<2) |
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# define EPxSTATUS_EP_TX_ERR (3<<2) |
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# define EPxSTATUS_EP_RX_ERR (4<<2) |
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# define EPxSTATUS_EP_BUSY (5<<2) |
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# define EPxSTATUS_EP_STALL (6<<2) |
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# define EPxSTATUS_EP_INVALID (7<<2) |
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#define EPxSTATUS_FIFO_DISABLE 0x02 |
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#define EPxSTATUS_STAGE_ERROR 0x01 |
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u8 _reserved3 [0x10]; |
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u32 EPxSizeLA[4]; |
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#define PACKET_ACTIVE (1<<7) |
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#define DATASIZE 0x7f |
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u8 _reserved3a [0x10]; |
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u32 EPxSizeLB[4]; /* only 1,2 valid */ |
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u8 _reserved3b [0x10]; |
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u32 EPxSizeHA[4]; /* only 1-3 valid */ |
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u8 _reserved3c [0x10]; |
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u32 EPxSizeHB[4]; /* only 1,2 valid */ |
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u8 _reserved4[0x30]; |
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/* SETUP packet contents */ |
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u32 bRequestType; /* 0x300 */ |
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u32 bRequest; |
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u32 wValueL; |
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u32 wValueH; |
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u32 wIndexL; |
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u32 wIndexH; |
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u32 wLengthL; |
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u32 wLengthH; |
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/* command interaction/handshaking */ |
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u32 SetupRecv; /* 0x320 */ |
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u32 CurrConfig; |
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u32 StdRequest; |
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u32 Request; |
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u32 DataSet; |
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#define DATASET_A(epnum) (1<<(2*(epnum))) |
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#define DATASET_B(epnum) (2<<(2*(epnum))) |
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#define DATASET_AB(epnum) (3<<(2*(epnum))) |
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u8 _reserved5[4]; |
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u32 UsbState; |
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#define USBSTATE_CONFIGURED 0x04 |
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#define USBSTATE_ADDRESSED 0x02 |
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#define USBSTATE_DEFAULT 0x01 |
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u32 EOP; |
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u32 Command; /* 0x340 */ |
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#define COMMAND_SETDATA0 2 |
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#define COMMAND_RESET 3 |
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#define COMMAND_STALL 4 |
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#define COMMAND_INVALID 5 |
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#define COMMAND_FIFO_DISABLE 7 |
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#define COMMAND_FIFO_ENABLE 8 |
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#define COMMAND_INIT_DESCRIPTOR 9 |
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#define COMMAND_FIFO_CLEAR 10 /* also stall */ |
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#define COMMAND_STALL_CLEAR 11 |
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#define COMMAND_EP(n) ((n) << 4) |
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u32 EPxSingle; |
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u8 _reserved6[4]; |
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u32 EPxBCS; |
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u8 _reserved7[8]; |
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u32 IntControl; |
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#define ICONTROL_STATUSNAK 1 |
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u8 _reserved8[4]; |
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u32 reqmode; // 0x360 standard request mode, low 8 bits |
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#define G_REQMODE_SET_INTF (1<<7) |
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#define G_REQMODE_GET_INTF (1<<6) |
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#define G_REQMODE_SET_CONF (1<<5) |
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#define G_REQMODE_GET_CONF (1<<4) |
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#define G_REQMODE_GET_DESC (1<<3) |
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#define G_REQMODE_SET_FEAT (1<<2) |
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#define G_REQMODE_CLEAR_FEAT (1<<1) |
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#define G_REQMODE_GET_STATUS (1<<0) |
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u32 ReqMode; |
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u8 _reserved9[0x18]; |
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u32 PortStatus; /* 0x380 */ |
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u8 _reserved10[8]; |
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u32 address; |
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u32 buff_test; |
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u8 _reserved11[4]; |
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u32 UsbReady; |
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u8 _reserved12[4]; |
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u32 SetDescStall; /* 0x3a0 */ |
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u8 _reserved13[0x45c]; |
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/* hardware could handle limited GET_DESCRIPTOR duties */ |
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#define DESC_LEN 0x80 |
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u32 descriptors[DESC_LEN]; /* 0x800 */ |
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u8 _reserved14[0x600]; |
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} __attribute__ ((packed)); |
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#define MAX_FIFO_SIZE 64 |
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#define MAX_EP0_SIZE 8 /* ep0 fifo is bigger, though */ |
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/*-------------------------------------------------------------------------*/ |
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/* DRIVER DATA STRUCTURES and UTILITIES */ |
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struct goku_ep { |
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struct usb_ep ep; |
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struct goku_udc *dev; |
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unsigned long irqs; |
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unsigned num:8, |
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dma:1, |
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is_in:1, |
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stopped:1; |
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/* analogous to a host-side qh */ |
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struct list_head queue; |
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u32 __iomem *reg_fifo; |
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u32 __iomem *reg_mode; |
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u32 __iomem *reg_status; |
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}; |
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struct goku_request { |
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struct usb_request req; |
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struct list_head queue; |
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unsigned mapped:1; |
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}; |
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enum ep0state { |
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EP0_DISCONNECT, /* no host */ |
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EP0_IDLE, /* between STATUS ack and SETUP report */ |
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EP0_IN, EP0_OUT, /* data stage */ |
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EP0_STATUS, /* status stage */ |
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EP0_STALL, /* data or status stages */ |
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EP0_SUSPEND, /* usb suspend */ |
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}; |
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struct goku_udc { |
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/* each pci device provides one gadget, several endpoints */ |
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struct usb_gadget gadget; |
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spinlock_t lock; |
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struct goku_ep ep[4]; |
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struct usb_gadget_driver *driver; |
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enum ep0state ep0state; |
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unsigned got_irq:1, |
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got_region:1, |
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req_config:1, |
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configured:1, |
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enabled:1; |
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/* pci state used to access those endpoints */ |
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struct pci_dev *pdev; |
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struct goku_udc_regs __iomem *regs; |
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u32 int_enable; |
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/* statistics... */ |
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unsigned long irqs; |
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}; |
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#define to_goku_udc(g) (container_of((g), struct goku_udc, gadget)) |
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/*-------------------------------------------------------------------------*/ |
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#define xprintk(dev,level,fmt,args...) \ |
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printk(level "%s %s: " fmt , driver_name , \ |
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pci_name(dev->pdev) , ## args) |
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#ifdef DEBUG |
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#define DBG(dev,fmt,args...) \ |
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xprintk(dev , KERN_DEBUG , fmt , ## args) |
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#else |
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#define DBG(dev,fmt,args...) \ |
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do { } while (0) |
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#endif /* DEBUG */ |
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#ifdef VERBOSE |
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#define VDBG DBG |
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#else |
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#define VDBG(dev,fmt,args...) \ |
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do { } while (0) |
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#endif /* VERBOSE */ |
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#define ERROR(dev,fmt,args...) \ |
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xprintk(dev , KERN_ERR , fmt , ## args) |
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#define WARNING(dev,fmt,args...) \ |
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xprintk(dev , KERN_WARNING , fmt , ## args) |
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#define INFO(dev,fmt,args...) \ |
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xprintk(dev , KERN_INFO , fmt , ## args) |
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