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257 lines
6.9 KiB
257 lines
6.9 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* Samsung SoC USB 1.1/2.0 PHY driver - Exynos 4210 support |
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* |
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* Copyright (C) 2013 Samsung Electronics Co., Ltd. |
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* Author: Kamil Debski <[email protected]> |
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*/ |
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#include <linux/delay.h> |
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#include <linux/io.h> |
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#include <linux/phy/phy.h> |
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#include <linux/regmap.h> |
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#include "phy-samsung-usb2.h" |
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/* Exynos USB PHY registers */ |
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/* PHY power control */ |
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#define EXYNOS_4210_UPHYPWR 0x0 |
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#define EXYNOS_4210_UPHYPWR_PHY0_SUSPEND BIT(0) |
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#define EXYNOS_4210_UPHYPWR_PHY0_PWR BIT(3) |
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#define EXYNOS_4210_UPHYPWR_PHY0_OTG_PWR BIT(4) |
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#define EXYNOS_4210_UPHYPWR_PHY0_SLEEP BIT(5) |
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#define EXYNOS_4210_UPHYPWR_PHY0 ( \ |
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EXYNOS_4210_UPHYPWR_PHY0_SUSPEND | \ |
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EXYNOS_4210_UPHYPWR_PHY0_PWR | \ |
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EXYNOS_4210_UPHYPWR_PHY0_OTG_PWR | \ |
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EXYNOS_4210_UPHYPWR_PHY0_SLEEP) |
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#define EXYNOS_4210_UPHYPWR_PHY1_SUSPEND BIT(6) |
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#define EXYNOS_4210_UPHYPWR_PHY1_PWR BIT(7) |
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#define EXYNOS_4210_UPHYPWR_PHY1_SLEEP BIT(8) |
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#define EXYNOS_4210_UPHYPWR_PHY1 ( \ |
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EXYNOS_4210_UPHYPWR_PHY1_SUSPEND | \ |
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EXYNOS_4210_UPHYPWR_PHY1_PWR | \ |
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EXYNOS_4210_UPHYPWR_PHY1_SLEEP) |
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#define EXYNOS_4210_UPHYPWR_HSIC0_SUSPEND BIT(9) |
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#define EXYNOS_4210_UPHYPWR_HSIC0_SLEEP BIT(10) |
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#define EXYNOS_4210_UPHYPWR_HSIC0 ( \ |
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EXYNOS_4210_UPHYPWR_HSIC0_SUSPEND | \ |
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EXYNOS_4210_UPHYPWR_HSIC0_SLEEP) |
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#define EXYNOS_4210_UPHYPWR_HSIC1_SUSPEND BIT(11) |
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#define EXYNOS_4210_UPHYPWR_HSIC1_SLEEP BIT(12) |
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#define EXYNOS_4210_UPHYPWR_HSIC1 ( \ |
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EXYNOS_4210_UPHYPWR_HSIC1_SUSPEND | \ |
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EXYNOS_4210_UPHYPWR_HSIC1_SLEEP) |
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/* PHY clock control */ |
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#define EXYNOS_4210_UPHYCLK 0x4 |
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#define EXYNOS_4210_UPHYCLK_PHYFSEL_MASK (0x3 << 0) |
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#define EXYNOS_4210_UPHYCLK_PHYFSEL_OFFSET 0 |
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#define EXYNOS_4210_UPHYCLK_PHYFSEL_48MHZ (0x0 << 0) |
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#define EXYNOS_4210_UPHYCLK_PHYFSEL_24MHZ (0x3 << 0) |
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#define EXYNOS_4210_UPHYCLK_PHYFSEL_12MHZ (0x2 << 0) |
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#define EXYNOS_4210_UPHYCLK_PHY0_ID_PULLUP BIT(2) |
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#define EXYNOS_4210_UPHYCLK_PHY0_COMMON_ON BIT(4) |
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#define EXYNOS_4210_UPHYCLK_PHY1_COMMON_ON BIT(7) |
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/* PHY reset control */ |
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#define EXYNOS_4210_UPHYRST 0x8 |
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#define EXYNOS_4210_URSTCON_PHY0 BIT(0) |
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#define EXYNOS_4210_URSTCON_OTG_HLINK BIT(1) |
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#define EXYNOS_4210_URSTCON_OTG_PHYLINK BIT(2) |
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#define EXYNOS_4210_URSTCON_PHY1_ALL BIT(3) |
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#define EXYNOS_4210_URSTCON_PHY1_P0 BIT(4) |
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#define EXYNOS_4210_URSTCON_PHY1_P1P2 BIT(5) |
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#define EXYNOS_4210_URSTCON_HOST_LINK_ALL BIT(6) |
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#define EXYNOS_4210_URSTCON_HOST_LINK_P0 BIT(7) |
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#define EXYNOS_4210_URSTCON_HOST_LINK_P1 BIT(8) |
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#define EXYNOS_4210_URSTCON_HOST_LINK_P2 BIT(9) |
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/* Isolation, configured in the power management unit */ |
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#define EXYNOS_4210_USB_ISOL_DEVICE_OFFSET 0x704 |
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#define EXYNOS_4210_USB_ISOL_DEVICE BIT(0) |
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#define EXYNOS_4210_USB_ISOL_HOST_OFFSET 0x708 |
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#define EXYNOS_4210_USB_ISOL_HOST BIT(0) |
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/* USBYPHY1 Floating prevention */ |
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#define EXYNOS_4210_UPHY1CON 0x34 |
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#define EXYNOS_4210_UPHY1CON_FLOAT_PREVENTION 0x1 |
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/* Mode switching SUB Device <-> Host */ |
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#define EXYNOS_4210_MODE_SWITCH_OFFSET 0x21c |
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#define EXYNOS_4210_MODE_SWITCH_MASK 1 |
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#define EXYNOS_4210_MODE_SWITCH_DEVICE 0 |
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#define EXYNOS_4210_MODE_SWITCH_HOST 1 |
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enum exynos4210_phy_id { |
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EXYNOS4210_DEVICE, |
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EXYNOS4210_HOST, |
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EXYNOS4210_HSIC0, |
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EXYNOS4210_HSIC1, |
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EXYNOS4210_NUM_PHYS, |
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}; |
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/* |
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* exynos4210_rate_to_clk() converts the supplied clock rate to the value that |
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* can be written to the phy register. |
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*/ |
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static int exynos4210_rate_to_clk(unsigned long rate, u32 *reg) |
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{ |
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switch (rate) { |
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case 12 * MHZ: |
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*reg = EXYNOS_4210_UPHYCLK_PHYFSEL_12MHZ; |
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break; |
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case 24 * MHZ: |
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*reg = EXYNOS_4210_UPHYCLK_PHYFSEL_24MHZ; |
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break; |
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case 48 * MHZ: |
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*reg = EXYNOS_4210_UPHYCLK_PHYFSEL_48MHZ; |
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break; |
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default: |
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return -EINVAL; |
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} |
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return 0; |
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} |
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static void exynos4210_isol(struct samsung_usb2_phy_instance *inst, bool on) |
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{ |
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struct samsung_usb2_phy_driver *drv = inst->drv; |
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u32 offset; |
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u32 mask; |
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switch (inst->cfg->id) { |
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case EXYNOS4210_DEVICE: |
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offset = EXYNOS_4210_USB_ISOL_DEVICE_OFFSET; |
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mask = EXYNOS_4210_USB_ISOL_DEVICE; |
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break; |
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case EXYNOS4210_HOST: |
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offset = EXYNOS_4210_USB_ISOL_HOST_OFFSET; |
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mask = EXYNOS_4210_USB_ISOL_HOST; |
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break; |
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default: |
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return; |
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} |
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regmap_update_bits(drv->reg_pmu, offset, mask, on ? 0 : mask); |
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} |
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static void exynos4210_phy_pwr(struct samsung_usb2_phy_instance *inst, bool on) |
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{ |
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struct samsung_usb2_phy_driver *drv = inst->drv; |
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u32 rstbits = 0; |
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u32 phypwr = 0; |
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u32 rst; |
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u32 pwr; |
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u32 clk; |
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switch (inst->cfg->id) { |
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case EXYNOS4210_DEVICE: |
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phypwr = EXYNOS_4210_UPHYPWR_PHY0; |
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rstbits = EXYNOS_4210_URSTCON_PHY0; |
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break; |
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case EXYNOS4210_HOST: |
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phypwr = EXYNOS_4210_UPHYPWR_PHY1; |
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rstbits = EXYNOS_4210_URSTCON_PHY1_ALL | |
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EXYNOS_4210_URSTCON_PHY1_P0 | |
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EXYNOS_4210_URSTCON_PHY1_P1P2 | |
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EXYNOS_4210_URSTCON_HOST_LINK_ALL | |
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EXYNOS_4210_URSTCON_HOST_LINK_P0; |
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writel(on, drv->reg_phy + EXYNOS_4210_UPHY1CON); |
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break; |
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case EXYNOS4210_HSIC0: |
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phypwr = EXYNOS_4210_UPHYPWR_HSIC0; |
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rstbits = EXYNOS_4210_URSTCON_PHY1_P1P2 | |
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EXYNOS_4210_URSTCON_HOST_LINK_P1; |
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break; |
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case EXYNOS4210_HSIC1: |
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phypwr = EXYNOS_4210_UPHYPWR_HSIC1; |
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rstbits = EXYNOS_4210_URSTCON_PHY1_P1P2 | |
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EXYNOS_4210_URSTCON_HOST_LINK_P2; |
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break; |
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} |
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if (on) { |
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clk = readl(drv->reg_phy + EXYNOS_4210_UPHYCLK); |
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clk &= ~EXYNOS_4210_UPHYCLK_PHYFSEL_MASK; |
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clk |= drv->ref_reg_val << EXYNOS_4210_UPHYCLK_PHYFSEL_OFFSET; |
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writel(clk, drv->reg_phy + EXYNOS_4210_UPHYCLK); |
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pwr = readl(drv->reg_phy + EXYNOS_4210_UPHYPWR); |
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pwr &= ~phypwr; |
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writel(pwr, drv->reg_phy + EXYNOS_4210_UPHYPWR); |
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rst = readl(drv->reg_phy + EXYNOS_4210_UPHYRST); |
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rst |= rstbits; |
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writel(rst, drv->reg_phy + EXYNOS_4210_UPHYRST); |
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udelay(10); |
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rst &= ~rstbits; |
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writel(rst, drv->reg_phy + EXYNOS_4210_UPHYRST); |
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/* The following delay is necessary for the reset sequence to be |
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* completed */ |
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udelay(80); |
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} else { |
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pwr = readl(drv->reg_phy + EXYNOS_4210_UPHYPWR); |
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pwr |= phypwr; |
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writel(pwr, drv->reg_phy + EXYNOS_4210_UPHYPWR); |
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} |
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} |
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static int exynos4210_power_on(struct samsung_usb2_phy_instance *inst) |
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{ |
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/* Order of initialisation is important - first power then isolation */ |
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exynos4210_phy_pwr(inst, 1); |
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exynos4210_isol(inst, 0); |
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return 0; |
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} |
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static int exynos4210_power_off(struct samsung_usb2_phy_instance *inst) |
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{ |
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exynos4210_isol(inst, 1); |
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exynos4210_phy_pwr(inst, 0); |
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return 0; |
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} |
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static const struct samsung_usb2_common_phy exynos4210_phys[] = { |
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{ |
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.label = "device", |
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.id = EXYNOS4210_DEVICE, |
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.power_on = exynos4210_power_on, |
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.power_off = exynos4210_power_off, |
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}, |
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{ |
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.label = "host", |
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.id = EXYNOS4210_HOST, |
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.power_on = exynos4210_power_on, |
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.power_off = exynos4210_power_off, |
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}, |
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{ |
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.label = "hsic0", |
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.id = EXYNOS4210_HSIC0, |
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.power_on = exynos4210_power_on, |
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.power_off = exynos4210_power_off, |
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}, |
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{ |
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.label = "hsic1", |
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.id = EXYNOS4210_HSIC1, |
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.power_on = exynos4210_power_on, |
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.power_off = exynos4210_power_off, |
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}, |
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}; |
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const struct samsung_usb2_phy_config exynos4210_usb2_phy_config = { |
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.has_mode_switch = 0, |
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.num_phys = EXYNOS4210_NUM_PHYS, |
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.phys = exynos4210_phys, |
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.rate_to_clk = exynos4210_rate_to_clk, |
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};
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