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209 lines
5.2 KiB
209 lines
5.2 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* Copyright (C) 2015 Linaro, Ltd. |
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* Rob Herring <[email protected]> |
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* |
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* Based on vendor driver: |
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* Copyright (C) 2013 Marvell Inc. |
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* Author: Chao Xie <[email protected]> |
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*/ |
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#include <linux/delay.h> |
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#include <linux/slab.h> |
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#include <linux/of.h> |
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#include <linux/io.h> |
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#include <linux/iopoll.h> |
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#include <linux/err.h> |
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#include <linux/clk.h> |
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#include <linux/module.h> |
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#include <linux/platform_device.h> |
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#include <linux/phy/phy.h> |
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#define PHY_28NM_HSIC_CTRL 0x08 |
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#define PHY_28NM_HSIC_IMPCAL_CAL 0x18 |
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#define PHY_28NM_HSIC_PLL_CTRL01 0x1c |
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#define PHY_28NM_HSIC_PLL_CTRL2 0x20 |
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#define PHY_28NM_HSIC_INT 0x28 |
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#define PHY_28NM_HSIC_PLL_SELLPFR_SHIFT 26 |
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#define PHY_28NM_HSIC_PLL_FBDIV_SHIFT 0 |
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#define PHY_28NM_HSIC_PLL_REFDIV_SHIFT 9 |
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#define PHY_28NM_HSIC_S2H_PU_PLL BIT(10) |
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#define PHY_28NM_HSIC_H2S_PLL_LOCK BIT(15) |
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#define PHY_28NM_HSIC_S2H_HSIC_EN BIT(7) |
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#define S2H_DRV_SE0_4RESUME BIT(14) |
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#define PHY_28NM_HSIC_H2S_IMPCAL_DONE BIT(27) |
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#define PHY_28NM_HSIC_CONNECT_INT BIT(1) |
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#define PHY_28NM_HSIC_HS_READY_INT BIT(2) |
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struct mv_hsic_phy { |
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struct phy *phy; |
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struct platform_device *pdev; |
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void __iomem *base; |
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struct clk *clk; |
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}; |
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static int wait_for_reg(void __iomem *reg, u32 mask, u32 ms) |
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{ |
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u32 val; |
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return readl_poll_timeout(reg, val, ((val & mask) == mask), |
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1000, 1000 * ms); |
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} |
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static int mv_hsic_phy_init(struct phy *phy) |
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{ |
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struct mv_hsic_phy *mv_phy = phy_get_drvdata(phy); |
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struct platform_device *pdev = mv_phy->pdev; |
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void __iomem *base = mv_phy->base; |
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int ret; |
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clk_prepare_enable(mv_phy->clk); |
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/* Set reference clock */ |
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writel(0x1 << PHY_28NM_HSIC_PLL_SELLPFR_SHIFT | |
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0xf0 << PHY_28NM_HSIC_PLL_FBDIV_SHIFT | |
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0xd << PHY_28NM_HSIC_PLL_REFDIV_SHIFT, |
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base + PHY_28NM_HSIC_PLL_CTRL01); |
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/* Turn on PLL */ |
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writel(readl(base + PHY_28NM_HSIC_PLL_CTRL2) | |
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PHY_28NM_HSIC_S2H_PU_PLL, |
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base + PHY_28NM_HSIC_PLL_CTRL2); |
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/* Make sure PHY PLL is locked */ |
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ret = wait_for_reg(base + PHY_28NM_HSIC_PLL_CTRL2, |
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PHY_28NM_HSIC_H2S_PLL_LOCK, 100); |
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if (ret) { |
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dev_err(&pdev->dev, "HSIC PHY PLL not locked after 100mS."); |
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clk_disable_unprepare(mv_phy->clk); |
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} |
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return ret; |
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} |
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static int mv_hsic_phy_power_on(struct phy *phy) |
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{ |
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struct mv_hsic_phy *mv_phy = phy_get_drvdata(phy); |
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struct platform_device *pdev = mv_phy->pdev; |
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void __iomem *base = mv_phy->base; |
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u32 reg; |
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int ret; |
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reg = readl(base + PHY_28NM_HSIC_CTRL); |
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/* Avoid SE0 state when resume for some device will take it as reset */ |
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reg &= ~S2H_DRV_SE0_4RESUME; |
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reg |= PHY_28NM_HSIC_S2H_HSIC_EN; /* Enable HSIC PHY */ |
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writel(reg, base + PHY_28NM_HSIC_CTRL); |
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/* |
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* Calibration Timing |
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* ____________________________ |
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* CAL START ___| |
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* ____________________ |
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* CAL_DONE ___________| |
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* | 400us | |
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*/ |
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/* Make sure PHY Calibration is ready */ |
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ret = wait_for_reg(base + PHY_28NM_HSIC_IMPCAL_CAL, |
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PHY_28NM_HSIC_H2S_IMPCAL_DONE, 100); |
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if (ret) { |
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dev_warn(&pdev->dev, "HSIC PHY READY not set after 100mS."); |
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return ret; |
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} |
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/* Waiting for HSIC connect int*/ |
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ret = wait_for_reg(base + PHY_28NM_HSIC_INT, |
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PHY_28NM_HSIC_CONNECT_INT, 200); |
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if (ret) |
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dev_warn(&pdev->dev, "HSIC wait for connect interrupt timeout."); |
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return ret; |
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} |
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static int mv_hsic_phy_power_off(struct phy *phy) |
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{ |
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struct mv_hsic_phy *mv_phy = phy_get_drvdata(phy); |
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void __iomem *base = mv_phy->base; |
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writel(readl(base + PHY_28NM_HSIC_CTRL) & ~PHY_28NM_HSIC_S2H_HSIC_EN, |
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base + PHY_28NM_HSIC_CTRL); |
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return 0; |
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} |
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static int mv_hsic_phy_exit(struct phy *phy) |
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{ |
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struct mv_hsic_phy *mv_phy = phy_get_drvdata(phy); |
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void __iomem *base = mv_phy->base; |
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/* Turn off PLL */ |
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writel(readl(base + PHY_28NM_HSIC_PLL_CTRL2) & |
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~PHY_28NM_HSIC_S2H_PU_PLL, |
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base + PHY_28NM_HSIC_PLL_CTRL2); |
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clk_disable_unprepare(mv_phy->clk); |
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return 0; |
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} |
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static const struct phy_ops hsic_ops = { |
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.init = mv_hsic_phy_init, |
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.power_on = mv_hsic_phy_power_on, |
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.power_off = mv_hsic_phy_power_off, |
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.exit = mv_hsic_phy_exit, |
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.owner = THIS_MODULE, |
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}; |
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static int mv_hsic_phy_probe(struct platform_device *pdev) |
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{ |
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struct phy_provider *phy_provider; |
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struct mv_hsic_phy *mv_phy; |
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mv_phy = devm_kzalloc(&pdev->dev, sizeof(*mv_phy), GFP_KERNEL); |
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if (!mv_phy) |
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return -ENOMEM; |
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mv_phy->pdev = pdev; |
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mv_phy->clk = devm_clk_get(&pdev->dev, NULL); |
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if (IS_ERR(mv_phy->clk)) { |
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dev_err(&pdev->dev, "failed to get clock.\n"); |
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return PTR_ERR(mv_phy->clk); |
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} |
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mv_phy->base = devm_platform_ioremap_resource(pdev, 0); |
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if (IS_ERR(mv_phy->base)) |
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return PTR_ERR(mv_phy->base); |
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mv_phy->phy = devm_phy_create(&pdev->dev, pdev->dev.of_node, &hsic_ops); |
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if (IS_ERR(mv_phy->phy)) |
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return PTR_ERR(mv_phy->phy); |
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phy_set_drvdata(mv_phy->phy, mv_phy); |
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phy_provider = devm_of_phy_provider_register(&pdev->dev, of_phy_simple_xlate); |
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return PTR_ERR_OR_ZERO(phy_provider); |
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} |
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static const struct of_device_id mv_hsic_phy_dt_match[] = { |
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{ .compatible = "marvell,pxa1928-hsic-phy", }, |
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{}, |
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}; |
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MODULE_DEVICE_TABLE(of, mv_hsic_phy_dt_match); |
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static struct platform_driver mv_hsic_phy_driver = { |
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.probe = mv_hsic_phy_probe, |
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.driver = { |
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.name = "mv-hsic-phy", |
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.of_match_table = of_match_ptr(mv_hsic_phy_dt_match), |
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}, |
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}; |
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module_platform_driver(mv_hsic_phy_driver); |
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MODULE_AUTHOR("Rob Herring <[email protected]>"); |
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MODULE_DESCRIPTION("Marvell HSIC phy driver"); |
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MODULE_LICENSE("GPL v2");
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