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358 lines
8.1 KiB
358 lines
8.1 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* ACPI probing code for ARM performance counters. |
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* |
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* Copyright (C) 2017 ARM Ltd. |
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*/ |
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#include <linux/acpi.h> |
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#include <linux/cpumask.h> |
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#include <linux/init.h> |
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#include <linux/irq.h> |
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#include <linux/irqdesc.h> |
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#include <linux/percpu.h> |
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#include <linux/perf/arm_pmu.h> |
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#include <asm/cputype.h> |
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static DEFINE_PER_CPU(struct arm_pmu *, probed_pmus); |
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static DEFINE_PER_CPU(int, pmu_irqs); |
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static int arm_pmu_acpi_register_irq(int cpu) |
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{ |
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struct acpi_madt_generic_interrupt *gicc; |
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int gsi, trigger; |
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gicc = acpi_cpu_get_madt_gicc(cpu); |
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gsi = gicc->performance_interrupt; |
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/* |
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* Per the ACPI spec, the MADT cannot describe a PMU that doesn't |
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* have an interrupt. QEMU advertises this by using a GSI of zero, |
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* which is not known to be valid on any hardware despite being |
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* valid per the spec. Take the pragmatic approach and reject a |
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* GSI of zero for now. |
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*/ |
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if (!gsi) |
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return 0; |
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if (gicc->flags & ACPI_MADT_PERFORMANCE_IRQ_MODE) |
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trigger = ACPI_EDGE_SENSITIVE; |
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else |
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trigger = ACPI_LEVEL_SENSITIVE; |
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/* |
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* Helpfully, the MADT GICC doesn't have a polarity flag for the |
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* "performance interrupt". Luckily, on compliant GICs the polarity is |
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* a fixed value in HW (for both SPIs and PPIs) that we cannot change |
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* from SW. |
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* |
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* Here we pass in ACPI_ACTIVE_HIGH to keep the core code happy. This |
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* may not match the real polarity, but that should not matter. |
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* |
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* Other interrupt controllers are not supported with ACPI. |
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*/ |
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return acpi_register_gsi(NULL, gsi, trigger, ACPI_ACTIVE_HIGH); |
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} |
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static void arm_pmu_acpi_unregister_irq(int cpu) |
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{ |
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struct acpi_madt_generic_interrupt *gicc; |
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int gsi; |
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gicc = acpi_cpu_get_madt_gicc(cpu); |
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gsi = gicc->performance_interrupt; |
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if (gsi) |
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acpi_unregister_gsi(gsi); |
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} |
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#if IS_ENABLED(CONFIG_ARM_SPE_PMU) |
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static struct resource spe_resources[] = { |
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{ |
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/* irq */ |
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.flags = IORESOURCE_IRQ, |
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} |
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}; |
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static struct platform_device spe_dev = { |
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.name = ARMV8_SPE_PDEV_NAME, |
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.id = -1, |
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.resource = spe_resources, |
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.num_resources = ARRAY_SIZE(spe_resources) |
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}; |
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/* |
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* For lack of a better place, hook the normal PMU MADT walk |
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* and create a SPE device if we detect a recent MADT with |
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* a homogeneous PPI mapping. |
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*/ |
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static void arm_spe_acpi_register_device(void) |
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{ |
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int cpu, hetid, irq, ret; |
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bool first = true; |
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u16 gsi = 0; |
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/* |
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* Sanity check all the GICC tables for the same interrupt number. |
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* For now, we only support homogeneous ACPI/SPE machines. |
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*/ |
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for_each_possible_cpu(cpu) { |
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struct acpi_madt_generic_interrupt *gicc; |
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gicc = acpi_cpu_get_madt_gicc(cpu); |
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if (gicc->header.length < ACPI_MADT_GICC_SPE) |
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return; |
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if (first) { |
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gsi = gicc->spe_interrupt; |
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if (!gsi) |
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return; |
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hetid = find_acpi_cpu_topology_hetero_id(cpu); |
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first = false; |
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} else if ((gsi != gicc->spe_interrupt) || |
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(hetid != find_acpi_cpu_topology_hetero_id(cpu))) { |
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pr_warn("ACPI: SPE must be homogeneous\n"); |
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return; |
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} |
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} |
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irq = acpi_register_gsi(NULL, gsi, ACPI_LEVEL_SENSITIVE, |
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ACPI_ACTIVE_HIGH); |
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if (irq < 0) { |
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pr_warn("ACPI: SPE Unable to register interrupt: %d\n", gsi); |
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return; |
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} |
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spe_resources[0].start = irq; |
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ret = platform_device_register(&spe_dev); |
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if (ret < 0) { |
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pr_warn("ACPI: SPE: Unable to register device\n"); |
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acpi_unregister_gsi(gsi); |
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} |
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} |
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#else |
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static inline void arm_spe_acpi_register_device(void) |
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{ |
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} |
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#endif /* CONFIG_ARM_SPE_PMU */ |
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static int arm_pmu_acpi_parse_irqs(void) |
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{ |
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int irq, cpu, irq_cpu, err; |
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for_each_possible_cpu(cpu) { |
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irq = arm_pmu_acpi_register_irq(cpu); |
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if (irq < 0) { |
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err = irq; |
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pr_warn("Unable to parse ACPI PMU IRQ for CPU%d: %d\n", |
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cpu, err); |
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goto out_err; |
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} else if (irq == 0) { |
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pr_warn("No ACPI PMU IRQ for CPU%d\n", cpu); |
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} |
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/* |
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* Log and request the IRQ so the core arm_pmu code can manage |
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* it. We'll have to sanity-check IRQs later when we associate |
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* them with their PMUs. |
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*/ |
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per_cpu(pmu_irqs, cpu) = irq; |
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armpmu_request_irq(irq, cpu); |
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} |
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return 0; |
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out_err: |
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for_each_possible_cpu(cpu) { |
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irq = per_cpu(pmu_irqs, cpu); |
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if (!irq) |
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continue; |
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arm_pmu_acpi_unregister_irq(cpu); |
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/* |
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* Blat all copies of the IRQ so that we only unregister the |
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* corresponding GSI once (e.g. when we have PPIs). |
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*/ |
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for_each_possible_cpu(irq_cpu) { |
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if (per_cpu(pmu_irqs, irq_cpu) == irq) |
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per_cpu(pmu_irqs, irq_cpu) = 0; |
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} |
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} |
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return err; |
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} |
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static struct arm_pmu *arm_pmu_acpi_find_alloc_pmu(void) |
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{ |
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unsigned long cpuid = read_cpuid_id(); |
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struct arm_pmu *pmu; |
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int cpu; |
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for_each_possible_cpu(cpu) { |
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pmu = per_cpu(probed_pmus, cpu); |
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if (!pmu || pmu->acpi_cpuid != cpuid) |
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continue; |
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return pmu; |
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} |
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pmu = armpmu_alloc_atomic(); |
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if (!pmu) { |
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pr_warn("Unable to allocate PMU for CPU%d\n", |
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smp_processor_id()); |
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return NULL; |
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} |
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pmu->acpi_cpuid = cpuid; |
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return pmu; |
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} |
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/* |
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* Check whether the new IRQ is compatible with those already associated with |
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* the PMU (e.g. we don't have mismatched PPIs). |
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*/ |
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static bool pmu_irq_matches(struct arm_pmu *pmu, int irq) |
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{ |
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struct pmu_hw_events __percpu *hw_events = pmu->hw_events; |
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int cpu; |
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if (!irq) |
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return true; |
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for_each_cpu(cpu, &pmu->supported_cpus) { |
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int other_irq = per_cpu(hw_events->irq, cpu); |
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if (!other_irq) |
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continue; |
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if (irq == other_irq) |
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continue; |
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if (!irq_is_percpu_devid(irq) && !irq_is_percpu_devid(other_irq)) |
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continue; |
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pr_warn("mismatched PPIs detected\n"); |
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return false; |
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} |
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return true; |
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} |
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/* |
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* This must run before the common arm_pmu hotplug logic, so that we can |
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* associate a CPU and its interrupt before the common code tries to manage the |
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* affinity and so on. |
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* |
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* Note that hotplug events are serialized, so we cannot race with another CPU |
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* coming up. The perf core won't open events while a hotplug event is in |
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* progress. |
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*/ |
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static int arm_pmu_acpi_cpu_starting(unsigned int cpu) |
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{ |
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struct arm_pmu *pmu; |
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struct pmu_hw_events __percpu *hw_events; |
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int irq; |
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/* If we've already probed this CPU, we have nothing to do */ |
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if (per_cpu(probed_pmus, cpu)) |
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return 0; |
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irq = per_cpu(pmu_irqs, cpu); |
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pmu = arm_pmu_acpi_find_alloc_pmu(); |
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if (!pmu) |
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return -ENOMEM; |
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per_cpu(probed_pmus, cpu) = pmu; |
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if (pmu_irq_matches(pmu, irq)) { |
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hw_events = pmu->hw_events; |
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per_cpu(hw_events->irq, cpu) = irq; |
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} |
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cpumask_set_cpu(cpu, &pmu->supported_cpus); |
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/* |
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* Ideally, we'd probe the PMU here when we find the first matching |
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* CPU. We can't do that for several reasons; see the comment in |
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* arm_pmu_acpi_init(). |
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* |
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* So for the time being, we're done. |
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*/ |
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return 0; |
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} |
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int arm_pmu_acpi_probe(armpmu_init_fn init_fn) |
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{ |
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int pmu_idx = 0; |
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int cpu, ret; |
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/* |
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* Initialise and register the set of PMUs which we know about right |
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* now. Ideally we'd do this in arm_pmu_acpi_cpu_starting() so that we |
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* could handle late hotplug, but this may lead to deadlock since we |
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* might try to register a hotplug notifier instance from within a |
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* hotplug notifier. |
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* |
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* There's also the problem of having access to the right init_fn, |
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* without tying this too deeply into the "real" PMU driver. |
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* |
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* For the moment, as with the platform/DT case, we need at least one |
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* of a PMU's CPUs to be online at probe time. |
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*/ |
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for_each_possible_cpu(cpu) { |
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struct arm_pmu *pmu = per_cpu(probed_pmus, cpu); |
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char *base_name; |
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if (!pmu || pmu->name) |
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continue; |
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ret = init_fn(pmu); |
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if (ret == -ENODEV) { |
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/* PMU not handled by this driver, or not present */ |
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continue; |
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} else if (ret) { |
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pr_warn("Unable to initialise PMU for CPU%d\n", cpu); |
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return ret; |
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} |
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base_name = pmu->name; |
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pmu->name = kasprintf(GFP_KERNEL, "%s_%d", base_name, pmu_idx++); |
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if (!pmu->name) { |
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pr_warn("Unable to allocate PMU name for CPU%d\n", cpu); |
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return -ENOMEM; |
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} |
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ret = armpmu_register(pmu); |
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if (ret) { |
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pr_warn("Failed to register PMU for CPU%d\n", cpu); |
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kfree(pmu->name); |
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return ret; |
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} |
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} |
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return 0; |
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} |
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static int arm_pmu_acpi_init(void) |
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{ |
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int ret; |
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if (acpi_disabled) |
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return 0; |
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arm_spe_acpi_register_device(); |
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ret = arm_pmu_acpi_parse_irqs(); |
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if (ret) |
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return ret; |
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ret = cpuhp_setup_state(CPUHP_AP_PERF_ARM_ACPI_STARTING, |
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"perf/arm/pmu_acpi:starting", |
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arm_pmu_acpi_cpu_starting, NULL); |
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return ret; |
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} |
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subsys_initcall(arm_pmu_acpi_init)
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