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641 lines
16 KiB
641 lines
16 KiB
// SPDX-License-Identifier: GPL-2.0+ |
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/** |
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* APM X-Gene PCIe Driver |
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* |
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* Copyright (c) 2014 Applied Micro Circuits Corporation. |
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* |
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* Author: Tanmay Inamdar <[email protected]>. |
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*/ |
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#include <linux/clk.h> |
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#include <linux/delay.h> |
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#include <linux/io.h> |
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#include <linux/jiffies.h> |
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#include <linux/memblock.h> |
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#include <linux/init.h> |
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#include <linux/of.h> |
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#include <linux/of_address.h> |
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#include <linux/of_irq.h> |
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#include <linux/of_pci.h> |
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#include <linux/pci.h> |
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#include <linux/pci-acpi.h> |
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#include <linux/pci-ecam.h> |
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#include <linux/platform_device.h> |
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#include <linux/slab.h> |
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|
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#include "../pci.h" |
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|
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#define PCIECORE_CTLANDSTATUS 0x50 |
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#define PIM1_1L 0x80 |
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#define IBAR2 0x98 |
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#define IR2MSK 0x9c |
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#define PIM2_1L 0xa0 |
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#define IBAR3L 0xb4 |
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#define IR3MSKL 0xbc |
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#define PIM3_1L 0xc4 |
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#define OMR1BARL 0x100 |
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#define OMR2BARL 0x118 |
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#define OMR3BARL 0x130 |
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#define CFGBARL 0x154 |
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#define CFGBARH 0x158 |
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#define CFGCTL 0x15c |
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#define RTDID 0x160 |
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#define BRIDGE_CFG_0 0x2000 |
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#define BRIDGE_CFG_4 0x2010 |
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#define BRIDGE_STATUS_0 0x2600 |
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#define LINK_UP_MASK 0x00000100 |
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#define AXI_EP_CFG_ACCESS 0x10000 |
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#define EN_COHERENCY 0xF0000000 |
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#define EN_REG 0x00000001 |
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#define OB_LO_IO 0x00000002 |
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#define XGENE_PCIE_VENDORID 0x10E8 |
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#define XGENE_PCIE_DEVICEID 0xE004 |
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#define SZ_1T (SZ_1G*1024ULL) |
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#define PIPE_PHY_RATE_RD(src) ((0xc000 & (u32)(src)) >> 0xe) |
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#define XGENE_V1_PCI_EXP_CAP 0x40 |
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|
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/* PCIe IP version */ |
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#define XGENE_PCIE_IP_VER_UNKN 0 |
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#define XGENE_PCIE_IP_VER_1 1 |
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#define XGENE_PCIE_IP_VER_2 2 |
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#if defined(CONFIG_PCI_XGENE) || (defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS)) |
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struct xgene_pcie_port { |
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struct device_node *node; |
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struct device *dev; |
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struct clk *clk; |
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void __iomem *csr_base; |
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void __iomem *cfg_base; |
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unsigned long cfg_addr; |
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bool link_up; |
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u32 version; |
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}; |
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static u32 xgene_pcie_readl(struct xgene_pcie_port *port, u32 reg) |
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{ |
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return readl(port->csr_base + reg); |
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} |
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static void xgene_pcie_writel(struct xgene_pcie_port *port, u32 reg, u32 val) |
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{ |
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writel(val, port->csr_base + reg); |
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} |
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static inline u32 pcie_bar_low_val(u32 addr, u32 flags) |
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{ |
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return (addr & PCI_BASE_ADDRESS_MEM_MASK) | flags; |
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} |
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static inline struct xgene_pcie_port *pcie_bus_to_port(struct pci_bus *bus) |
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{ |
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struct pci_config_window *cfg; |
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if (acpi_disabled) |
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return (struct xgene_pcie_port *)(bus->sysdata); |
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cfg = bus->sysdata; |
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return (struct xgene_pcie_port *)(cfg->priv); |
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} |
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|
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/* |
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* When the address bit [17:16] is 2'b01, the Configuration access will be |
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* treated as Type 1 and it will be forwarded to external PCIe device. |
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*/ |
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static void __iomem *xgene_pcie_get_cfg_base(struct pci_bus *bus) |
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{ |
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struct xgene_pcie_port *port = pcie_bus_to_port(bus); |
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if (bus->number >= (bus->primary + 1)) |
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return port->cfg_base + AXI_EP_CFG_ACCESS; |
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return port->cfg_base; |
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} |
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/* |
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* For Configuration request, RTDID register is used as Bus Number, |
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* Device Number and Function number of the header fields. |
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*/ |
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static void xgene_pcie_set_rtdid_reg(struct pci_bus *bus, uint devfn) |
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{ |
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struct xgene_pcie_port *port = pcie_bus_to_port(bus); |
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unsigned int b, d, f; |
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u32 rtdid_val = 0; |
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b = bus->number; |
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d = PCI_SLOT(devfn); |
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f = PCI_FUNC(devfn); |
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if (!pci_is_root_bus(bus)) |
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rtdid_val = (b << 8) | (d << 3) | f; |
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xgene_pcie_writel(port, RTDID, rtdid_val); |
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/* read the register back to ensure flush */ |
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xgene_pcie_readl(port, RTDID); |
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} |
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/* |
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* X-Gene PCIe port uses BAR0-BAR1 of RC's configuration space as |
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* the translation from PCI bus to native BUS. Entire DDR region |
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* is mapped into PCIe space using these registers, so it can be |
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* reached by DMA from EP devices. The BAR0/1 of bridge should be |
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* hidden during enumeration to avoid the sizing and resource allocation |
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* by PCIe core. |
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*/ |
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static bool xgene_pcie_hide_rc_bars(struct pci_bus *bus, int offset) |
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{ |
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if (pci_is_root_bus(bus) && ((offset == PCI_BASE_ADDRESS_0) || |
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(offset == PCI_BASE_ADDRESS_1))) |
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return true; |
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return false; |
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} |
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static void __iomem *xgene_pcie_map_bus(struct pci_bus *bus, unsigned int devfn, |
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int offset) |
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{ |
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if ((pci_is_root_bus(bus) && devfn != 0) || |
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xgene_pcie_hide_rc_bars(bus, offset)) |
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return NULL; |
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xgene_pcie_set_rtdid_reg(bus, devfn); |
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return xgene_pcie_get_cfg_base(bus) + offset; |
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} |
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static int xgene_pcie_config_read32(struct pci_bus *bus, unsigned int devfn, |
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int where, int size, u32 *val) |
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{ |
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struct xgene_pcie_port *port = pcie_bus_to_port(bus); |
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if (pci_generic_config_read32(bus, devfn, where & ~0x3, 4, val) != |
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PCIBIOS_SUCCESSFUL) |
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return PCIBIOS_DEVICE_NOT_FOUND; |
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/* |
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* The v1 controller has a bug in its Configuration Request |
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* Retry Status (CRS) logic: when CRS Software Visibility is |
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* enabled and we read the Vendor and Device ID of a non-existent |
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* device, the controller fabricates return data of 0xFFFF0001 |
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* ("device exists but is not ready") instead of 0xFFFFFFFF |
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* ("device does not exist"). This causes the PCI core to retry |
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* the read until it times out. Avoid this by not claiming to |
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* support CRS SV. |
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*/ |
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if (pci_is_root_bus(bus) && (port->version == XGENE_PCIE_IP_VER_1) && |
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((where & ~0x3) == XGENE_V1_PCI_EXP_CAP + PCI_EXP_RTCTL)) |
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*val &= ~(PCI_EXP_RTCAP_CRSVIS << 16); |
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if (size <= 2) |
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*val = (*val >> (8 * (where & 3))) & ((1 << (size * 8)) - 1); |
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return PCIBIOS_SUCCESSFUL; |
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} |
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#endif |
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#if defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS) |
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static int xgene_get_csr_resource(struct acpi_device *adev, |
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struct resource *res) |
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{ |
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struct device *dev = &adev->dev; |
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struct resource_entry *entry; |
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struct list_head list; |
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unsigned long flags; |
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int ret; |
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INIT_LIST_HEAD(&list); |
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flags = IORESOURCE_MEM; |
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ret = acpi_dev_get_resources(adev, &list, |
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acpi_dev_filter_resource_type_cb, |
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(void *) flags); |
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if (ret < 0) { |
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dev_err(dev, "failed to parse _CRS method, error code %d\n", |
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ret); |
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return ret; |
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} |
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if (ret == 0) { |
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dev_err(dev, "no IO and memory resources present in _CRS\n"); |
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return -EINVAL; |
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} |
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entry = list_first_entry(&list, struct resource_entry, node); |
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*res = *entry->res; |
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acpi_dev_free_resource_list(&list); |
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return 0; |
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} |
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static int xgene_pcie_ecam_init(struct pci_config_window *cfg, u32 ipversion) |
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{ |
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struct device *dev = cfg->parent; |
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struct acpi_device *adev = to_acpi_device(dev); |
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struct xgene_pcie_port *port; |
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struct resource csr; |
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int ret; |
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port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL); |
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if (!port) |
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return -ENOMEM; |
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ret = xgene_get_csr_resource(adev, &csr); |
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if (ret) { |
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dev_err(dev, "can't get CSR resource\n"); |
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return ret; |
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} |
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port->csr_base = devm_pci_remap_cfg_resource(dev, &csr); |
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if (IS_ERR(port->csr_base)) |
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return PTR_ERR(port->csr_base); |
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port->cfg_base = cfg->win; |
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port->version = ipversion; |
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cfg->priv = port; |
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return 0; |
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} |
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static int xgene_v1_pcie_ecam_init(struct pci_config_window *cfg) |
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{ |
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return xgene_pcie_ecam_init(cfg, XGENE_PCIE_IP_VER_1); |
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} |
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const struct pci_ecam_ops xgene_v1_pcie_ecam_ops = { |
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.init = xgene_v1_pcie_ecam_init, |
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.pci_ops = { |
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.map_bus = xgene_pcie_map_bus, |
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.read = xgene_pcie_config_read32, |
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.write = pci_generic_config_write, |
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} |
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}; |
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static int xgene_v2_pcie_ecam_init(struct pci_config_window *cfg) |
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{ |
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return xgene_pcie_ecam_init(cfg, XGENE_PCIE_IP_VER_2); |
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} |
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const struct pci_ecam_ops xgene_v2_pcie_ecam_ops = { |
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.init = xgene_v2_pcie_ecam_init, |
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.pci_ops = { |
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.map_bus = xgene_pcie_map_bus, |
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.read = xgene_pcie_config_read32, |
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.write = pci_generic_config_write, |
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} |
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}; |
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#endif |
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#if defined(CONFIG_PCI_XGENE) |
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static u64 xgene_pcie_set_ib_mask(struct xgene_pcie_port *port, u32 addr, |
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u32 flags, u64 size) |
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{ |
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u64 mask = (~(size - 1) & PCI_BASE_ADDRESS_MEM_MASK) | flags; |
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u32 val32 = 0; |
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u32 val; |
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val32 = xgene_pcie_readl(port, addr); |
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val = (val32 & 0x0000ffff) | (lower_32_bits(mask) << 16); |
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xgene_pcie_writel(port, addr, val); |
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val32 = xgene_pcie_readl(port, addr + 0x04); |
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val = (val32 & 0xffff0000) | (lower_32_bits(mask) >> 16); |
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xgene_pcie_writel(port, addr + 0x04, val); |
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val32 = xgene_pcie_readl(port, addr + 0x04); |
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val = (val32 & 0x0000ffff) | (upper_32_bits(mask) << 16); |
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xgene_pcie_writel(port, addr + 0x04, val); |
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val32 = xgene_pcie_readl(port, addr + 0x08); |
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val = (val32 & 0xffff0000) | (upper_32_bits(mask) >> 16); |
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xgene_pcie_writel(port, addr + 0x08, val); |
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return mask; |
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} |
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static void xgene_pcie_linkup(struct xgene_pcie_port *port, |
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u32 *lanes, u32 *speed) |
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{ |
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u32 val32; |
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port->link_up = false; |
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val32 = xgene_pcie_readl(port, PCIECORE_CTLANDSTATUS); |
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if (val32 & LINK_UP_MASK) { |
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port->link_up = true; |
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*speed = PIPE_PHY_RATE_RD(val32); |
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val32 = xgene_pcie_readl(port, BRIDGE_STATUS_0); |
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*lanes = val32 >> 26; |
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} |
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} |
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static int xgene_pcie_init_port(struct xgene_pcie_port *port) |
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{ |
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struct device *dev = port->dev; |
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int rc; |
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port->clk = clk_get(dev, NULL); |
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if (IS_ERR(port->clk)) { |
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dev_err(dev, "clock not available\n"); |
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return -ENODEV; |
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} |
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rc = clk_prepare_enable(port->clk); |
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if (rc) { |
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dev_err(dev, "clock enable failed\n"); |
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return rc; |
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} |
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return 0; |
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} |
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static int xgene_pcie_map_reg(struct xgene_pcie_port *port, |
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struct platform_device *pdev) |
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{ |
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struct device *dev = port->dev; |
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struct resource *res; |
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "csr"); |
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port->csr_base = devm_pci_remap_cfg_resource(dev, res); |
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if (IS_ERR(port->csr_base)) |
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return PTR_ERR(port->csr_base); |
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg"); |
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port->cfg_base = devm_ioremap_resource(dev, res); |
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if (IS_ERR(port->cfg_base)) |
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return PTR_ERR(port->cfg_base); |
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port->cfg_addr = res->start; |
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return 0; |
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} |
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static void xgene_pcie_setup_ob_reg(struct xgene_pcie_port *port, |
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struct resource *res, u32 offset, |
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u64 cpu_addr, u64 pci_addr) |
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{ |
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struct device *dev = port->dev; |
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resource_size_t size = resource_size(res); |
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u64 restype = resource_type(res); |
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u64 mask = 0; |
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u32 min_size; |
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u32 flag = EN_REG; |
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if (restype == IORESOURCE_MEM) { |
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min_size = SZ_128M; |
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} else { |
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min_size = 128; |
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flag |= OB_LO_IO; |
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} |
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if (size >= min_size) |
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mask = ~(size - 1) | flag; |
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else |
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dev_warn(dev, "res size 0x%llx less than minimum 0x%x\n", |
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(u64)size, min_size); |
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xgene_pcie_writel(port, offset, lower_32_bits(cpu_addr)); |
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xgene_pcie_writel(port, offset + 0x04, upper_32_bits(cpu_addr)); |
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xgene_pcie_writel(port, offset + 0x08, lower_32_bits(mask)); |
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xgene_pcie_writel(port, offset + 0x0c, upper_32_bits(mask)); |
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xgene_pcie_writel(port, offset + 0x10, lower_32_bits(pci_addr)); |
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xgene_pcie_writel(port, offset + 0x14, upper_32_bits(pci_addr)); |
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} |
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static void xgene_pcie_setup_cfg_reg(struct xgene_pcie_port *port) |
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{ |
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u64 addr = port->cfg_addr; |
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xgene_pcie_writel(port, CFGBARL, lower_32_bits(addr)); |
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xgene_pcie_writel(port, CFGBARH, upper_32_bits(addr)); |
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xgene_pcie_writel(port, CFGCTL, EN_REG); |
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} |
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static int xgene_pcie_map_ranges(struct xgene_pcie_port *port) |
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{ |
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struct pci_host_bridge *bridge = pci_host_bridge_from_priv(port); |
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struct resource_entry *window; |
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struct device *dev = port->dev; |
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resource_list_for_each_entry(window, &bridge->windows) { |
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struct resource *res = window->res; |
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u64 restype = resource_type(res); |
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dev_dbg(dev, "%pR\n", res); |
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switch (restype) { |
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case IORESOURCE_IO: |
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xgene_pcie_setup_ob_reg(port, res, OMR3BARL, |
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pci_pio_to_address(res->start), |
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res->start - window->offset); |
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break; |
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case IORESOURCE_MEM: |
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if (res->flags & IORESOURCE_PREFETCH) |
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xgene_pcie_setup_ob_reg(port, res, OMR2BARL, |
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res->start, |
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res->start - |
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window->offset); |
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else |
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xgene_pcie_setup_ob_reg(port, res, OMR1BARL, |
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res->start, |
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res->start - |
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window->offset); |
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break; |
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case IORESOURCE_BUS: |
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break; |
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default: |
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dev_err(dev, "invalid resource %pR\n", res); |
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return -EINVAL; |
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} |
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} |
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xgene_pcie_setup_cfg_reg(port); |
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return 0; |
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} |
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static void xgene_pcie_setup_pims(struct xgene_pcie_port *port, u32 pim_reg, |
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u64 pim, u64 size) |
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{ |
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xgene_pcie_writel(port, pim_reg, lower_32_bits(pim)); |
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xgene_pcie_writel(port, pim_reg + 0x04, |
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upper_32_bits(pim) | EN_COHERENCY); |
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xgene_pcie_writel(port, pim_reg + 0x10, lower_32_bits(size)); |
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xgene_pcie_writel(port, pim_reg + 0x14, upper_32_bits(size)); |
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} |
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|
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/* |
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* X-Gene PCIe support maximum 3 inbound memory regions |
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* This function helps to select a region based on size of region |
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*/ |
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static int xgene_pcie_select_ib_reg(u8 *ib_reg_mask, u64 size) |
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{ |
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if ((size > 4) && (size < SZ_16M) && !(*ib_reg_mask & (1 << 1))) { |
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*ib_reg_mask |= (1 << 1); |
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return 1; |
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} |
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|
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if ((size > SZ_1K) && (size < SZ_1T) && !(*ib_reg_mask & (1 << 0))) { |
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*ib_reg_mask |= (1 << 0); |
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return 0; |
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} |
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|
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if ((size > SZ_1M) && (size < SZ_1T) && !(*ib_reg_mask & (1 << 2))) { |
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*ib_reg_mask |= (1 << 2); |
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return 2; |
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} |
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|
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return -EINVAL; |
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} |
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|
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static void xgene_pcie_setup_ib_reg(struct xgene_pcie_port *port, |
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struct resource_entry *entry, |
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u8 *ib_reg_mask) |
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{ |
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void __iomem *cfg_base = port->cfg_base; |
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struct device *dev = port->dev; |
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void *bar_addr; |
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u32 pim_reg; |
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u64 cpu_addr = entry->res->start; |
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u64 pci_addr = cpu_addr - entry->offset; |
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u64 size = resource_size(entry->res); |
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u64 mask = ~(size - 1) | EN_REG; |
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u32 flags = PCI_BASE_ADDRESS_MEM_TYPE_64; |
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u32 bar_low; |
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int region; |
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|
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region = xgene_pcie_select_ib_reg(ib_reg_mask, size); |
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if (region < 0) { |
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dev_warn(dev, "invalid pcie dma-range config\n"); |
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return; |
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} |
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|
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if (entry->res->flags & IORESOURCE_PREFETCH) |
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flags |= PCI_BASE_ADDRESS_MEM_PREFETCH; |
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bar_low = pcie_bar_low_val((u32)cpu_addr, flags); |
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switch (region) { |
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case 0: |
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xgene_pcie_set_ib_mask(port, BRIDGE_CFG_4, flags, size); |
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bar_addr = cfg_base + PCI_BASE_ADDRESS_0; |
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writel(bar_low, bar_addr); |
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writel(upper_32_bits(cpu_addr), bar_addr + 0x4); |
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pim_reg = PIM1_1L; |
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break; |
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case 1: |
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xgene_pcie_writel(port, IBAR2, bar_low); |
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xgene_pcie_writel(port, IR2MSK, lower_32_bits(mask)); |
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pim_reg = PIM2_1L; |
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break; |
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case 2: |
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xgene_pcie_writel(port, IBAR3L, bar_low); |
|
xgene_pcie_writel(port, IBAR3L + 0x4, upper_32_bits(cpu_addr)); |
|
xgene_pcie_writel(port, IR3MSKL, lower_32_bits(mask)); |
|
xgene_pcie_writel(port, IR3MSKL + 0x4, upper_32_bits(mask)); |
|
pim_reg = PIM3_1L; |
|
break; |
|
} |
|
|
|
xgene_pcie_setup_pims(port, pim_reg, pci_addr, ~(size - 1)); |
|
} |
|
|
|
static int xgene_pcie_parse_map_dma_ranges(struct xgene_pcie_port *port) |
|
{ |
|
struct pci_host_bridge *bridge = pci_host_bridge_from_priv(port); |
|
struct resource_entry *entry; |
|
u8 ib_reg_mask = 0; |
|
|
|
resource_list_for_each_entry(entry, &bridge->dma_ranges) |
|
xgene_pcie_setup_ib_reg(port, entry, &ib_reg_mask); |
|
|
|
return 0; |
|
} |
|
|
|
/* clear BAR configuration which was done by firmware */ |
|
static void xgene_pcie_clear_config(struct xgene_pcie_port *port) |
|
{ |
|
int i; |
|
|
|
for (i = PIM1_1L; i <= CFGCTL; i += 4) |
|
xgene_pcie_writel(port, i, 0); |
|
} |
|
|
|
static int xgene_pcie_setup(struct xgene_pcie_port *port) |
|
{ |
|
struct device *dev = port->dev; |
|
u32 val, lanes = 0, speed = 0; |
|
int ret; |
|
|
|
xgene_pcie_clear_config(port); |
|
|
|
/* setup the vendor and device IDs correctly */ |
|
val = (XGENE_PCIE_DEVICEID << 16) | XGENE_PCIE_VENDORID; |
|
xgene_pcie_writel(port, BRIDGE_CFG_0, val); |
|
|
|
ret = xgene_pcie_map_ranges(port); |
|
if (ret) |
|
return ret; |
|
|
|
ret = xgene_pcie_parse_map_dma_ranges(port); |
|
if (ret) |
|
return ret; |
|
|
|
xgene_pcie_linkup(port, &lanes, &speed); |
|
if (!port->link_up) |
|
dev_info(dev, "(rc) link down\n"); |
|
else |
|
dev_info(dev, "(rc) x%d gen-%d link up\n", lanes, speed + 1); |
|
return 0; |
|
} |
|
|
|
static struct pci_ops xgene_pcie_ops = { |
|
.map_bus = xgene_pcie_map_bus, |
|
.read = xgene_pcie_config_read32, |
|
.write = pci_generic_config_write32, |
|
}; |
|
|
|
static int xgene_pcie_probe(struct platform_device *pdev) |
|
{ |
|
struct device *dev = &pdev->dev; |
|
struct device_node *dn = dev->of_node; |
|
struct xgene_pcie_port *port; |
|
struct pci_host_bridge *bridge; |
|
int ret; |
|
|
|
bridge = devm_pci_alloc_host_bridge(dev, sizeof(*port)); |
|
if (!bridge) |
|
return -ENOMEM; |
|
|
|
port = pci_host_bridge_priv(bridge); |
|
|
|
port->node = of_node_get(dn); |
|
port->dev = dev; |
|
|
|
port->version = XGENE_PCIE_IP_VER_UNKN; |
|
if (of_device_is_compatible(port->node, "apm,xgene-pcie")) |
|
port->version = XGENE_PCIE_IP_VER_1; |
|
|
|
ret = xgene_pcie_map_reg(port, pdev); |
|
if (ret) |
|
return ret; |
|
|
|
ret = xgene_pcie_init_port(port); |
|
if (ret) |
|
return ret; |
|
|
|
ret = xgene_pcie_setup(port); |
|
if (ret) |
|
return ret; |
|
|
|
bridge->sysdata = port; |
|
bridge->ops = &xgene_pcie_ops; |
|
|
|
return pci_host_probe(bridge); |
|
} |
|
|
|
static const struct of_device_id xgene_pcie_match_table[] = { |
|
{.compatible = "apm,xgene-pcie",}, |
|
{}, |
|
}; |
|
|
|
static struct platform_driver xgene_pcie_driver = { |
|
.driver = { |
|
.name = "xgene-pcie", |
|
.of_match_table = of_match_ptr(xgene_pcie_match_table), |
|
.suppress_bind_attrs = true, |
|
}, |
|
.probe = xgene_pcie_probe, |
|
}; |
|
builtin_platform_driver(xgene_pcie_driver); |
|
#endif
|
|
|