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647 lines
17 KiB
647 lines
17 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* Driver for the Texas Instruments DP83822, DP83825 and DP83826 PHYs. |
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* |
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* Copyright (C) 2017 Texas Instruments Inc. |
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*/ |
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#include <linux/ethtool.h> |
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#include <linux/etherdevice.h> |
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#include <linux/kernel.h> |
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#include <linux/mii.h> |
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#include <linux/module.h> |
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#include <linux/of.h> |
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#include <linux/phy.h> |
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#include <linux/netdevice.h> |
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#define DP83822_PHY_ID 0x2000a240 |
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#define DP83825S_PHY_ID 0x2000a140 |
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#define DP83825I_PHY_ID 0x2000a150 |
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#define DP83825CM_PHY_ID 0x2000a160 |
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#define DP83825CS_PHY_ID 0x2000a170 |
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#define DP83826C_PHY_ID 0x2000a130 |
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#define DP83826NC_PHY_ID 0x2000a110 |
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#define DP83822_DEVADDR 0x1f |
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#define MII_DP83822_CTRL_2 0x0a |
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#define MII_DP83822_PHYSTS 0x10 |
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#define MII_DP83822_PHYSCR 0x11 |
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#define MII_DP83822_MISR1 0x12 |
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#define MII_DP83822_MISR2 0x13 |
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#define MII_DP83822_FCSCR 0x14 |
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#define MII_DP83822_RCSR 0x17 |
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#define MII_DP83822_RESET_CTRL 0x1f |
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#define MII_DP83822_GENCFG 0x465 |
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#define MII_DP83822_SOR1 0x467 |
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/* GENCFG */ |
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#define DP83822_SIG_DET_LOW BIT(0) |
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/* Control Register 2 bits */ |
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#define DP83822_FX_ENABLE BIT(14) |
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#define DP83822_HW_RESET BIT(15) |
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#define DP83822_SW_RESET BIT(14) |
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/* PHY STS bits */ |
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#define DP83822_PHYSTS_DUPLEX BIT(2) |
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#define DP83822_PHYSTS_10 BIT(1) |
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#define DP83822_PHYSTS_LINK BIT(0) |
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/* PHYSCR Register Fields */ |
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#define DP83822_PHYSCR_INT_OE BIT(0) /* Interrupt Output Enable */ |
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#define DP83822_PHYSCR_INTEN BIT(1) /* Interrupt Enable */ |
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/* MISR1 bits */ |
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#define DP83822_RX_ERR_HF_INT_EN BIT(0) |
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#define DP83822_FALSE_CARRIER_HF_INT_EN BIT(1) |
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#define DP83822_ANEG_COMPLETE_INT_EN BIT(2) |
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#define DP83822_DUP_MODE_CHANGE_INT_EN BIT(3) |
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#define DP83822_SPEED_CHANGED_INT_EN BIT(4) |
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#define DP83822_LINK_STAT_INT_EN BIT(5) |
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#define DP83822_ENERGY_DET_INT_EN BIT(6) |
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#define DP83822_LINK_QUAL_INT_EN BIT(7) |
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/* MISR2 bits */ |
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#define DP83822_JABBER_DET_INT_EN BIT(0) |
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#define DP83822_WOL_PKT_INT_EN BIT(1) |
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#define DP83822_SLEEP_MODE_INT_EN BIT(2) |
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#define DP83822_MDI_XOVER_INT_EN BIT(3) |
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#define DP83822_LB_FIFO_INT_EN BIT(4) |
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#define DP83822_PAGE_RX_INT_EN BIT(5) |
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#define DP83822_ANEG_ERR_INT_EN BIT(6) |
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#define DP83822_EEE_ERROR_CHANGE_INT_EN BIT(7) |
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/* INT_STAT1 bits */ |
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#define DP83822_WOL_INT_EN BIT(4) |
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#define DP83822_WOL_INT_STAT BIT(12) |
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#define MII_DP83822_RXSOP1 0x04a5 |
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#define MII_DP83822_RXSOP2 0x04a6 |
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#define MII_DP83822_RXSOP3 0x04a7 |
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/* WoL Registers */ |
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#define MII_DP83822_WOL_CFG 0x04a0 |
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#define MII_DP83822_WOL_STAT 0x04a1 |
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#define MII_DP83822_WOL_DA1 0x04a2 |
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#define MII_DP83822_WOL_DA2 0x04a3 |
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#define MII_DP83822_WOL_DA3 0x04a4 |
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/* WoL bits */ |
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#define DP83822_WOL_MAGIC_EN BIT(0) |
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#define DP83822_WOL_SECURE_ON BIT(5) |
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#define DP83822_WOL_EN BIT(7) |
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#define DP83822_WOL_INDICATION_SEL BIT(8) |
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#define DP83822_WOL_CLR_INDICATION BIT(11) |
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/* RSCR bits */ |
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#define DP83822_RX_CLK_SHIFT BIT(12) |
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#define DP83822_TX_CLK_SHIFT BIT(11) |
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/* SOR1 mode */ |
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#define DP83822_STRAP_MODE1 0 |
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#define DP83822_STRAP_MODE2 BIT(0) |
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#define DP83822_STRAP_MODE3 BIT(1) |
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#define DP83822_STRAP_MODE4 GENMASK(1, 0) |
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#define DP83822_COL_STRAP_MASK GENMASK(11, 10) |
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#define DP83822_COL_SHIFT 10 |
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#define DP83822_RX_ER_STR_MASK GENMASK(9, 8) |
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#define DP83822_RX_ER_SHIFT 8 |
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#define MII_DP83822_FIBER_ADVERTISE (ADVERTISED_TP | ADVERTISED_MII | \ |
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ADVERTISED_FIBRE | \ |
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ADVERTISED_Pause | ADVERTISED_Asym_Pause) |
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struct dp83822_private { |
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bool fx_signal_det_low; |
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int fx_enabled; |
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u16 fx_sd_enable; |
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}; |
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static int dp83822_set_wol(struct phy_device *phydev, |
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struct ethtool_wolinfo *wol) |
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{ |
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struct net_device *ndev = phydev->attached_dev; |
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u16 value; |
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const u8 *mac; |
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if (wol->wolopts & (WAKE_MAGIC | WAKE_MAGICSECURE)) { |
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mac = (const u8 *)ndev->dev_addr; |
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if (!is_valid_ether_addr(mac)) |
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return -EINVAL; |
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/* MAC addresses start with byte 5, but stored in mac[0]. |
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* 822 PHYs store bytes 4|5, 2|3, 0|1 |
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*/ |
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phy_write_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_DA1, |
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(mac[1] << 8) | mac[0]); |
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phy_write_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_DA2, |
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(mac[3] << 8) | mac[2]); |
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phy_write_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_DA3, |
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(mac[5] << 8) | mac[4]); |
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value = phy_read_mmd(phydev, DP83822_DEVADDR, |
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MII_DP83822_WOL_CFG); |
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if (wol->wolopts & WAKE_MAGIC) |
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value |= DP83822_WOL_MAGIC_EN; |
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else |
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value &= ~DP83822_WOL_MAGIC_EN; |
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if (wol->wolopts & WAKE_MAGICSECURE) { |
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phy_write_mmd(phydev, DP83822_DEVADDR, |
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MII_DP83822_RXSOP1, |
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(wol->sopass[1] << 8) | wol->sopass[0]); |
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phy_write_mmd(phydev, DP83822_DEVADDR, |
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MII_DP83822_RXSOP2, |
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(wol->sopass[3] << 8) | wol->sopass[2]); |
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phy_write_mmd(phydev, DP83822_DEVADDR, |
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MII_DP83822_RXSOP3, |
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(wol->sopass[5] << 8) | wol->sopass[4]); |
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value |= DP83822_WOL_SECURE_ON; |
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} else { |
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value &= ~DP83822_WOL_SECURE_ON; |
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} |
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/* Clear any pending WoL interrupt */ |
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phy_read(phydev, MII_DP83822_MISR2); |
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value |= DP83822_WOL_EN | DP83822_WOL_INDICATION_SEL | |
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DP83822_WOL_CLR_INDICATION; |
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return phy_write_mmd(phydev, DP83822_DEVADDR, |
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MII_DP83822_WOL_CFG, value); |
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} else { |
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return phy_clear_bits_mmd(phydev, DP83822_DEVADDR, |
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MII_DP83822_WOL_CFG, DP83822_WOL_EN); |
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} |
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} |
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static void dp83822_get_wol(struct phy_device *phydev, |
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struct ethtool_wolinfo *wol) |
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{ |
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int value; |
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u16 sopass_val; |
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wol->supported = (WAKE_MAGIC | WAKE_MAGICSECURE); |
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wol->wolopts = 0; |
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value = phy_read_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_CFG); |
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if (value & DP83822_WOL_MAGIC_EN) |
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wol->wolopts |= WAKE_MAGIC; |
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if (value & DP83822_WOL_SECURE_ON) { |
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sopass_val = phy_read_mmd(phydev, DP83822_DEVADDR, |
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MII_DP83822_RXSOP1); |
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wol->sopass[0] = (sopass_val & 0xff); |
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wol->sopass[1] = (sopass_val >> 8); |
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sopass_val = phy_read_mmd(phydev, DP83822_DEVADDR, |
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MII_DP83822_RXSOP2); |
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wol->sopass[2] = (sopass_val & 0xff); |
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wol->sopass[3] = (sopass_val >> 8); |
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sopass_val = phy_read_mmd(phydev, DP83822_DEVADDR, |
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MII_DP83822_RXSOP3); |
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wol->sopass[4] = (sopass_val & 0xff); |
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wol->sopass[5] = (sopass_val >> 8); |
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wol->wolopts |= WAKE_MAGICSECURE; |
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} |
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/* WoL is not enabled so set wolopts to 0 */ |
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if (!(value & DP83822_WOL_EN)) |
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wol->wolopts = 0; |
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} |
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static int dp83822_config_intr(struct phy_device *phydev) |
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{ |
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struct dp83822_private *dp83822 = phydev->priv; |
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int misr_status; |
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int physcr_status; |
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int err; |
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if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { |
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misr_status = phy_read(phydev, MII_DP83822_MISR1); |
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if (misr_status < 0) |
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return misr_status; |
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misr_status |= (DP83822_RX_ERR_HF_INT_EN | |
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DP83822_FALSE_CARRIER_HF_INT_EN | |
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DP83822_LINK_STAT_INT_EN | |
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DP83822_ENERGY_DET_INT_EN | |
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DP83822_LINK_QUAL_INT_EN); |
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if (!dp83822->fx_enabled) |
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misr_status |= DP83822_ANEG_COMPLETE_INT_EN | |
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DP83822_DUP_MODE_CHANGE_INT_EN | |
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DP83822_SPEED_CHANGED_INT_EN; |
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err = phy_write(phydev, MII_DP83822_MISR1, misr_status); |
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if (err < 0) |
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return err; |
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misr_status = phy_read(phydev, MII_DP83822_MISR2); |
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if (misr_status < 0) |
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return misr_status; |
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misr_status |= (DP83822_JABBER_DET_INT_EN | |
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DP83822_SLEEP_MODE_INT_EN | |
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DP83822_LB_FIFO_INT_EN | |
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DP83822_PAGE_RX_INT_EN | |
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DP83822_EEE_ERROR_CHANGE_INT_EN); |
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if (!dp83822->fx_enabled) |
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misr_status |= DP83822_MDI_XOVER_INT_EN | |
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DP83822_ANEG_ERR_INT_EN | |
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DP83822_WOL_PKT_INT_EN; |
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err = phy_write(phydev, MII_DP83822_MISR2, misr_status); |
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if (err < 0) |
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return err; |
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physcr_status = phy_read(phydev, MII_DP83822_PHYSCR); |
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if (physcr_status < 0) |
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return physcr_status; |
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physcr_status |= DP83822_PHYSCR_INT_OE | DP83822_PHYSCR_INTEN; |
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} else { |
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err = phy_write(phydev, MII_DP83822_MISR1, 0); |
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if (err < 0) |
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return err; |
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err = phy_write(phydev, MII_DP83822_MISR1, 0); |
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if (err < 0) |
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return err; |
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physcr_status = phy_read(phydev, MII_DP83822_PHYSCR); |
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if (physcr_status < 0) |
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return physcr_status; |
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physcr_status &= ~DP83822_PHYSCR_INTEN; |
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} |
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return phy_write(phydev, MII_DP83822_PHYSCR, physcr_status); |
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} |
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static irqreturn_t dp83822_handle_interrupt(struct phy_device *phydev) |
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{ |
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bool trigger_machine = false; |
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int irq_status; |
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/* The MISR1 and MISR2 registers are holding the interrupt status in |
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* the upper half (15:8), while the lower half (7:0) is used for |
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* controlling the interrupt enable state of those individual interrupt |
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* sources. To determine the possible interrupt sources, just read the |
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* MISR* register and use it directly to know which interrupts have |
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* been enabled previously or not. |
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*/ |
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irq_status = phy_read(phydev, MII_DP83822_MISR1); |
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if (irq_status < 0) { |
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phy_error(phydev); |
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return IRQ_NONE; |
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} |
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if (irq_status & ((irq_status & GENMASK(7, 0)) << 8)) |
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trigger_machine = true; |
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irq_status = phy_read(phydev, MII_DP83822_MISR2); |
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if (irq_status < 0) { |
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phy_error(phydev); |
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return IRQ_NONE; |
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} |
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if (irq_status & ((irq_status & GENMASK(7, 0)) << 8)) |
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trigger_machine = true; |
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if (!trigger_machine) |
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return IRQ_NONE; |
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phy_trigger_machine(phydev); |
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return IRQ_HANDLED; |
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} |
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static int dp8382x_disable_wol(struct phy_device *phydev) |
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{ |
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int value = DP83822_WOL_EN | DP83822_WOL_MAGIC_EN | |
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DP83822_WOL_SECURE_ON; |
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return phy_clear_bits_mmd(phydev, DP83822_DEVADDR, |
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MII_DP83822_WOL_CFG, value); |
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} |
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static int dp83822_read_status(struct phy_device *phydev) |
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{ |
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struct dp83822_private *dp83822 = phydev->priv; |
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int status = phy_read(phydev, MII_DP83822_PHYSTS); |
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int ctrl2; |
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int ret; |
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if (dp83822->fx_enabled) { |
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if (status & DP83822_PHYSTS_LINK) { |
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phydev->speed = SPEED_UNKNOWN; |
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phydev->duplex = DUPLEX_UNKNOWN; |
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} else { |
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ctrl2 = phy_read(phydev, MII_DP83822_CTRL_2); |
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if (ctrl2 < 0) |
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return ctrl2; |
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if (!(ctrl2 & DP83822_FX_ENABLE)) { |
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ret = phy_write(phydev, MII_DP83822_CTRL_2, |
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DP83822_FX_ENABLE | ctrl2); |
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if (ret < 0) |
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return ret; |
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} |
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} |
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} |
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ret = genphy_read_status(phydev); |
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if (ret) |
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return ret; |
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if (status < 0) |
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return status; |
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if (status & DP83822_PHYSTS_DUPLEX) |
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phydev->duplex = DUPLEX_FULL; |
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else |
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phydev->duplex = DUPLEX_HALF; |
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if (status & DP83822_PHYSTS_10) |
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phydev->speed = SPEED_10; |
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else |
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phydev->speed = SPEED_100; |
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return 0; |
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} |
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static int dp83822_config_init(struct phy_device *phydev) |
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{ |
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struct dp83822_private *dp83822 = phydev->priv; |
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struct device *dev = &phydev->mdio.dev; |
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int rgmii_delay; |
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s32 rx_int_delay; |
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s32 tx_int_delay; |
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int err = 0; |
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int bmcr; |
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if (phy_interface_is_rgmii(phydev)) { |
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rx_int_delay = phy_get_internal_delay(phydev, dev, NULL, 0, |
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true); |
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if (rx_int_delay <= 0) |
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rgmii_delay = 0; |
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else |
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rgmii_delay = DP83822_RX_CLK_SHIFT; |
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tx_int_delay = phy_get_internal_delay(phydev, dev, NULL, 0, |
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false); |
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if (tx_int_delay <= 0) |
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rgmii_delay &= ~DP83822_TX_CLK_SHIFT; |
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else |
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rgmii_delay |= DP83822_TX_CLK_SHIFT; |
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if (rgmii_delay) { |
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err = phy_set_bits_mmd(phydev, DP83822_DEVADDR, |
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MII_DP83822_RCSR, rgmii_delay); |
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if (err) |
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return err; |
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} |
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} |
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if (dp83822->fx_enabled) { |
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err = phy_modify(phydev, MII_DP83822_CTRL_2, |
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DP83822_FX_ENABLE, 1); |
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if (err < 0) |
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return err; |
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/* Only allow advertising what this PHY supports */ |
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linkmode_and(phydev->advertising, phydev->advertising, |
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phydev->supported); |
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linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, |
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phydev->supported); |
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linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, |
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phydev->advertising); |
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linkmode_set_bit(ETHTOOL_LINK_MODE_100baseFX_Full_BIT, |
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phydev->supported); |
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linkmode_set_bit(ETHTOOL_LINK_MODE_100baseFX_Half_BIT, |
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phydev->supported); |
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linkmode_set_bit(ETHTOOL_LINK_MODE_100baseFX_Full_BIT, |
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phydev->advertising); |
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linkmode_set_bit(ETHTOOL_LINK_MODE_100baseFX_Half_BIT, |
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phydev->advertising); |
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/* Auto neg is not supported in fiber mode */ |
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bmcr = phy_read(phydev, MII_BMCR); |
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if (bmcr < 0) |
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return bmcr; |
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if (bmcr & BMCR_ANENABLE) { |
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err = phy_modify(phydev, MII_BMCR, BMCR_ANENABLE, 0); |
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if (err < 0) |
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return err; |
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} |
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phydev->autoneg = AUTONEG_DISABLE; |
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linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, |
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phydev->supported); |
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linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, |
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phydev->advertising); |
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|
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/* Setup fiber advertisement */ |
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err = phy_modify_changed(phydev, MII_ADVERTISE, |
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MII_DP83822_FIBER_ADVERTISE, |
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MII_DP83822_FIBER_ADVERTISE); |
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if (err < 0) |
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return err; |
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if (dp83822->fx_signal_det_low) { |
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err = phy_set_bits_mmd(phydev, DP83822_DEVADDR, |
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MII_DP83822_GENCFG, |
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DP83822_SIG_DET_LOW); |
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if (err) |
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return err; |
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} |
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} |
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return dp8382x_disable_wol(phydev); |
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} |
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static int dp8382x_config_init(struct phy_device *phydev) |
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{ |
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return dp8382x_disable_wol(phydev); |
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} |
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static int dp83822_phy_reset(struct phy_device *phydev) |
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{ |
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int err; |
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err = phy_write(phydev, MII_DP83822_RESET_CTRL, DP83822_SW_RESET); |
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if (err < 0) |
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return err; |
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return phydev->drv->config_init(phydev); |
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} |
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#ifdef CONFIG_OF_MDIO |
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static int dp83822_of_init(struct phy_device *phydev) |
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{ |
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struct dp83822_private *dp83822 = phydev->priv; |
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struct device *dev = &phydev->mdio.dev; |
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|
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/* Signal detection for the PHY is only enabled if the FX_EN and the |
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* SD_EN pins are strapped. Signal detection can only enabled if FX_EN |
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* is strapped otherwise signal detection is disabled for the PHY. |
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*/ |
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if (dp83822->fx_enabled && dp83822->fx_sd_enable) |
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dp83822->fx_signal_det_low = device_property_present(dev, |
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"ti,link-loss-low"); |
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if (!dp83822->fx_enabled) |
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dp83822->fx_enabled = device_property_present(dev, |
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"ti,fiber-mode"); |
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return 0; |
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} |
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#else |
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static int dp83822_of_init(struct phy_device *phydev) |
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{ |
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return 0; |
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} |
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#endif /* CONFIG_OF_MDIO */ |
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|
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static int dp83822_read_straps(struct phy_device *phydev) |
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{ |
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struct dp83822_private *dp83822 = phydev->priv; |
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int fx_enabled, fx_sd_enable; |
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int val; |
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|
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val = phy_read_mmd(phydev, DP83822_DEVADDR, MII_DP83822_SOR1); |
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if (val < 0) |
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return val; |
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|
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fx_enabled = (val & DP83822_COL_STRAP_MASK) >> DP83822_COL_SHIFT; |
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if (fx_enabled == DP83822_STRAP_MODE2 || |
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fx_enabled == DP83822_STRAP_MODE3) |
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dp83822->fx_enabled = 1; |
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|
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if (dp83822->fx_enabled) { |
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fx_sd_enable = (val & DP83822_RX_ER_STR_MASK) >> DP83822_RX_ER_SHIFT; |
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if (fx_sd_enable == DP83822_STRAP_MODE3 || |
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fx_sd_enable == DP83822_STRAP_MODE4) |
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dp83822->fx_sd_enable = 1; |
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} |
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|
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return 0; |
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} |
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|
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static int dp83822_probe(struct phy_device *phydev) |
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{ |
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struct dp83822_private *dp83822; |
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int ret; |
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|
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dp83822 = devm_kzalloc(&phydev->mdio.dev, sizeof(*dp83822), |
|
GFP_KERNEL); |
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if (!dp83822) |
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return -ENOMEM; |
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|
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phydev->priv = dp83822; |
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|
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ret = dp83822_read_straps(phydev); |
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if (ret) |
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return ret; |
|
|
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dp83822_of_init(phydev); |
|
|
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if (dp83822->fx_enabled) |
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phydev->port = PORT_FIBRE; |
|
|
|
return 0; |
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} |
|
|
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static int dp83822_suspend(struct phy_device *phydev) |
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{ |
|
int value; |
|
|
|
value = phy_read_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_CFG); |
|
|
|
if (!(value & DP83822_WOL_EN)) |
|
genphy_suspend(phydev); |
|
|
|
return 0; |
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} |
|
|
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static int dp83822_resume(struct phy_device *phydev) |
|
{ |
|
int value; |
|
|
|
genphy_resume(phydev); |
|
|
|
value = phy_read_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_CFG); |
|
|
|
phy_write_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_CFG, value | |
|
DP83822_WOL_CLR_INDICATION); |
|
|
|
return 0; |
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} |
|
|
|
#define DP83822_PHY_DRIVER(_id, _name) \ |
|
{ \ |
|
PHY_ID_MATCH_MODEL(_id), \ |
|
.name = (_name), \ |
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/* PHY_BASIC_FEATURES */ \ |
|
.probe = dp83822_probe, \ |
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.soft_reset = dp83822_phy_reset, \ |
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.config_init = dp83822_config_init, \ |
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.read_status = dp83822_read_status, \ |
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.get_wol = dp83822_get_wol, \ |
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.set_wol = dp83822_set_wol, \ |
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.config_intr = dp83822_config_intr, \ |
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.handle_interrupt = dp83822_handle_interrupt, \ |
|
.suspend = dp83822_suspend, \ |
|
.resume = dp83822_resume, \ |
|
} |
|
|
|
#define DP8382X_PHY_DRIVER(_id, _name) \ |
|
{ \ |
|
PHY_ID_MATCH_MODEL(_id), \ |
|
.name = (_name), \ |
|
/* PHY_BASIC_FEATURES */ \ |
|
.soft_reset = dp83822_phy_reset, \ |
|
.config_init = dp8382x_config_init, \ |
|
.get_wol = dp83822_get_wol, \ |
|
.set_wol = dp83822_set_wol, \ |
|
.config_intr = dp83822_config_intr, \ |
|
.handle_interrupt = dp83822_handle_interrupt, \ |
|
.suspend = dp83822_suspend, \ |
|
.resume = dp83822_resume, \ |
|
} |
|
|
|
static struct phy_driver dp83822_driver[] = { |
|
DP83822_PHY_DRIVER(DP83822_PHY_ID, "TI DP83822"), |
|
DP8382X_PHY_DRIVER(DP83825I_PHY_ID, "TI DP83825I"), |
|
DP8382X_PHY_DRIVER(DP83826C_PHY_ID, "TI DP83826C"), |
|
DP8382X_PHY_DRIVER(DP83826NC_PHY_ID, "TI DP83826NC"), |
|
DP8382X_PHY_DRIVER(DP83825S_PHY_ID, "TI DP83825S"), |
|
DP8382X_PHY_DRIVER(DP83825CM_PHY_ID, "TI DP83825M"), |
|
DP8382X_PHY_DRIVER(DP83825CS_PHY_ID, "TI DP83825CS"), |
|
}; |
|
module_phy_driver(dp83822_driver); |
|
|
|
static struct mdio_device_id __maybe_unused dp83822_tbl[] = { |
|
{ DP83822_PHY_ID, 0xfffffff0 }, |
|
{ DP83825I_PHY_ID, 0xfffffff0 }, |
|
{ DP83826C_PHY_ID, 0xfffffff0 }, |
|
{ DP83826NC_PHY_ID, 0xfffffff0 }, |
|
{ DP83825S_PHY_ID, 0xfffffff0 }, |
|
{ DP83825CM_PHY_ID, 0xfffffff0 }, |
|
{ DP83825CS_PHY_ID, 0xfffffff0 }, |
|
{ }, |
|
}; |
|
MODULE_DEVICE_TABLE(mdio, dp83822_tbl); |
|
|
|
MODULE_DESCRIPTION("Texas Instruments DP83822 PHY driver"); |
|
MODULE_AUTHOR("Dan Murphy <[email protected]"); |
|
MODULE_LICENSE("GPL v2");
|
|
|